From patchwork Tue Mar 28 01:00:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 66975 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1A8B33858C62 for ; Tue, 28 Mar 2023 01:01:38 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgeu1.qq.com (smtpbgeu1.qq.com [52.59.177.22]) by sourceware.org (Postfix) with ESMTPS id 244E53858D39 for ; Tue, 28 Mar 2023 01:01:00 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 244E53858D39 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp63t1679965213tcfp3d0q Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 28 Mar 2023 09:00:12 +0800 (CST) X-QQ-SSF: 01400000000000E0O000000A0000000 X-QQ-FEAT: hS2fwqriTaieP4GqVZCBjjCJ1UL/vsli X-QQ-GoodBg: 2 X-BIZMAIL-ID: 15964566336170335725 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Eliminate redundant vsetvli for duplicate AVL def Date: Tue, 28 Mar 2023 09:00:10 +0800 Message-Id: <20230328010010.235224-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_PASS, TXREP, T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Juzhe-Zhong void f (int8_t* base1,int8_t* base2,int8_t* out,int n) { vint8mf4_t v = __riscv_vle8_v_i8mf4 (base1, 32); for (int i = 0; i < n; i++){ v = __riscv_vor_vx_i8mf4 (v, 101, 32); v = __riscv_vle8_v_i8mf4_tu (v, base2, 32); } __riscv_vse8_v_i8mf4 (out, v, 32); } before this patch: f: li a5,32 vsetvli zero,a5,e8,mf4,tu,ma vle8.v v1,0(a0) ble a3,zero,.L2 li t0,0 li a0,101 .L3: addiw t0,t0,1 vor.vx v1,v1,a0 vle8.v v1,0(a1) bne a3,t0,.L3 .L2: vsetvli zero,zero,e8,mf4,tu,ma vse8.v v1,0(a2) ret afther this patch: f: li a5,32 vsetvli zero,a5,e8,mf4,tu,ma vle8.v v1,0(a0) ble a3,zero,.L2 li t0,0 li a0,101 .L3: addiw t0,t0,1 vor.vx v1,v1,a0 vle8.v v1,0(a1) bne a3,t0,.L3 .L2: vse8.v v1,0(a2) ret gcc/ChangeLog: * config/riscv/riscv-vsetvl.cc (vector_infos_manager::all_avail_in_compatible_p): New function. (pass_vsetvl::refine_vsetvls): Remove redundant vsetvli. * config/riscv/riscv-vsetvl.h: New function declare. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vsetvl/avl_single-102.c: New test. --- gcc/config/riscv/riscv-vsetvl.cc | 67 ++++++++++++++++++- gcc/config/riscv/riscv-vsetvl.h | 1 + .../riscv/rvv/vsetvl/avl_single-102.c | 16 +++++ 3 files changed, 81 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index 4948e5d4c5e..58568b45010 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -2376,6 +2376,23 @@ vector_infos_manager::all_empty_predecessor_p (const basic_block cfg_bb) const return true; } +bool +vector_infos_manager::all_avail_in_compatible_p (const basic_block cfg_bb) const +{ + const auto &info = vector_block_infos[cfg_bb->index].local_dem; + sbitmap avin = vector_avin[cfg_bb->index]; + unsigned int bb_index; + sbitmap_iterator sbi; + EXECUTE_IF_SET_IN_BITMAP (avin, 0, bb_index, sbi) + { + const auto &avin_info + = static_cast (*vector_exprs[bb_index]); + if (!info.compatible_p (avin_info)) + return false; + } + return true; +} + bool vector_infos_manager::all_same_avl_p (const basic_block cfg_bb, sbitmap bitdata) const @@ -3741,9 +3758,53 @@ pass_vsetvl::refine_vsetvls (void) const m_vector_manager->to_refine_vsetvls.add (rinsn); continue; } - rinsn = PREV_INSN (rinsn); - rtx new_pat = gen_vsetvl_pat (VSETVL_VTYPE_CHANGE_ONLY, info, NULL_RTX); - change_insn (rinsn, new_pat); + + /* Optimize such case: + void f (int8_t* base1,int8_t* base2,int8_t* out,int n) + { + vint8mf4_t v = __riscv_vle8_v_i8mf4 (base1, 32); + for (int i = 0; i < n; i++){ + v = __riscv_vor_vx_i8mf4 (v, 101, 32); + v = __riscv_vle8_v_i8mf4_tu (v, base2, 32); + } + __riscv_vse8_v_i8mf4 (out, v, 32); + } + + f: + li a5,32 + vsetvli zero,a5,e8,mf4,tu,ma + vle8.v v1,0(a0) + ble a3,zero,.L2 + li t0,0 + li a0,101 + .L3: + addiw t0,t0,1 + vor.vx v1,v1,a0 + vle8.v v1,0(a1) + bne a3,t0,.L3 + .L2: + vsetvli zero,zero,e8,mf4,tu,ma + vse8.v v1,0(a2) + ret + + The second vsetvli is redundant. */ + + gcc_assert (has_vtype_op (insn->rtl ())); + rinsn = PREV_INSN (insn->rtl ()); + gcc_assert (vector_config_insn_p (PREV_INSN (insn->rtl ()))); + if (m_vector_manager->all_avail_in_compatible_p (cfg_bb)) + { + size_t id = m_vector_manager->get_expr_id (info); + if (bitmap_bit_p (m_vector_manager->vector_del[cfg_bb->index], id)) + continue; + eliminate_insn (rinsn); + } + else + { + rtx new_pat + = gen_vsetvl_pat (VSETVL_VTYPE_CHANGE_ONLY, info, NULL_RTX); + change_insn (rinsn, new_pat); + } } } diff --git a/gcc/config/riscv/riscv-vsetvl.h b/gcc/config/riscv/riscv-vsetvl.h index eec03d35071..d05472c86a0 100644 --- a/gcc/config/riscv/riscv-vsetvl.h +++ b/gcc/config/riscv/riscv-vsetvl.h @@ -451,6 +451,7 @@ public: bool all_same_ratio_p (sbitmap) const; bool all_empty_predecessor_p (const basic_block) const; + bool all_avail_in_compatible_p (const basic_block) const; void release (void); void create_bitmap_vectors (void); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c new file mode 100644 index 00000000000..8236d4e7f18 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-102.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */ + +#include "riscv_vector.h" + +void f (int8_t* base1,int8_t* base2,int8_t* out,int n) +{ + vint8mf4_t v = __riscv_vle8_v_i8mf4 (base1, 32); + for (int i = 0; i < n; i++){ + v = __riscv_vor_vx_i8mf4 (v, 101, 32); + v = __riscv_vle8_v_i8mf4_tu (v, base2, 32); + } + __riscv_vse8_v_i8mf4 (out, v, 32); +} + +/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */