From patchwork Sat Mar 25 12:14:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Li, Pan2 via Gcc-patches" X-Patchwork-Id: 66884 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A73C3385B512 for ; Sat, 25 Mar 2023 12:15:10 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A73C3385B512 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1679746510; bh=jWEQZHhQqIVNhl47U9EeIqoHE89h4bportp67AGIEa0=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=dSyzsE74OyUfPnydSupJbAZlFNua+tCB+ST/KcfAk1FPyRaMkR0Tjdlvq2OHQOO89 4jcjeyMm/8iVq6giohC7vE0eXk+rrQ4ytC/phczHXmZkl2qrOY4z3Vs/tIex8BF5Q4 YlhG3HJE5sJiY9UM3T+ydix3KBo777eOiQWb9k9o= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by sourceware.org (Postfix) with ESMTPS id E21F73858D20 for ; Sat, 25 Mar 2023 12:14:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E21F73858D20 X-IronPort-AV: E=McAfee;i="6600,9927,10659"; a="341536478" X-IronPort-AV: E=Sophos;i="5.98,290,1673942400"; d="scan'208";a="341536478" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Mar 2023 05:14:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10659"; a="806979386" X-IronPort-AV: E=Sophos;i="5.98,290,1673942400"; d="scan'208";a="806979386" Received: from pli-ubuntu.sh.intel.com ([10.239.46.88]) by orsmga004.jf.intel.com with ESMTP; 25 Mar 2023 05:14:39 -0700 To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@sifive.com, pan2.li@intel.com, hongtao.liu@intel.com Subject: [PATCH v2] RISCV: Bugfix for wrong code with v16hi compare & mask Date: Sat, 25 Mar 2023 20:14:32 +0800 Message-Id: <20230325121432.3203674-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230324141157.1646192-1-pan2.li@intel.com> References: <20230324141157.1646192-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "pan2.li--- via Gcc-patches" From: "Li, Pan2 via Gcc-patches" Reply-To: pan2.li@intel.com Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: yes Fix the bug of the incorrect code generation for the below code sample. typedef unsigned short __attribute__((__vector_size__ (32))) V; typedef unsigned short u16; void foo (V m, u16 *ret) { V v = 6 > ((V) { 2049, 8 } & m); *ret = v[0]; // + a + b + c + d; } Before this patch. addi sp,sp,-64 ld a5,0(a0) li a4,528384 addi a4,a4,-2047 and a5,a5,a4 // slli a5,a5,48 <- eliminated by mistake.. // srli a5,a5,48 <- eliminated by mistake. sltiu a5,a5,6 negw a5,a5 sh a5,0(a1) After this patch. addi sp,sp,-64 ld a5,0(a0) li a4,528384 addi a4,a4,-2047 and a5,a5,a4 slli a5,a5,48 srli a5,a5,48 sltiu a5,a5,6 negw a5,a5 sh a5,0(a1) The simplify_comparation for the AND operation will try to simplify below RTL code from: (and:DI (subreg:DI (reg:HI 154) 0) (const_int 0x801)) to: (subreg:DI (and (reg:HI 154) (const_int 0x801)) 0) If reg:HI 154 is 0x801 and reg:DI 154 is 0x80801, the RTL will be simplified continuely to: (subreg:DI (reg:HI 154) 0) That will loss the chance to clean the upper bits of the reg:DI 154, which result in the slli/srli to be eliminated. This patch will try 2 times when simplify_gen_binary for both the reg:HI 154 and the reg:DI 154, and only perform the operation if the returned simplified RTX equals. PR 109040 gcc/ChangeLog: * combine.cc (simplify_comparison): gcc/testsuite/ChangeLog: * gcc.dg/pr109040.c: New test. Signed-off-by: yes --- gcc/combine.cc | 14 +++++++++++--- gcc/testsuite/gcc.target/riscv/pr109040.c | 14 ++++++++++++++ 2 files changed, 25 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/pr109040.c diff --git a/gcc/combine.cc b/gcc/combine.cc index 053879500b7..7a62c95ddc8 100644 --- a/gcc/combine.cc +++ b/gcc/combine.cc @@ -12681,10 +12681,18 @@ simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1) && c1 != mask && c1 != GET_MODE_MASK (tmode)) { - op0 = simplify_gen_binary (AND, tmode, - SUBREG_REG (XEXP (op0, 0)), + rtx op0_exp0 = XEXP (op0, 0); + machine_mode op0_exp0_mode = GET_MODE (op0_exp0); + rtx op0_subreg = simplify_gen_binary (AND, tmode, + SUBREG_REG (op0_exp0), gen_int_mode (c1, tmode)); - op0 = gen_lowpart (mode, op0); + rtx op0_reg = simplify_gen_binary (AND, GET_MODE (op0_exp0), + op0_exp0, + gen_int_mode (c1, op0_exp0_mode)); + if (!rtx_equal_p (op0_subreg, op0_reg)) + break; + + op0 = gen_lowpart (mode, op0_reg); continue; } } diff --git a/gcc/testsuite/gcc.target/riscv/pr109040.c b/gcc/testsuite/gcc.target/riscv/pr109040.c new file mode 100644 index 00000000000..3b72ab319b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr109040.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64 -O2 -fno-schedule-insns -fno-schedule-insns2" } */ + +typedef unsigned short __attribute__((__vector_size__ (32))) V; +typedef unsigned short u16; + +void +foo (V m, u16 *ret) +{ + V v = 6 > ((V) { 2049, 8 } & m); + *ret = v[0]; +} + +/* { dg-final { scan-assembler-times {slli\s+a[0-9]+,\s*a[0-9]+,\s*48\s+srli\s+a[0-9]+,\s*a[0-9]+,\s*48} 1 } } */