From patchwork Fri Mar 24 01:53:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Feng Wang X-Patchwork-Id: 66830 X-Patchwork-Delegate: jlaw@ventanamicro.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B5AFD3876890 for ; Fri, 24 Mar 2023 01:54:02 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from zg8tmtyylji0my4xnjqumte4.icoremail.net (zg8tmtyylji0my4xnjqumte4.icoremail.net [162.243.164.118]) by sourceware.org (Postfix) with ESMTP id 4219E38754BB for ; Fri, 24 Mar 2023 01:53:46 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4219E38754BB Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from localhost.localdomain (unknown [10.12.130.31]) by app1 (Coremail) with SMTP id EwgMCgB3FcWWAh1kHUEAAA--.2347S4; Fri, 24 Mar 2023 09:53:26 +0800 (CST) From: Feng Wang To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, Feng Wang Subject: [PATCH] RISC-V: Optimize zbb ins sext.b and sext.h in rv64 Date: Fri, 24 Mar 2023 01:53:24 +0000 Message-Id: <20230324015324.13616-1-wangfeng@eswincomputing.com> X-Mailer: git-send-email 2.17.1 X-CM-TRANSID: EwgMCgB3FcWWAh1kHUEAAA--.2347S4 X-Coremail-Antispam: 1UD129KBjvJXoWxJr17AF1fZFy3Gw4Dtw47Jwb_yoW5Jr48pa y7Gr42grs7JFsxKw1fK3WxWws5Ars7KFyYvws7Cr12va15Jr9Yga18trWayF4UJF4UXrya 9r4xur1a9a4Yq37anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkF14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26F4U JVW0owA2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oV Cq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0 I7IYx2IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r 4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY02Avz4vE-syl42xK 82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGw C20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48J MIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMI IF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E 87Iv6xkF7I0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x0JUdEfOUUUUU= X-CM-SenderInfo: pzdqwwxhqjqvxvzl0uprps33xlqjhudrp/ X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_NUMSUBJECT, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This patch optimize the combine processing for sext.b/h in rv64. Please refer to the following test case, int sextb32(int x) { return (x << 24) >> 24; } The rtl expression is as follows, (insn 6 3 7 2 (set (reg:SI 138) (ashift:SI (subreg/s/u:SI (reg/v:DI 136 [ xD.2271 ]) 0) (const_int 24 [0x18]))) "sextb.c":2:13 195 {ashlsi3} (expr_list:REG_DEAD (reg/v:DI 136 [ xD.2271 ]) (nil))) (insn 7 6 8 2 (set (reg:SI 137) (ashiftrt:SI (reg:SI 138) (const_int 24 [0x18]))) "sextb.c":2:20 196 {ashrsi3} (expr_list:REG_DEAD (reg:SI 138) (nil))) During the combine phase, they will combine into (set (reg:SI 137) (ashiftrt:SI (subreg:SI (ashift:DI (reg:DI 140) (const_int 24 [0x18])) 0) (const_int 24 [0x18]))) The optimal combine result is (set (reg:SI 137) (sign_extend:SI (subreg:QI (reg:DI 140) 0))) This can be converted to the sext ins. Due to the influence of subreg,the current processing can't obtain the imm of left shifts. Need to peel off another layer of rtl to obtain it. gcc/ChangeLog: * combine.cc (extract_left_shift): Add SUBREG case. gcc/testsuite/ChangeLog: * gcc.target/riscv/zbb-sext-rv64.c: New test. --- gcc/combine.cc | 5 +++++ gcc/testsuite/gcc.target/riscv/zbb-sext-rv64.c | 12 ++++++++++++ 2 files changed, 17 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-sext-rv64.c diff --git a/gcc/combine.cc b/gcc/combine.cc index 053879500b7..fb396a3d974 100644 --- a/gcc/combine.cc +++ b/gcc/combine.cc @@ -7915,6 +7915,11 @@ extract_left_shift (scalar_int_mode mode, rtx x, int count) switch (code) { + case SUBREG: + x = XEXP (x, 0); + if (GET_CODE(x) != ASHIFT) + break; + case ASHIFT: /* This is the shift itself. If it is wide enough, we will return either the value being shifted if the shift count is equal to diff --git a/gcc/testsuite/gcc.target/riscv/zbb-sext-rv64.c b/gcc/testsuite/gcc.target/riscv/zbb-sext-rv64.c new file mode 100644 index 00000000000..4086ee56f57 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbb-sext-rv64.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64g_zbb -mabi=lp64d -O2" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +int sextb32(int x) +{ return (x << 24) >> 24; } + +int sexth32(int x) +{ return (x << 16) >> 16; } + +/* { dg-final { scan-assembler "sext.b" } } */ +/* { dg-final { scan-assembler "sext.h" } } */ \ No newline at end of file