From patchwork Wed Mar 15 06:37:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 66399 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2443E385B517 for ; Wed, 15 Mar 2023 06:38:26 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg151.qq.com (smtpbg151.qq.com [18.169.211.239]) by sourceware.org (Postfix) with ESMTPS id 14CB83858D20 for ; Wed, 15 Mar 2023 06:37:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 14CB83858D20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp68t1678862269tb11absa Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 15 Mar 2023 14:37:48 +0800 (CST) X-QQ-SSF: 01400000000000E0N000000A0000000 X-QQ-FEAT: 3M0okmaRx3i7xvGdjV5j2Zs+Dmnl49A9lYBMhO9I2rWXkzT1p1dY4lJ58MEtx i10MH6i7icNLvo7entDtCP5Ku5/mWoNAD84P5rs96cA/lnFKqXsTBUb3BUu7GyO271ElFt/ GfCunA2GCaEQsxcQRAo7B9tqxqwZFy4IgumCdzQgobd0LcWPMHoUrf+S8bHZTva5Y+4R0o5 FhxhQTOEgshTM6q4qTt1KPMynywE/rYHUfWWfMr9NX34qtElzlcoP4Y+Uuo90ZQiK3qwY+v +a8Dcso4B56FYd9o9+I/pp1WvYUmp7sj35dGr1/nFyhReDW7CG86NBPGXaU34T4neM2+AQ9 bgml3frbnyD9LHrHWsWFWx2qJ3eenKly9e2zKnuUW9MNinpTtEZ9uPN3kmGz9gC6ck4vzfJ fj32FdxvE0U= X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Fix bugs of ternary integer and floating-point ternary intrinsics. Date: Wed, 15 Mar 2023 14:37:46 +0800 Message-Id: <20230315063746.166390-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Ju-Zhe Zhong Fix bugs of ternary intrinsic pattern: interger: vnmsac.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) + vd[i] (minus op3 (mult op1 op2)) vnmsac.vx vd, rs1, vs2, vm # vd[i] = -(x[rs1] * vs2[i]) + vd[i] (minus op3 (mult op1 op2)) floating-point: # FP multiply-accumulate, overwrites addend vfmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] (plus (mult (op1 op2)) op3) vfmacc.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) + vd[i] (plus (mult (op1 op2)) op3) # FP negate-(multiply-accumulate), overwrites subtrahend vfnmacc.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) - vd[i] (minus (neg (mult (op1 op2))) op3)) vfnmacc.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) - vd[i] (minus (neg (mult (op1 op2)) op3)) # FP multiply-subtract-accumulator, overwrites subtrahend vfmsac.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) - vd[i] (minus (mult (op1 op2)) op3) vfmsac.vf vd, rs1, vs2, vm # vd[i] = +(f[rs1] * vs2[i]) - vd[i] (minus (mult (op1 op2)) op3) # FP negate-(multiply-subtract-accumulator), overwrites minuend vfnmsac.vv vd, vs1, vs2, vm # vd[i] = -(vs1[i] * vs2[i]) + vd[i] (plus (neg:(mult (op1 op2))) op3) vfnmsac.vf vd, rs1, vs2, vm # vd[i] = -(f[rs1] * vs2[i]) + vd[i] (plus (neg:(mult (op1 op2))) op3) gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc: Fix ternary bug. * config/riscv/vector-iterators.md (nmsac): Ditto. (nmsub): Ditto. (msac): Ditto. (msub): Ditto. (nmadd): Ditto. (nmacc): Ditto. * config/riscv/vector.md (@pred_mul_): Ditto. (@pred_mul_plus): Ditto. (*pred_madd): Ditto. (*pred_macc): Ditto. (*pred_mul_plus): Ditto. (@pred_mul_plus_scalar): Ditto. (*pred_madd_scalar): Ditto. (*pred_macc_scalar): Ditto. (*pred_mul_plus_scalar): Ditto. (*pred_madd_extended_scalar): Ditto. (*pred_macc_extended_scalar): Ditto. (*pred_mul_plus_extended_scalar): Ditto. (@pred_minus_mul): Ditto. (*pred_): Ditto. (*pred_nmsub): Ditto. (*pred_): Ditto. (*pred_nmsac): Ditto. (*pred_mul_): Ditto. (*pred_minus_mul): Ditto. (@pred_mul__scalar): Ditto. (@pred_minus_mul_scalar): Ditto. (*pred__scalar): Ditto. (*pred_nmsub_scalar): Ditto. (*pred__scalar): Ditto. (*pred_nmsac_scalar): Ditto. (*pred_mul__scalar): Ditto. (*pred_minus_mul_scalar): Ditto. (*pred__extended_scalar): Ditto. (*pred_nmsub_extended_scalar): Ditto. (*pred__extended_scalar): Ditto. (*pred_nmsac_extended_scalar): Ditto. (*pred_mul__extended_scalar): Ditto. (*pred_minus_mul_extended_scalar): Ditto. (*pred_): Ditto. (*pred_): Ditto. (*pred__scalar): Ditto. (*pred__scalar): Ditto. (@pred_neg_mul_): Ditto. (@pred_mul_neg_): Ditto. (*pred_): Ditto. (*pred_): Ditto. (*pred_): Ditto. (*pred_): Ditto. (*pred_neg_mul_): Ditto. (*pred_mul_neg_): Ditto. (@pred_neg_mul__scalar): Ditto. (@pred_mul_neg__scalar): Ditto. (*pred__scalar): Ditto. (*pred__scalar): Ditto. (*pred__scalar): Ditto. (*pred__scalar): Ditto. (*pred_neg_mul__scalar): Ditto. (*pred_mul_neg__scalar): Ditto. (@pred_widen_neg_mul_): Ditto. (@pred_widen_mul_neg_): Ditto. (@pred_widen_neg_mul__scalar): Ditto. (@pred_widen_mul_neg__scalar): Ditto. --- .../riscv/riscv-vector-builtins-bases.cc | 80 +- gcc/config/riscv/vector-iterators.md | 8 +- gcc/config/riscv/vector.md | 745 ++++++++++++++---- 3 files changed, 621 insertions(+), 212 deletions(-) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 3f0f809c714..839eb66efb2 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -627,12 +627,11 @@ public: rtx expand (function_expander &e) const override { if (e.op_info->op == OP_TYPE_vx) - return e.use_ternop_insn (true, - code_for_pred_mul_scalar (PLUS, - e.vector_mode ())); + return e.use_ternop_insn (true, code_for_pred_mul_plus_scalar ( + e.vector_mode ())); if (e.op_info->op == OP_TYPE_vv) return e.use_ternop_insn (true, - code_for_pred_mul (PLUS, e.vector_mode ())); + code_for_pred_mul_plus (e.vector_mode ())); gcc_unreachable (); } }; @@ -645,12 +644,11 @@ public: rtx expand (function_expander &e) const override { if (e.op_info->op == OP_TYPE_vx) - return e.use_ternop_insn (true, - code_for_pred_mul_scalar (MINUS, - e.vector_mode ())); + return e.use_ternop_insn (true, code_for_pred_minus_mul_scalar ( + e.vector_mode ())); if (e.op_info->op == OP_TYPE_vv) return e.use_ternop_insn (true, - code_for_pred_mul (MINUS, e.vector_mode ())); + code_for_pred_minus_mul (e.vector_mode ())); gcc_unreachable (); } }; @@ -663,12 +661,11 @@ public: rtx expand (function_expander &e) const override { if (e.op_info->op == OP_TYPE_vx) - return e.use_ternop_insn (false, - code_for_pred_mul_scalar (PLUS, - e.vector_mode ())); + return e.use_ternop_insn (false, code_for_pred_mul_plus_scalar ( + e.vector_mode ())); if (e.op_info->op == OP_TYPE_vv) return e.use_ternop_insn (false, - code_for_pred_mul (PLUS, e.vector_mode ())); + code_for_pred_mul_plus (e.vector_mode ())); gcc_unreachable (); } }; @@ -681,17 +678,15 @@ public: rtx expand (function_expander &e) const override { if (e.op_info->op == OP_TYPE_vx) - return e.use_ternop_insn (false, - code_for_pred_mul_scalar (MINUS, - e.vector_mode ())); + return e.use_ternop_insn (false, code_for_pred_minus_mul_scalar ( + e.vector_mode ())); if (e.op_info->op == OP_TYPE_vv) return e.use_ternop_insn (false, - code_for_pred_mul (MINUS, e.vector_mode ())); + code_for_pred_minus_mul (e.vector_mode ())); gcc_unreachable (); } }; - /* Implements vwmacc. */ class vwmacc : public function_base { @@ -973,12 +968,11 @@ public: rtx expand (function_expander &e) const override { if (e.op_info->op == OP_TYPE_vf) - return e.use_ternop_insn (true, - code_for_pred_mul_scalar (MINUS, - e.vector_mode ())); + return e.use_ternop_insn ( + true, code_for_pred_mul_neg_scalar (PLUS, e.vector_mode ())); if (e.op_info->op == OP_TYPE_vv) return e.use_ternop_insn (true, - code_for_pred_mul (MINUS, e.vector_mode ())); + code_for_pred_mul_neg (PLUS, e.vector_mode ())); gcc_unreachable (); } }; @@ -1009,12 +1003,11 @@ public: rtx expand (function_expander &e) const override { if (e.op_info->op == OP_TYPE_vf) - return e.use_ternop_insn (false, - code_for_pred_mul_scalar (MINUS, - e.vector_mode ())); + return e.use_ternop_insn ( + false, code_for_pred_mul_neg_scalar (PLUS, e.vector_mode ())); if (e.op_info->op == OP_TYPE_vv) return e.use_ternop_insn (false, - code_for_pred_mul (MINUS, e.vector_mode ())); + code_for_pred_mul_neg (PLUS, e.vector_mode ())); gcc_unreachable (); } }; @@ -1028,10 +1021,10 @@ public: { if (e.op_info->op == OP_TYPE_vf) return e.use_ternop_insn ( - true, code_for_pred_neg_mul_scalar (PLUS, e.vector_mode ())); + true, code_for_pred_mul_neg_scalar (MINUS, e.vector_mode ())); if (e.op_info->op == OP_TYPE_vv) return e.use_ternop_insn (true, - code_for_pred_neg_mul (PLUS, e.vector_mode ())); + code_for_pred_mul_neg (MINUS, e.vector_mode ())); gcc_unreachable (); } }; @@ -1044,11 +1037,12 @@ public: rtx expand (function_expander &e) const override { if (e.op_info->op == OP_TYPE_vf) - return e.use_ternop_insn ( - true, code_for_pred_neg_mul_scalar (MINUS, e.vector_mode ())); + return e.use_ternop_insn (true, + code_for_pred_mul_scalar (MINUS, + e.vector_mode ())); if (e.op_info->op == OP_TYPE_vv) - return e.use_ternop_insn (true, code_for_pred_neg_mul (MINUS, - e.vector_mode ())); + return e.use_ternop_insn (true, + code_for_pred_mul (MINUS, e.vector_mode ())); gcc_unreachable (); } }; @@ -1062,10 +1056,10 @@ public: { if (e.op_info->op == OP_TYPE_vf) return e.use_ternop_insn ( - false, code_for_pred_neg_mul_scalar (PLUS, e.vector_mode ())); + false, code_for_pred_mul_neg_scalar (MINUS, e.vector_mode ())); if (e.op_info->op == OP_TYPE_vv) return e.use_ternop_insn (false, - code_for_pred_neg_mul (PLUS, e.vector_mode ())); + code_for_pred_mul_neg (MINUS, e.vector_mode ())); gcc_unreachable (); } }; @@ -1078,12 +1072,12 @@ public: rtx expand (function_expander &e) const override { if (e.op_info->op == OP_TYPE_vf) - return e.use_ternop_insn ( - false, code_for_pred_neg_mul_scalar (MINUS, e.vector_mode ())); + return e.use_ternop_insn (false, + code_for_pred_mul_scalar (MINUS, + e.vector_mode ())); if (e.op_info->op == OP_TYPE_vv) return e.use_ternop_insn (false, - code_for_pred_neg_mul (MINUS, - e.vector_mode ())); + code_for_pred_mul (MINUS, e.vector_mode ())); gcc_unreachable (); } }; @@ -1114,10 +1108,10 @@ public: { if (e.op_info->op == OP_TYPE_vf) return e.use_widen_ternop_insn ( - code_for_pred_widen_neg_mul_scalar (PLUS, e.vector_mode ())); + code_for_pred_widen_mul_neg_scalar (MINUS, e.vector_mode ())); if (e.op_info->op == OP_TYPE_vv) return e.use_widen_ternop_insn ( - code_for_pred_widen_neg_mul (PLUS, e.vector_mode ())); + code_for_pred_widen_mul_neg (MINUS, e.vector_mode ())); gcc_unreachable (); } }; @@ -1131,10 +1125,10 @@ public: { if (e.op_info->op == OP_TYPE_vf) return e.use_widen_ternop_insn ( - code_for_pred_widen_neg_mul_scalar (MINUS, e.vector_mode ())); + code_for_pred_widen_mul_scalar (MINUS, e.vector_mode ())); if (e.op_info->op == OP_TYPE_vv) return e.use_widen_ternop_insn ( - code_for_pred_widen_neg_mul (MINUS, e.vector_mode ())); + code_for_pred_widen_mul (MINUS, e.vector_mode ())); gcc_unreachable (); } }; @@ -1148,10 +1142,10 @@ public: { if (e.op_info->op == OP_TYPE_vf) return e.use_widen_ternop_insn ( - code_for_pred_widen_mul_scalar (MINUS, e.vector_mode ())); + code_for_pred_widen_mul_neg_scalar (PLUS, e.vector_mode ())); if (e.op_info->op == OP_TYPE_vv) return e.use_widen_ternop_insn ( - code_for_pred_widen_mul (MINUS, e.vector_mode ())); + code_for_pred_widen_mul_neg (PLUS, e.vector_mode ())); gcc_unreachable (); } }; diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md index 266563a3aa0..34e486e48ca 100644 --- a/gcc/config/riscv/vector-iterators.md +++ b/gcc/config/riscv/vector-iterators.md @@ -839,10 +839,10 @@ (define_code_iterator any_widen_binop [plus minus mult]) (define_code_iterator plus_minus [plus minus]) -(define_code_attr macc_nmsac [(plus "macc") (minus "nmsac")]) -(define_code_attr madd_nmsub [(plus "madd") (minus "nmsub")]) -(define_code_attr nmacc_msac [(plus "nmacc") (minus "msac")]) -(define_code_attr nmadd_msub [(plus "nmadd") (minus "msub")]) +(define_code_attr madd_msub [(plus "madd") (minus "msub")]) +(define_code_attr macc_msac [(plus "macc") (minus "msac")]) +(define_code_attr nmsub_nmadd [(plus "nmsub") (minus "nmadd")]) +(define_code_attr nmsac_nmacc [(plus "nmsac") (minus "nmacc")]) (define_code_iterator and_ior [and ior]) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 27c5cccb451..a76e8286fe5 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -4148,7 +4148,422 @@ ;; - 11.13 Vector Single-Width Integer Multiply-Add Instructions ;; ------------------------------------------------------------------------------- -(define_expand "@pred_mul_" +(define_expand "@pred_mul_plus" + [(set (match_operand:VI 0 "register_operand") + (if_then_else:VI + (unspec: + [(match_operand: 1 "vector_mask_operand") + (match_operand 6 "vector_length_operand") + (match_operand 7 "const_int_operand") + (match_operand 8 "const_int_operand") + (match_operand 9 "const_int_operand") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (plus:VI + (mult:VI + (match_operand:VI 2 "register_operand") + (match_operand:VI 3 "register_operand")) + (match_operand:VI 4 "register_operand")) + (match_operand:VI 5 "register_operand")))] + "TARGET_VECTOR" +{ + /* Swap the multiplication operands if the fallback value is the + second of the two. */ + if (rtx_equal_p (operands[3], operands[5])) + std::swap (operands[2], operands[3]); +}) + +(define_insn "*pred_madd" + [(set (match_operand:VI 0 "register_operand" "=vd, vr, ?&vr") + (if_then_else:VI + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm,Wc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i") + (match_operand 7 "const_int_operand" " i, i, i") + (match_operand 8 "const_int_operand" " i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (plus:VI + (mult:VI + (match_operand:VI 2 "register_operand" " 0, 0, vr") + (match_operand:VI 3 "register_operand" " vr, vr, vr")) + (match_operand:VI 4 "register_operand" " vr, vr, vr")) + (match_dup 2)))] + "TARGET_VECTOR" + "@ + vmadd.vv\t%0,%3,%4%p1 + vmadd.vv\t%0,%3,%4%p1 + vmv.v.v\t%0,%2\;vmadd.vv\t%0,%3,%4%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "") + (set_attr "merge_op_idx" "4") + (set_attr "vl_op_idx" "5") + (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) + (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) + (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) + +(define_insn "*pred_macc" + [(set (match_operand:VI 0 "register_operand" "=vd, vr, ?&vr") + (if_then_else:VI + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm,Wc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i") + (match_operand 7 "const_int_operand" " i, i, i") + (match_operand 8 "const_int_operand" " i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (plus:VI + (mult:VI + (match_operand:VI 2 "register_operand" " vr, vr, vr") + (match_operand:VI 3 "register_operand" " vr, vr, vr")) + (match_operand:VI 4 "register_operand" " 0, 0, vr")) + (match_dup 4)))] + "TARGET_VECTOR" + "@ + vmacc.vv\t%0,%2,%3%p1 + vmacc.vv\t%0,%2,%3%p1 + vmv.v.v\t%0,%4\;vmacc.vv\t%0,%2,%3%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "") + (set_attr "merge_op_idx" "2") + (set_attr "vl_op_idx" "5") + (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) + (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) + (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) + +(define_insn_and_rewrite "*pred_mul_plus" + [(set (match_operand:VI 0 "register_operand" "=&vr,?&vr, ?&vr, ?&vr, ?&vr") + (if_then_else:VI + (unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1,vmWc1") + (match_operand 6 "vector_length_operand" " rK, rK, rK, rK, rK") + (match_operand 7 "const_int_operand" " i, i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i, i") + (match_operand 9 "const_int_operand" " i, i, i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (plus:VI + (mult:VI + (match_operand:VI 2 "register_operand" " vr, vr, vi, vr, vr") + (match_operand:VI 3 "register_operand" " vr, vr, vr, vi, vr")) + (match_operand:VI 4 "vector_arith_operand" " vr, vi, vr, vr, vr")) + (match_operand:VI 5 "register_operand" " 0, vr, vr, vr, vr")))] + "TARGET_VECTOR + && !rtx_equal_p (operands[2], operands[5]) + && !rtx_equal_p (operands[3], operands[5]) + && !rtx_equal_p (operands[4], operands[5])" + "@ + vmv.v.v\t%0,%4\;vmacc.vv\t%0,%2,%3%p1 + # + # + # + #" + "&& reload_completed + && !rtx_equal_p (operands[0], operands[5])" + { + if (satisfies_constraint_vi (operands[3])) + std::swap (operands[2], operands[3]); + + if (satisfies_constraint_vi (operands[2])) + { + emit_insn (gen_pred_merge (operands[0], RVV_VUNDEF (mode), + operands[5], operands[2], operands[1], operands[6], + operands[7], operands[9])); + operands[5] = operands[2] = operands[0]; + } + else + { + emit_insn (gen_pred_merge (operands[0], RVV_VUNDEF (mode), + operands[5], operands[4], operands[1], operands[6], + operands[7], operands[9])); + operands[5] = operands[4] = operands[0]; + } + } + [(set_attr "type" "vimuladd") + (set_attr "mode" "")]) + +(define_expand "@pred_mul_plus_scalar" + [(set (match_operand:VI_QHS 0 "register_operand") + (if_then_else:VI_QHS + (unspec: + [(match_operand: 1 "vector_mask_operand") + (match_operand 6 "vector_length_operand") + (match_operand 7 "const_int_operand") + (match_operand 8 "const_int_operand") + (match_operand 9 "const_int_operand") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (plus:VI_QHS + (mult:VI_QHS + (vec_duplicate:VI_QHS + (match_operand: 2 "reg_or_int_operand")) + (match_operand:VI_QHS 3 "register_operand")) + (match_operand:VI_QHS 4 "register_operand")) + (match_operand:VI_QHS 5 "register_operand")))] + "TARGET_VECTOR" +{ + operands[2] = force_reg (mode, operands[2]); +}) + +(define_insn "*pred_madd_scalar" + [(set (match_operand:VI 0 "register_operand" "=vd, vr, ?&vr") + (if_then_else:VI + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm,Wc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i") + (match_operand 7 "const_int_operand" " i, i, i") + (match_operand 8 "const_int_operand" " i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (plus:VI + (mult:VI + (vec_duplicate:VI + (match_operand: 2 "register_operand" " r, r, vr")) + (match_operand:VI 3 "register_operand" " 0, 0, vr")) + (match_operand:VI 4 "register_operand" " vr, vr, vr")) + (match_dup 3)))] + "TARGET_VECTOR" + "@ + vmadd.vx\t%0,%2,%4%p1 + vmadd.vx\t%0,%2,%4%p1 + vmv.v.v\t%0,%2\;vmadd.vx\t%0,%2,%4%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "") + (set_attr "merge_op_idx" "4") + (set_attr "vl_op_idx" "5") + (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) + (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) + (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) + +(define_insn "*pred_macc_scalar" + [(set (match_operand:VI 0 "register_operand" "=vd, vr, ?&vr") + (if_then_else:VI + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm,Wc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i") + (match_operand 7 "const_int_operand" " i, i, i") + (match_operand 8 "const_int_operand" " i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (plus:VI + (mult:VI + (vec_duplicate:VI + (match_operand: 2 "register_operand" " r, r, vr")) + (match_operand:VI 3 "register_operand" " vr, vr, vr")) + (match_operand:VI 4 "register_operand" " 0, 0, vr")) + (match_dup 4)))] + "TARGET_VECTOR" + "@ + vmacc.vx\t%0,%2,%3%p1 + vmacc.vx\t%0,%2,%3%p1 + vmv.v.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "") + (set_attr "merge_op_idx" "2") + (set_attr "vl_op_idx" "5") + (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) + (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) + (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) + +(define_insn_and_rewrite "*pred_mul_plus_scalar" + [(set (match_operand:VI 0 "register_operand" "=&vr, ?&vr, ?&vr, ?&vr") + (if_then_else:VI + (unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") + (match_operand 6 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") + (match_operand 9 "const_int_operand" " i, i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (plus:VI + (mult:VI + (vec_duplicate:VI + (match_operand: 2 "register_operand" " r, r, r, r")) + (match_operand:VI 3 "register_operand" " vr, vr, vi, vr")) + (match_operand:VI 4 "vector_arith_operand" " vr, vi, vr, vr")) + (match_operand:VI 5 "register_operand" " 0, vr, vr, vr")))] + "TARGET_VECTOR + && !rtx_equal_p (operands[3], operands[5]) + && !rtx_equal_p (operands[4], operands[5])" + "@ + vmv.v.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1 + # + # + #" + "&& reload_completed + && !rtx_equal_p (operands[0], operands[5])" + { + if (satisfies_constraint_vi (operands[3])) + { + emit_insn (gen_pred_merge (operands[0], RVV_VUNDEF (mode), + operands[5], operands[3], operands[1], operands[6], + operands[7], operands[9])); + operands[5] = operands[3] = operands[0]; + } + else + { + emit_insn (gen_pred_merge (operands[0], RVV_VUNDEF (mode), + operands[5], operands[4], operands[1], operands[6], + operands[7], operands[9])); + operands[5] = operands[4] = operands[0]; + } + } + [(set_attr "type" "vimuladd") + (set_attr "mode" "")]) + +(define_expand "@pred_mul_plus_scalar" + [(set (match_operand:VI_D 0 "register_operand") + (if_then_else:VI_D + (unspec: + [(match_operand: 1 "vector_mask_operand") + (match_operand 6 "vector_length_operand") + (match_operand 7 "const_int_operand") + (match_operand 8 "const_int_operand") + (match_operand 9 "const_int_operand") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (plus:VI_D + (mult:VI_D + (vec_duplicate:VI_D + (match_operand: 2 "reg_or_int_operand")) + (match_operand:VI_D 3 "register_operand")) + (match_operand:VI_D 4 "register_operand")) + (match_operand:VI_D 5 "register_operand")))] + "TARGET_VECTOR" +{ + if (riscv_vector::sew64_scalar_helper ( + operands, + /* scalar op */&operands[2], + /* vl */operands[6], + mode, + mode, + false, + [] (rtx *operands, rtx boardcast_scalar) { + emit_insn (gen_pred_mul_plus (operands[0], operands[1], + boardcast_scalar, operands[3], operands[4], operands[5], + operands[6], operands[7], operands[8], operands[9])); + })) + DONE; +}) + +(define_insn "*pred_madd_extended_scalar" + [(set (match_operand:VI_D 0 "register_operand" "=vd, vr, ?&vr") + (if_then_else:VI_D + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm,Wc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i") + (match_operand 7 "const_int_operand" " i, i, i") + (match_operand 8 "const_int_operand" " i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (plus:VI_D + (mult:VI_D + (vec_duplicate:VI_D + (sign_extend: + (match_operand: 2 "register_operand" " r, r, vr"))) + (match_operand:VI_D 3 "register_operand" " 0, 0, vr")) + (match_operand:VI_D 4 "register_operand" " vr, vr, vr")) + (match_dup 3)))] + "TARGET_VECTOR" + "@ + vmadd.vx\t%0,%2,%4%p1 + vmadd.vx\t%0,%2,%4%p1 + vmv.v.v\t%0,%2\;vmadd.vx\t%0,%2,%4%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "") + (set_attr "merge_op_idx" "4") + (set_attr "vl_op_idx" "5") + (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) + (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) + (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) + +(define_insn "*pred_macc_extended_scalar" + [(set (match_operand:VI_D 0 "register_operand" "=vd, vr, ?&vr") + (if_then_else:VI_D + (unspec: + [(match_operand: 1 "vector_mask_operand" " vm,Wc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i") + (match_operand 7 "const_int_operand" " i, i, i") + (match_operand 8 "const_int_operand" " i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (plus:VI_D + (mult:VI_D + (vec_duplicate:VI_D + (sign_extend: + (match_operand: 2 "register_operand" " r, r, vr"))) + (match_operand:VI_D 3 "register_operand" " vr, vr, vr")) + (match_operand:VI_D 4 "register_operand" " 0, 0, vr")) + (match_dup 4)))] + "TARGET_VECTOR" + "@ + vmacc.vx\t%0,%2,%3%p1 + vmacc.vx\t%0,%2,%3%p1 + vmv.v.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1" + [(set_attr "type" "vimuladd") + (set_attr "mode" "") + (set_attr "merge_op_idx" "2") + (set_attr "vl_op_idx" "5") + (set (attr "ta") (symbol_ref "riscv_vector::get_ta(operands[6])")) + (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) + (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) + +(define_insn_and_rewrite "*pred_mul_plus_extended_scalar" + [(set (match_operand:VI_D 0 "register_operand" "=&vr, ?&vr, ?&vr, ?&vr") + (if_then_else:VI_D + (unspec: + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1,vmWc1,vmWc1") + (match_operand 6 "vector_length_operand" " rK, rK, rK, rK") + (match_operand 7 "const_int_operand" " i, i, i, i") + (match_operand 8 "const_int_operand" " i, i, i, i") + (match_operand 9 "const_int_operand" " i, i, i, i") + (reg:SI VL_REGNUM) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) + (plus:VI_D + (mult:VI_D + (vec_duplicate:VI_D + (sign_extend: + (match_operand: 2 "register_operand" " r, r, r, r"))) + (match_operand:VI_D 3 "register_operand" " vr, vr, vr, vr")) + (match_operand:VI_D 4 "vector_arith_operand" " vr, vr, vr, vr")) + (match_operand:VI_D 5 "register_operand" " 0, vr, vr, vr")))] + "TARGET_VECTOR + && !rtx_equal_p (operands[3], operands[5]) + && !rtx_equal_p (operands[4], operands[5])" + "@ + vmv.v.v\t%0,%4\;vmacc.vx\t%0,%2,%3%p1 + # + # + #" + "&& reload_completed + && !rtx_equal_p (operands[0], operands[5])" + { + if (satisfies_constraint_vi (operands[3])) + { + emit_insn (gen_pred_merge (operands[0], RVV_VUNDEF (mode), + operands[5], operands[3], operands[1], operands[6], + operands[7], operands[9])); + operands[5] = operands[3] = operands[0]; + } + else + { + emit_insn (gen_pred_merge (operands[0], RVV_VUNDEF (mode), + operands[5], operands[4], operands[1], operands[6], + operands[7], operands[9])); + operands[5] = operands[4] = operands[0]; + } + } + [(set_attr "type" "vimuladd") + (set_attr "mode" "")]) + +(define_expand "@pred_minus_mul" [(set (match_operand:VI 0 "register_operand") (if_then_else:VI (unspec: @@ -4159,7 +4574,7 @@ (match_operand 9 "const_int_operand") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VI + (minus:VI (match_operand:VI 4 "register_operand") (mult:VI (match_operand:VI 2 "register_operand") @@ -4173,7 +4588,7 @@ std::swap (operands[2], operands[3]); }) -(define_insn "*pred_" +(define_insn "*pred_nmsub" [(set (match_operand:VI 0 "register_operand" "=vd, vr, ?&vr") (if_then_else:VI (unspec: @@ -4184,7 +4599,7 @@ (match_operand 8 "const_int_operand" " i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VI + (minus:VI (match_operand:VI 4 "register_operand" " vr, vr, vr") (mult:VI (match_operand:VI 2 "register_operand" " 0, 0, vr") @@ -4192,9 +4607,9 @@ (match_dup 2)))] "TARGET_VECTOR" "@ - v.vv\t%0,%3,%4%p1 - v.vv\t%0,%3,%4%p1 - vmv.v.v\t%0,%2\;v.vv\t%0,%3,%4%p1" + vnmsub.vv\t%0,%3,%4%p1 + vnmsub.vv\t%0,%3,%4%p1 + vmv.v.v\t%0,%2\;vnmsub.vv\t%0,%3,%4%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "4") @@ -4203,7 +4618,7 @@ (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) -(define_insn "*pred_" +(define_insn "*pred_nmsac" [(set (match_operand:VI 0 "register_operand" "=vd, vr, ?&vr") (if_then_else:VI (unspec: @@ -4214,7 +4629,7 @@ (match_operand 8 "const_int_operand" " i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VI + (minus:VI (match_operand:VI 4 "register_operand" " 0, 0, vr") (mult:VI (match_operand:VI 2 "register_operand" " vr, vr, vr") @@ -4222,9 +4637,9 @@ (match_dup 4)))] "TARGET_VECTOR" "@ - v.vv\t%0,%2,%3%p1 - v.vv\t%0,%2,%3%p1 - vmv.v.v\t%0,%4\;v.vv\t%0,%2,%3%p1" + vnmsac.vv\t%0,%2,%3%p1 + vnmsac.vv\t%0,%2,%3%p1 + vmv.v.v\t%0,%4\;vnmsac.vv\t%0,%2,%3%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "2") @@ -4233,7 +4648,7 @@ (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) -(define_insn_and_rewrite "*pred_mul_" +(define_insn_and_rewrite "*pred_minus_mul" [(set (match_operand:VI 0 "register_operand" "=&vr,?&vr, ?&vr, ?&vr, ?&vr") (if_then_else:VI (unspec: @@ -4244,7 +4659,7 @@ (match_operand 9 "const_int_operand" " i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VI + (minus:VI (match_operand:VI 4 "vector_arith_operand" " vr, vi, vr, vr, vr") (mult:VI (match_operand:VI 2 "register_operand" " vr, vr, vi, vr, vr") @@ -4255,7 +4670,7 @@ && !rtx_equal_p (operands[3], operands[5]) && !rtx_equal_p (operands[4], operands[5])" "@ - vmv.v.v\t%0,%4\;v.vv\t%0,%2,%3%p1 + vmv.v.v\t%0,%4\;vnmsac.vv\t%0,%2,%3%p1 # # # @@ -4284,7 +4699,7 @@ [(set_attr "type" "vimuladd") (set_attr "mode" "")]) -(define_expand "@pred_mul__scalar" +(define_expand "@pred_minus_mul_scalar" [(set (match_operand:VI_QHS 0 "register_operand") (if_then_else:VI_QHS (unspec: @@ -4295,7 +4710,7 @@ (match_operand 9 "const_int_operand") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VI_QHS + (minus:VI_QHS (match_operand:VI_QHS 4 "register_operand") (mult:VI_QHS (vec_duplicate:VI_QHS @@ -4307,7 +4722,7 @@ operands[2] = force_reg (mode, operands[2]); }) -(define_insn "*pred__scalar" +(define_insn "*pred_nmsub_scalar" [(set (match_operand:VI 0 "register_operand" "=vd, vr, ?&vr") (if_then_else:VI (unspec: @@ -4318,7 +4733,7 @@ (match_operand 8 "const_int_operand" " i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VI + (minus:VI (match_operand:VI 4 "register_operand" " vr, vr, vr") (mult:VI (vec_duplicate:VI @@ -4327,9 +4742,9 @@ (match_dup 3)))] "TARGET_VECTOR" "@ - v.vx\t%0,%2,%4%p1 - v.vx\t%0,%2,%4%p1 - vmv.v.v\t%0,%2\;v.vx\t%0,%2,%4%p1" + vnmsub.vx\t%0,%2,%4%p1 + vnmsub.vx\t%0,%2,%4%p1 + vmv.v.v\t%0,%2\;vnmsub.vx\t%0,%2,%4%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "4") @@ -4338,7 +4753,7 @@ (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) -(define_insn "*pred__scalar" +(define_insn "*pred_nmsac_scalar" [(set (match_operand:VI 0 "register_operand" "=vd, vr, ?&vr") (if_then_else:VI (unspec: @@ -4349,7 +4764,7 @@ (match_operand 8 "const_int_operand" " i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VI + (minus:VI (match_operand:VI 4 "register_operand" " 0, 0, vr") (mult:VI (vec_duplicate:VI @@ -4358,9 +4773,9 @@ (match_dup 4)))] "TARGET_VECTOR" "@ - v.vx\t%0,%2,%3%p1 - v.vx\t%0,%2,%3%p1 - vmv.v.v\t%0,%4\;v.vx\t%0,%2,%3%p1" + vnmsac.vx\t%0,%2,%3%p1 + vnmsac.vx\t%0,%2,%3%p1 + vmv.v.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "2") @@ -4369,7 +4784,7 @@ (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) -(define_insn_and_rewrite "*pred_mul__scalar" +(define_insn_and_rewrite "*pred_minus_mul_scalar" [(set (match_operand:VI 0 "register_operand" "=&vr, ?&vr, ?&vr, ?&vr") (if_then_else:VI (unspec: @@ -4380,7 +4795,7 @@ (match_operand 9 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VI + (minus:VI (match_operand:VI 4 "vector_arith_operand" " vr, vi, vr, vr") (mult:VI (vec_duplicate:VI @@ -4391,7 +4806,7 @@ && !rtx_equal_p (operands[3], operands[5]) && !rtx_equal_p (operands[4], operands[5])" "@ - vmv.v.v\t%0,%4\;v.vx\t%0,%2,%3%p1 + vmv.v.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1 # # #" @@ -4416,7 +4831,7 @@ [(set_attr "type" "vimuladd") (set_attr "mode" "")]) -(define_expand "@pred_mul__scalar" +(define_expand "@pred_minus_mul_scalar" [(set (match_operand:VI_D 0 "register_operand") (if_then_else:VI_D (unspec: @@ -4427,7 +4842,7 @@ (match_operand 9 "const_int_operand") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VI_D + (minus:VI_D (match_operand:VI_D 4 "register_operand") (mult:VI_D (vec_duplicate:VI_D @@ -4444,14 +4859,14 @@ mode, false, [] (rtx *operands, rtx boardcast_scalar) { - emit_insn (gen_pred_mul_ (operands[0], operands[1], + emit_insn (gen_pred_minus_mul (operands[0], operands[1], boardcast_scalar, operands[3], operands[4], operands[5], operands[6], operands[7], operands[8], operands[9])); })) DONE; }) -(define_insn "*pred__extended_scalar" +(define_insn "*pred_nmsub_extended_scalar" [(set (match_operand:VI_D 0 "register_operand" "=vd, vr, ?&vr") (if_then_else:VI_D (unspec: @@ -4462,7 +4877,7 @@ (match_operand 8 "const_int_operand" " i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VI_D + (minus:VI_D (match_operand:VI_D 4 "register_operand" " vr, vr, vr") (mult:VI_D (vec_duplicate:VI_D @@ -4472,9 +4887,9 @@ (match_dup 3)))] "TARGET_VECTOR" "@ - v.vx\t%0,%2,%4%p1 - v.vx\t%0,%2,%4%p1 - vmv.v.v\t%0,%2\;v.vx\t%0,%2,%4%p1" + vnmsub.vx\t%0,%2,%4%p1 + vnmsub.vx\t%0,%2,%4%p1 + vmv.v.v\t%0,%2\;vnmsub.vx\t%0,%2,%4%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "4") @@ -4483,7 +4898,7 @@ (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) -(define_insn "*pred__extended_scalar" +(define_insn "*pred_nmsac_extended_scalar" [(set (match_operand:VI_D 0 "register_operand" "=vd, vr, ?&vr") (if_then_else:VI_D (unspec: @@ -4494,7 +4909,7 @@ (match_operand 8 "const_int_operand" " i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VI_D + (minus:VI_D (match_operand:VI_D 4 "register_operand" " 0, 0, vr") (mult:VI_D (vec_duplicate:VI_D @@ -4504,9 +4919,9 @@ (match_dup 4)))] "TARGET_VECTOR" "@ - v.vx\t%0,%2,%3%p1 - v.vx\t%0,%2,%3%p1 - vmv.v.v\t%0,%4\;v.vx\t%0,%2,%3%p1" + vnmsac.vx\t%0,%2,%3%p1 + vnmsac.vx\t%0,%2,%3%p1 + vmv.v.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1" [(set_attr "type" "vimuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "2") @@ -4515,7 +4930,7 @@ (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) -(define_insn_and_rewrite "*pred_mul__extended_scalar" +(define_insn_and_rewrite "*pred_minus_mul_extended_scalar" [(set (match_operand:VI_D 0 "register_operand" "=&vr, ?&vr, ?&vr, ?&vr") (if_then_else:VI_D (unspec: @@ -4526,7 +4941,7 @@ (match_operand 9 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (plus_minus:VI_D + (minus:VI_D (match_operand:VI_D 4 "vector_arith_operand" " vr, vr, vr, vr") (mult:VI_D (vec_duplicate:VI_D @@ -4538,7 +4953,7 @@ && !rtx_equal_p (operands[3], operands[5]) && !rtx_equal_p (operands[4], operands[5])" "@ - vmv.v.v\t%0,%4\;v.vx\t%0,%2,%3%p1 + vmv.v.v\t%0,%4\;vnmsac.vx\t%0,%2,%3%p1 # # #" @@ -5033,10 +5448,10 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VF - (match_operand:VF 4 "register_operand") (mult:VF (match_operand:VF 2 "register_operand") - (match_operand:VF 3 "register_operand"))) + (match_operand:VF 3 "register_operand")) + (match_operand:VF 4 "register_operand")) (match_operand:VF 5 "register_operand")))] "TARGET_VECTOR" { @@ -5046,7 +5461,7 @@ std::swap (operands[2], operands[3]); }) -(define_insn "*pred_" +(define_insn "*pred_" [(set (match_operand:VF 0 "register_operand" "=vd, vr, ?&vr") (if_then_else:VF (unspec: @@ -5058,16 +5473,16 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VF - (match_operand:VF 4 "register_operand" " vr, vr, vr") (mult:VF (match_operand:VF 2 "register_operand" " 0, 0, vr") - (match_operand:VF 3 "register_operand" " vr, vr, vr"))) + (match_operand:VF 3 "register_operand" " vr, vr, vr")) + (match_operand:VF 4 "register_operand" " vr, vr, vr")) (match_dup 2)))] "TARGET_VECTOR" "@ - vf.vv\t%0,%3,%4%p1 - vf.vv\t%0,%3,%4%p1 - vmv.v.v\t%0,%2\;vf.vv\t%0,%3,%4%p1" + vf.vv\t%0,%3,%4%p1 + vf.vv\t%0,%3,%4%p1 + vmv.v.v\t%0,%2\;vf.vv\t%0,%3,%4%p1" [(set_attr "type" "vfmuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "4") @@ -5076,7 +5491,7 @@ (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) -(define_insn "*pred_" +(define_insn "*pred_" [(set (match_operand:VF 0 "register_operand" "=vd, vr, ?&vr") (if_then_else:VF (unspec: @@ -5088,16 +5503,16 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VF - (match_operand:VF 4 "register_operand" " 0, 0, vr") (mult:VF (match_operand:VF 2 "register_operand" " vr, vr, vr") - (match_operand:VF 3 "register_operand" " vr, vr, vr"))) + (match_operand:VF 3 "register_operand" " vr, vr, vr")) + (match_operand:VF 4 "register_operand" " 0, 0, vr")) (match_dup 4)))] "TARGET_VECTOR" "@ - vf.vv\t%0,%2,%3%p1 - vf.vv\t%0,%2,%3%p1 - vmv.v.v\t%0,%4\;vf.vv\t%0,%2,%3%p1" + vf.vv\t%0,%2,%3%p1 + vf.vv\t%0,%2,%3%p1 + vmv.v.v\t%0,%4\;vf.vv\t%0,%2,%3%p1" [(set_attr "type" "vfmuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "2") @@ -5118,17 +5533,17 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VF - (match_operand:VF 4 "vector_arith_operand" " vr, vr") (mult:VF (match_operand:VF 2 "register_operand" " vr, vr") - (match_operand:VF 3 "register_operand" " vr, vr"))) + (match_operand:VF 3 "register_operand" " vr, vr")) + (match_operand:VF 4 "vector_arith_operand" " vr, vr")) (match_operand:VF 5 "register_operand" " 0, vr")))] "TARGET_VECTOR && !rtx_equal_p (operands[2], operands[5]) && !rtx_equal_p (operands[3], operands[5]) && !rtx_equal_p (operands[4], operands[5])" "@ - vmv.v.v\t%0,%4\;vf.vv\t%0,%2,%3%p1 + vmv.v.v\t%0,%4\;vf.vv\t%0,%2,%3%p1 #" "&& reload_completed && !rtx_equal_p (operands[0], operands[5])" @@ -5153,16 +5568,16 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VF - (match_operand:VF 4 "register_operand") (mult:VF (vec_duplicate:VF (match_operand: 2 "register_operand")) - (match_operand:VF 3 "register_operand"))) + (match_operand:VF 3 "register_operand")) + (match_operand:VF 4 "register_operand")) (match_operand:VF 5 "register_operand")))] "TARGET_VECTOR" {}) -(define_insn "*pred__scalar" +(define_insn "*pred__scalar" [(set (match_operand:VF 0 "register_operand" "=vd, vr, ?&vr") (if_then_else:VF (unspec: @@ -5174,17 +5589,17 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VF - (match_operand:VF 4 "register_operand" " vr, vr, vr") (mult:VF (vec_duplicate:VF (match_operand: 2 "register_operand" " f, f, vr")) - (match_operand:VF 3 "register_operand" " 0, 0, vr"))) + (match_operand:VF 3 "register_operand" " 0, 0, vr")) + (match_operand:VF 4 "register_operand" " vr, vr, vr")) (match_dup 3)))] "TARGET_VECTOR" "@ - vf.vf\t%0,%2,%4%p1 - vf.vf\t%0,%2,%4%p1 - vmv.v.v\t%0,%2\;vf.vf\t%0,%2,%4%p1" + vf.vf\t%0,%2,%4%p1 + vf.vf\t%0,%2,%4%p1 + vmv.v.v\t%0,%2\;vf.vf\t%0,%2,%4%p1" [(set_attr "type" "vfmuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "4") @@ -5193,7 +5608,7 @@ (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) -(define_insn "*pred__scalar" +(define_insn "*pred__scalar" [(set (match_operand:VF 0 "register_operand" "=vd, vr, ?&vr") (if_then_else:VF (unspec: @@ -5205,17 +5620,17 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VF - (match_operand:VF 4 "register_operand" " 0, 0, vr") (mult:VF (vec_duplicate:VF (match_operand: 2 "register_operand" " f, f, vr")) - (match_operand:VF 3 "register_operand" " vr, vr, vr"))) + (match_operand:VF 3 "register_operand" " vr, vr, vr")) + (match_operand:VF 4 "register_operand" " 0, 0, vr")) (match_dup 4)))] "TARGET_VECTOR" "@ - vf.vf\t%0,%2,%3%p1 - vf.vf\t%0,%2,%3%p1 - vmv.v.v\t%0,%4\;vf.vf\t%0,%2,%3%p1" + vf.vf\t%0,%2,%3%p1 + vf.vf\t%0,%2,%3%p1 + vmv.v.v\t%0,%4\;vf.vf\t%0,%2,%3%p1" [(set_attr "type" "vfmuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "2") @@ -5236,17 +5651,17 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VF - (match_operand:VF 4 "vector_arith_operand" " vr, vr") (mult:VF (vec_duplicate:VF (match_operand: 2 "register_operand" " f, f")) - (match_operand:VF 3 "register_operand" " vr, vr"))) + (match_operand:VF 3 "register_operand" " vr, vr")) + (match_operand:VF 4 "vector_arith_operand" " vr, vr")) (match_operand:VF 5 "register_operand" " 0, vr")))] "TARGET_VECTOR && !rtx_equal_p (operands[3], operands[5]) && !rtx_equal_p (operands[4], operands[5])" "@ - vmv.v.v\t%0,%4\;vf.vf\t%0,%2,%3%p1 + vmv.v.v\t%0,%4\;vf.vf\t%0,%2,%3%p1 #" "&& reload_completed && !rtx_equal_p (operands[0], operands[5])" @@ -5259,7 +5674,7 @@ [(set_attr "type" "vfmuladd") (set_attr "mode" "")]) -(define_expand "@pred_neg_mul_" +(define_expand "@pred_mul_neg_" [(set (match_operand:VF 0 "register_operand") (if_then_else:VF (unspec: @@ -5270,12 +5685,12 @@ (match_operand 9 "const_int_operand") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (neg:VF - (plus_minus:VF - (match_operand:VF 4 "register_operand") + (plus_minus:VF + (neg:VF (mult:VF (match_operand:VF 2 "register_operand") - (match_operand:VF 3 "register_operand")))) + (match_operand:VF 3 "register_operand"))) + (match_operand:VF 4 "register_operand")) (match_operand:VF 5 "register_operand")))] "TARGET_VECTOR" { @@ -5285,7 +5700,7 @@ std::swap (operands[2], operands[3]); }) -(define_insn "*pred_" +(define_insn "*pred_" [(set (match_operand:VF 0 "register_operand" "=vd, vr, ?&vr") (if_then_else:VF (unspec: @@ -5296,18 +5711,18 @@ (match_operand 8 "const_int_operand" " i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (neg:VF - (plus_minus:VF - (match_operand:VF 4 "register_operand" " vr, vr, vr") + (plus_minus:VF + (neg:VF (mult:VF (match_operand:VF 2 "register_operand" " 0, 0, vr") - (match_operand:VF 3 "register_operand" " vr, vr, vr")))) + (match_operand:VF 3 "register_operand" " vr, vr, vr"))) + (match_operand:VF 4 "register_operand" " vr, vr, vr")) (match_dup 2)))] "TARGET_VECTOR" "@ - vf.vv\t%0,%3,%4%p1 - vf.vv\t%0,%3,%4%p1 - vmv.v.v\t%0,%2\;vf.vv\t%0,%3,%4%p1" + vf.vv\t%0,%3,%4%p1 + vf.vv\t%0,%3,%4%p1 + vmv.v.v\t%0,%2\;vf.vv\t%0,%3,%4%p1" [(set_attr "type" "vfmuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "4") @@ -5316,7 +5731,7 @@ (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) -(define_insn "*pred_" +(define_insn "*pred_" [(set (match_operand:VF 0 "register_operand" "=vd, vr, ?&vr") (if_then_else:VF (unspec: @@ -5327,18 +5742,18 @@ (match_operand 8 "const_int_operand" " i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (neg:VF - (plus_minus:VF - (match_operand:VF 4 "register_operand" " 0, 0, vr") + (plus_minus:VF + (neg:VF (mult:VF (match_operand:VF 2 "register_operand" " vr, vr, vr") - (match_operand:VF 3 "register_operand" " vr, vr, vr")))) + (match_operand:VF 3 "register_operand" " vr, vr, vr"))) + (match_operand:VF 4 "register_operand" " 0, 0, vr")) (match_dup 4)))] "TARGET_VECTOR" "@ - vf.vv\t%0,%2,%3%p1 - vf.vv\t%0,%2,%3%p1 - vmv.v.v\t%0,%4\;vf.vv\t%0,%2,%3%p1" + vf.vv\t%0,%2,%3%p1 + vf.vv\t%0,%2,%3%p1 + vmv.v.v\t%0,%4\;vf.vv\t%0,%2,%3%p1" [(set_attr "type" "vfmuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "2") @@ -5347,7 +5762,7 @@ (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) -(define_insn_and_rewrite "*pred_neg_mul_" +(define_insn_and_rewrite "*pred_mul_neg_" [(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr") (if_then_else:VF (unspec: @@ -5358,19 +5773,19 @@ (match_operand 9 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (neg:VF - (plus_minus:VF - (match_operand:VF 4 "vector_arith_operand" " vr, vr") + (plus_minus:VF + (neg:VF (mult:VF - (match_operand:VF 2 "register_operand" " vr, vr") - (match_operand:VF 3 "register_operand" " vr, vr")))) + (match_operand:VF 2 "register_operand" " vr, vr") + (match_operand:VF 3 "register_operand" " vr, vr"))) + (match_operand:VF 4 "vector_arith_operand" " vr, vr")) (match_operand:VF 5 "register_operand" " 0, vr")))] "TARGET_VECTOR && !rtx_equal_p (operands[2], operands[5]) && !rtx_equal_p (operands[3], operands[5]) && !rtx_equal_p (operands[4], operands[5])" "@ - vmv.v.v\t%0,%4\;vf.vv\t%0,%2,%3%p1 + vmv.v.v\t%0,%4\;vf.vv\t%0,%2,%3%p1 #" "&& reload_completed && !rtx_equal_p (operands[0], operands[5])" @@ -5383,7 +5798,7 @@ [(set_attr "type" "vfmuladd") (set_attr "mode" "")]) -(define_expand "@pred_neg_mul__scalar" +(define_expand "@pred_mul_neg__scalar" [(set (match_operand:VF 0 "register_operand") (if_then_else:VF (unspec: @@ -5394,41 +5809,41 @@ (match_operand 9 "const_int_operand") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (neg:VF - (plus_minus:VF - (match_operand:VF 4 "register_operand") + (plus_minus:VF + (neg:VF (mult:VF (vec_duplicate:VF (match_operand: 2 "register_operand")) - (match_operand:VF 3 "register_operand")))) + (match_operand:VF 3 "register_operand"))) + (match_operand:VF 4 "register_operand")) (match_operand:VF 5 "register_operand")))] "TARGET_VECTOR" {}) -(define_insn "*pred__scalar" - [(set (match_operand:VF 0 "register_operand" "=vd, vr, ?&vr") +(define_insn "*pred__scalar" + [(set (match_operand:VF 0 "register_operand" "=vd, vr, ?&vr") (if_then_else:VF (unspec: - [(match_operand: 1 "vector_mask_operand" " vm,Wc1,vmWc1") - (match_operand 5 "vector_length_operand" " rK, rK, rK") - (match_operand 6 "const_int_operand" " i, i, i") - (match_operand 7 "const_int_operand" " i, i, i") - (match_operand 8 "const_int_operand" " i, i, i") + [(match_operand: 1 "vector_mask_operand" " vm,Wc1,vmWc1") + (match_operand 5 "vector_length_operand" " rK, rK, rK") + (match_operand 6 "const_int_operand" " i, i, i") + (match_operand 7 "const_int_operand" " i, i, i") + (match_operand 8 "const_int_operand" " i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (neg:VF - (plus_minus:VF - (match_operand:VF 4 "register_operand" " vr, vr, vr") + (plus_minus:VF + (neg:VF (mult:VF (vec_duplicate:VF (match_operand: 2 "register_operand" " f, f, vr")) - (match_operand:VF 3 "register_operand" " 0, 0, vr")))) + (match_operand:VF 3 "register_operand" " 0, 0, vr"))) + (match_operand:VF 4 "register_operand" " vr, vr, vr")) (match_dup 3)))] "TARGET_VECTOR" "@ - vf.vf\t%0,%2,%4%p1 - vf.vf\t%0,%2,%4%p1 - vmv.v.v\t%0,%2\;vf.vf\t%0,%2,%4%p1" + vf.vf\t%0,%2,%4%p1 + vf.vf\t%0,%2,%4%p1 + vmv.v.v\t%0,%2\;vf.vf\t%0,%2,%4%p1" [(set_attr "type" "vfmuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "4") @@ -5437,7 +5852,7 @@ (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) -(define_insn "*pred__scalar" +(define_insn "*pred__scalar" [(set (match_operand:VF 0 "register_operand" "=vd, vr, ?&vr") (if_then_else:VF (unspec: @@ -5448,19 +5863,19 @@ (match_operand 8 "const_int_operand" " i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (neg:VF - (plus_minus:VF - (match_operand:VF 4 "register_operand" " 0, 0, vr") + (plus_minus:VF + (neg:VF (mult:VF (vec_duplicate:VF (match_operand: 2 "register_operand" " f, f, vr")) - (match_operand:VF 3 "register_operand" " vr, vr, vr")))) + (match_operand:VF 3 "register_operand" " vr, vr, vr"))) + (match_operand:VF 4 "register_operand" " 0, 0, vr")) (match_dup 4)))] "TARGET_VECTOR" "@ - vf.vf\t%0,%2,%3%p1 - vf.vf\t%0,%2,%3%p1 - vmv.v.v\t%0,%4\;vf.vf\t%0,%2,%3%p1" + vf.vf\t%0,%2,%3%p1 + vf.vf\t%0,%2,%3%p1 + vmv.v.v\t%0,%4\;vf.vf\t%0,%2,%3%p1" [(set_attr "type" "vfmuladd") (set_attr "mode" "") (set_attr "merge_op_idx" "2") @@ -5469,30 +5884,30 @@ (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[7])")) (set (attr "avl_type") (symbol_ref "INTVAL (operands[8])"))]) -(define_insn_and_rewrite "*pred_neg_mul__scalar" - [(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr") +(define_insn_and_rewrite "*pred_mul_neg__scalar" + [(set (match_operand:VF 0 "register_operand" "=&vr, ?&vr") (if_then_else:VF (unspec: - [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") - (match_operand 6 "vector_length_operand" " rK, rK") - (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") - (match_operand 9 "const_int_operand" " i, i") + [(match_operand: 1 "vector_mask_operand" "vmWc1,vmWc1") + (match_operand 6 "vector_length_operand" " rK, rK") + (match_operand 7 "const_int_operand" " i, i") + (match_operand 8 "const_int_operand" " i, i") + (match_operand 9 "const_int_operand" " i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (neg:VF - (plus_minus:VF - (match_operand:VF 4 "vector_arith_operand" " vr, vr") + (plus_minus:VF + (neg:VF (mult:VF (vec_duplicate:VF (match_operand: 2 "register_operand" " f, f")) - (match_operand:VF 3 "register_operand" " vr, vr")))) + (match_operand:VF 3 "register_operand" " vr, vr"))) + (match_operand:VF 4 "vector_arith_operand" " vr, vr")) (match_operand:VF 5 "register_operand" " 0, vr")))] "TARGET_VECTOR && !rtx_equal_p (operands[3], operands[5]) && !rtx_equal_p (operands[4], operands[5])" "@ - vmv.v.v\t%0,%4\;vf.vf\t%0,%2,%3%p1 + vmv.v.v\t%0,%4\;vf.vf\t%0,%2,%3%p1 #" "&& reload_completed && !rtx_equal_p (operands[0], operands[5])" @@ -5693,15 +6108,15 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VWEXTF - (match_operand:VWEXTF 2 "register_operand" " 0") (mult:VWEXTF (float_extend:VWEXTF (match_operand: 3 "register_operand" " vr")) (float_extend:VWEXTF - (match_operand: 4 "register_operand" " vr")))) + (match_operand: 4 "register_operand" " vr"))) + (match_operand:VWEXTF 2 "register_operand" " 0")) (match_dup 2)))] "TARGET_VECTOR" - "vfw.vv\t%0,%3,%4%p1" + "vfw.vv\t%0,%3,%4%p1" [(set_attr "type" "vfwmuladd") (set_attr "mode" "")]) @@ -5717,20 +6132,20 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (plus_minus:VWEXTF - (match_operand:VWEXTF 2 "register_operand" " 0") (mult:VWEXTF (float_extend:VWEXTF (vec_duplicate: (match_operand: 3 "register_operand" " f"))) (float_extend:VWEXTF - (match_operand: 4 "register_operand" " vr")))) + (match_operand: 4 "register_operand" " vr"))) + (match_operand:VWEXTF 2 "register_operand" " 0")) (match_dup 2)))] "TARGET_VECTOR" - "vfw.vf\t%0,%3,%4%p1" + "vfw.vf\t%0,%3,%4%p1" [(set_attr "type" "vfwmuladd") (set_attr "mode" "")]) -(define_insn "@pred_widen_neg_mul_" +(define_insn "@pred_widen_mul_neg_" [(set (match_operand:VWEXTF 0 "register_operand" "=&vr") (if_then_else:VWEXTF (unspec: @@ -5741,21 +6156,21 @@ (match_operand 8 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (neg:VWEXTF - (plus_minus:VWEXTF - (match_operand:VWEXTF 2 "register_operand" " 0") + (plus_minus:VWEXTF + (neg:VWEXTF (mult:VWEXTF (float_extend:VWEXTF (match_operand: 3 "register_operand" " vr")) (float_extend:VWEXTF - (match_operand: 4 "register_operand" " vr"))))) + (match_operand: 4 "register_operand" " vr")))) + (match_operand:VWEXTF 2 "register_operand" " 0")) (match_dup 2)))] "TARGET_VECTOR" - "vfw.vv\t%0,%3,%4%p1" + "vfw.vv\t%0,%3,%4%p1" [(set_attr "type" "vfwmuladd") (set_attr "mode" "")]) -(define_insn "@pred_widen_neg_mul__scalar" +(define_insn "@pred_widen_mul_neg__scalar" [(set (match_operand:VWEXTF 0 "register_operand" "=&vr") (if_then_else:VWEXTF (unspec: @@ -5766,18 +6181,18 @@ (match_operand 8 "const_int_operand" " i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (neg:VWEXTF - (plus_minus:VWEXTF - (match_operand:VWEXTF 2 "register_operand" " 0") + (plus_minus:VWEXTF + (neg:VWEXTF (mult:VWEXTF (float_extend:VWEXTF (vec_duplicate: (match_operand: 3 "register_operand" " f"))) (float_extend:VWEXTF - (match_operand: 4 "register_operand" " vr"))))) + (match_operand: 4 "register_operand" " vr")))) + (match_operand:VWEXTF 2 "register_operand" " 0")) (match_dup 2)))] "TARGET_VECTOR" - "vfw.vf\t%0,%3,%4%p1" + "vfw.vf\t%0,%3,%4%p1" [(set_attr "type" "vfwmuladd") (set_attr "mode" "")])