From patchwork Tue Mar 14 17:43:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 66385 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1BA2E3858431 for ; Tue, 14 Mar 2023 17:43:58 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 1BA2E3858431 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1678815838; bh=kcwzBVFDprtqmNmQjqWq7kAXo81fZLgnNlXUHoH0/5w=; h=Date:Subject:To:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=wS/qI1t9XTRyajpso30QHj/0bSVEFG24MhFDVml7XuF4mHmbcXvunjvxPlZcd9ghi eX1dz3ij90sCn0u74YskUpnQvO4IzUpPQjv35ZnTK755G0hibH9JzQ2sFHauJct0RN igSgeOJB2gnmKs6tDnE/OVJNiQ+tyWAM7IYO974s= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-yb1-xb2e.google.com (mail-yb1-xb2e.google.com [IPv6:2607:f8b0:4864:20::b2e]) by sourceware.org (Postfix) with ESMTPS id D7B413858D33 for ; Tue, 14 Mar 2023 17:43:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D7B413858D33 Received: by mail-yb1-xb2e.google.com with SMTP id cj14so5418714ybb.12 for ; Tue, 14 Mar 2023 10:43:28 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678815808; h=to:subject:message-id:date:from:mime-version:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=kcwzBVFDprtqmNmQjqWq7kAXo81fZLgnNlXUHoH0/5w=; b=zL6p35JKZaKk8gNsicTjR9mgsiKpd8JLkx45/L3dO68w2aJOjuAffCoBPgob2XBHJR xGrPa9TsjRmaQbzbFXujvu6uU8Fmd4Gv4a2avysMU7ftlPrf6qJ49U/R9D0t1wbKrd5A fYQpT/orEHPdrfXSGUQcxE2LGX0H2RXdQxZFL6yTf8ARk6S8z/7tx+mCi+BhaAfs/0j1 d51Prg86S1DP0YGGawX8oviUuQU76TDXtIhJkjmsOLv2F/RDfuv8CcL6cBKQGWcA5RfU njSb3Fuuo8LHISWT+R5McGEFz/odabPz5RDODkJdnysr18l+CblqOO7NyNiVzHyG7K4p L6mg== X-Gm-Message-State: AO0yUKVnN4LPj9VbriibDXXCpsRnjHR1Jv3r0QldRghq9C+4/vRsYuig VguWjy5IK7aS6lJdm9aTWBHfEOsZStxdQV9cZa5UWmzPnN24Yw== X-Google-Smtp-Source: AK7set/rCwIW7sU3Z7mZWJ2cUO8aVr0fJc+KfU0NVkB8AF9fAm24oKsrfqZVEJmljm/4LAYjv2W12BLF8yrmouAfuFI= X-Received: by 2002:a5b:24c:0:b0:b3b:a48c:b23e with SMTP id g12-20020a5b024c000000b00b3ba48cb23emr5624223ybp.2.1678815807843; Tue, 14 Mar 2023 10:43:27 -0700 (PDT) MIME-Version: 1.0 Date: Tue, 14 Mar 2023 18:43:16 +0100 Message-ID: Subject: [PATCH] i386: Use movss to implement V2SImode VEC_PERM. To: "gcc-patches@gcc.gnu.org" X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Uros Bizjak via Gcc-patches From: Uros Bizjak Reply-To: Uros Bizjak Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Perform V2SI vector permutation in the same way as existing V2SF for TARGET_MMX_WITH_SSE targets. The testcase: typedef unsigned int v2si __attribute__((vector_size(8))); v2si foo(v2si x, v2si y) { return (v2si){y[0], x[1]}; } is currently compiled to (-O2): foo: movdqa %xmm0, %xmm2 movdqa %xmm1, %xmm0 pshufd $0xe5, %xmm2, %xmm2 punpckldq %xmm2, %xmm0 ret and with the patched compiler: foo: movss %xmm1, %xmm0 ret The functionality is already tested in gcc.target/i386/vperm-v2si.c gcc/ChangeLog: * config/i386/i386-expand.cc (expand_vec_perm_movs): Handle V2SImode for TARGET_MMX_WITH_SSE. * config/i386/mmx.md (*mmx_movss_): Rename from *mmx_movss using V2FI mode iterator to handle both V2SI and V2SF modes. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Pushed to master. Uros. diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index 1094ece8b6d..6cc8bd5c80c 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -18949,11 +18949,9 @@ expand_vec_perm_movs (struct expand_vec_perm_d *d) if (d->one_operand_p) return false; - if (!(TARGET_SSE && vmode == V4SFmode) - && !(TARGET_SSE && vmode == V4SImode) - && !(TARGET_MMX_WITH_SSE && vmode == V2SFmode) - && !(TARGET_SSE2 && vmode == V2DFmode) - && !(TARGET_SSE2 && vmode == V2DImode)) + if (!(TARGET_SSE && (vmode == V4SFmode || vmode == V4SImode)) + && !(TARGET_MMX_WITH_SSE && (vmode == V2SFmode || vmode == V2SImode)) + && !(TARGET_SSE2 && (vmode == V2DFmode || vmode == V2DImode))) return false; /* Only the first element is changed. */ diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 0deccc2d2f4..f9c66115f81 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1518,11 +1518,11 @@ (set_attr "prefix" "*,maybe_vex,orig") (set_attr "mode" "DI,V4SF,V4SF")]) -(define_insn "*mmx_movss" - [(set (match_operand:V2SF 0 "register_operand" "=x,v") - (vec_merge:V2SF - (match_operand:V2SF 2 "register_operand" " x,v") - (match_operand:V2SF 1 "register_operand" " 0,v") +(define_insn "*mmx_movss_" + [(set (match_operand:V2FI 0 "register_operand" "=x,v") + (vec_merge:V2FI + (match_operand:V2FI 2 "register_operand" " x,v") + (match_operand:V2FI 1 "register_operand" " 0,v") (const_int 1)))] "TARGET_MMX_WITH_SSE" "@