From patchwork Sat Feb 25 09:50:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ajit Agarwal X-Patchwork-Id: 65644 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 997C1385B530 for ; Sat, 25 Feb 2023 09:51:13 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 997C1385B530 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1677318673; bh=aaB6tbeZXTZ4FW+R4OmGMlQzKryAsyRuCJFl4sC8SW8=; h=Date:To:Cc:Subject:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=x+JItRNbK35KpOY5AOY64bonQqZWfKv06alIiTmq1yKJ9YUd86DM4hrbKzOJ5Ku5b LOcrcButZspIux9+P91Qn9cV2bOjS0sO1DY+ELMJdJxtEk1nIdwc55iZuxMdUxqPrg f7cGqxQHsKb8elroTgjsdGD8XbLDFb84cBztva2M= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 703BC3857C45 for ; Sat, 25 Feb 2023 09:50:41 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 703BC3857C45 Received: from pps.filterd (m0187473.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 31P4jenE036511; Sat, 25 Feb 2023 09:50:40 GMT Received: from ppma04wdc.us.ibm.com (1a.90.2fa9.ip4.static.sl-reverse.com [169.47.144.26]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3nybkbv2xj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 25 Feb 2023 09:50:39 +0000 Received: from pps.filterd (ppma04wdc.us.ibm.com [127.0.0.1]) by ppma04wdc.us.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 31P8x9sr019435; Sat, 25 Feb 2023 09:50:38 GMT Received: from smtprelay01.wdc07v.mail.ibm.com ([9.208.129.119]) by ppma04wdc.us.ibm.com (PPS) with ESMTPS id 3nybdts2eh-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 25 Feb 2023 09:50:38 +0000 Received: from smtpav06.wdc07v.mail.ibm.com (smtpav06.wdc07v.mail.ibm.com [10.39.53.233]) by smtprelay01.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 31P9oaIR39453202 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sat, 25 Feb 2023 09:50:37 GMT Received: from smtpav06.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DE8F25803F; Sat, 25 Feb 2023 09:50:36 +0000 (GMT) Received: from smtpav06.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 638385804E; Sat, 25 Feb 2023 09:50:35 +0000 (GMT) Received: from [9.43.6.59] (unknown [9.43.6.59]) by smtpav06.wdc07v.mail.ibm.com (Postfix) with ESMTP; Sat, 25 Feb 2023 09:50:35 +0000 (GMT) Message-ID: <174972e2-3792-935b-ed4e-4e9d3d4ec26a@linux.ibm.com> Date: Sat, 25 Feb 2023 15:20:33 +0530 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.8.0 Content-Language: en-US To: gcc-patches Cc: Segher Boessenkool , bergner@linux.ibm.com Subject: [PATCH v2] rs6000: fmr gets used instead of faster xxlor [PR93571] X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: HNgHc_-kb4wuFuxTDVg_suq8UWZ1CWCR X-Proofpoint-GUID: HNgHc_-kb4wuFuxTDVg_suq8UWZ1CWCR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.170.22 definitions=2023-02-25_05,2023-02-24_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 phishscore=0 lowpriorityscore=0 suspectscore=0 priorityscore=1501 mlxlogscore=999 impostorscore=0 bulkscore=0 clxscore=1015 malwarescore=0 mlxscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2212070000 definitions=main-2302250077 X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Ajit Agarwal via Gcc-patches From: Ajit Agarwal Reply-To: Ajit Agarwal Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Hello All: Here is the patch that uses xxlor instead of fmr where possible. Performance results shows that fmr is better in power9 and power10 architectures whereas xxlor is better in power7 and power 8 architectures. fmr is the only option before p7. Bootstrapped and regtested on powerpc64-linux-gnu Thanks & Regards Ajit rs6000: Use xxlor instead of fmr where possible Replaces fmr with xxlor instruction for power7 and power8 architectures whereas for power9 and power10 keep fmr instruction. Perf measurement results: Power9 fmr: 201,847,661 cycles. Power9 xxlor: 201,877,78 cycles. Power8 fmr: 200,901,043 cycles. Power8 xxlor: 201,020,518 cycles. Power7 fmr: 201,059,524 cycles. Power7 xxlor: 201,042,851 cycles. 2023-02-25 Ajit Kumar Agarwal gcc/ChangeLog: * config/rs6000/rs6000.md (*movdf_hardfloat64): Use xxlor for power7 and power8 and fmr for power9 and power10. --- gcc/config/rs6000/rs6000.md | 44 +++++++++++++++++++++++-------------- 1 file changed, 28 insertions(+), 16 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 81bffb04ceb..e101f7f5fc1 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -354,7 +354,7 @@ (define_attr "cpu" (const (symbol_ref "(enum attr_cpu) rs6000_tune"))) ;; The ISA we implement. -(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10" +(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p7p8v,p9,p9v,p9kf,p9tf,p10" (const_string "any")) ;; Is this alternative enabled for the current CPU/ISA/etc.? @@ -402,6 +402,11 @@ (define_attr "enabled" "" (and (eq_attr "isa" "p10") (match_test "TARGET_POWER10")) (const_int 1) + + (and (eq_attr "isa" "p7p8v") + (match_test "TARGET_VSX && !TARGET_P9_VECTOR")) + (const_int 1) + ] (const_int 0))) ;; If this instruction is microcoded on the CELL processor @@ -8436,27 +8441,29 @@ (define_insn "*mov_softfloat32" (define_insn "*mov_hardfloat64" [(set (match_operand:FMOVE64 0 "nonimmediate_operand" - "=m, d, d, , wY, - , Z, , , !r, + "=m, d, , , wY, + , Z, wa, , !r, YZ, r, !r, *c*l, !r, - *h, r, , wa") + *h, r, , d, wn, + wa") (match_operand:FMOVE64 1 "input_operand" - "d, m, d, wY, , - Z, , , , , + "d, m, , wY, , + Z, , wa, , , r, YZ, r, r, *h, - 0, , r, eP"))] + 0, , r, d, wn, + eP"))] "TARGET_POWERPC64 && TARGET_HARD_FLOAT && (gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode))" "@ stfd%U0%X0 %1,%0 lfd%U1%X1 %0,%1 - fmr %0,%1 + xxlor %x0,%x1,%x1 lxsd %0,%1 stxsd %1,%0 lxsdx %x0,%y1 stxsdx %x1,%y0 - xxlor %x0,%x1,%x1 + fmr %0,%1 xxlxor %x0,%x0,%x0 li %0,0 std%U0%X0 %1,%0 @@ -8467,23 +8474,28 @@ (define_insn "*mov_hardfloat64" nop mfvsrd %0,%x1 mtvsrd %x0,%1 + fmr %0,%1 + fmr %0,%1 #" [(set_attr "type" - "fpstore, fpload, fpsimple, fpload, fpstore, + "fpstore, fpload, veclogical, fpload, fpstore, fpload, fpstore, veclogical, veclogical, integer, store, load, *, mtjmpr, mfjmpr, - *, mfvsr, mtvsr, vecperm") + *, mfvsr, mtvsr, fpsimple, fpsimple, + vecperm") (set_attr "size" "64") (set_attr "isa" - "*, *, *, p9v, p9v, - p7v, p7v, *, *, *, - *, *, *, *, *, - *, p8v, p8v, p10") + "*, *, p7p8v, p9v, p9v, + p7v, p7v, *, *, *, + *, *, *, *, *, + *, p8v, p8v, *, *, + p10") (set_attr "prefixed" "*, *, *, *, *, *, *, *, *, *, *, *, *, *, *, - *, *, *, *")]) + *, *, *, *, *, + *")]) ;; STD LD MR MT MF G-const ;; H-const F-const Special