From patchwork Sat Feb 11 17:49:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shiqi Zhang X-Patchwork-Id: 64768 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 662D83857B93 for ; Sat, 11 Feb 2023 17:49:45 +0000 (GMT) X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from cstnet.cn (smtp80.cstnet.cn [159.226.251.80]) by sourceware.org (Postfix) with ESMTP id 3C3803858D32 for ; Sat, 11 Feb 2023 17:49:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3C3803858D32 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=isrc.iscas.ac.cn Authentication-Results: sourceware.org; spf=none smtp.mailfrom=isrc.iscas.ac.cn Received: from localhost (unknown [101.6.102.102]) by APP-01 (Coremail) with SMTP id qwCowAAXF0Ml1edjP8igBA--.8707S2; Sun, 12 Feb 2023 01:49:25 +0800 (CST) From: Shiqi Zhang To: libc-alpha@sourceware.org Cc: Shiqi Zhang Subject: [PATCH] riscv: Add macros for FPUCW in fpu_control.h Date: Sun, 12 Feb 2023 01:49:16 +0800 Message-Id: <20230211174916.1455-1-shiqi@isrc.iscas.ac.cn> X-Mailer: git-send-email 2.39.1 MIME-Version: 1.0 X-CM-TRANSID: qwCowAAXF0Ml1edjP8igBA--.8707S2 X-Coremail-Antispam: 1UD129KBjvJXoW7trWkKryUuw4rZr4UGw48WFg_yoW8Aw1rpF Z3CFy5KFy5trWaqan2k3W8tr1fXa1DKF1DJrZ3Cr4xJF4ay3Z7KrW2qr4FvFyUXrs5Xa10 9r1UGryUWF43ZrDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUyq14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWUuVWrJwAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26r1j6r1xM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r1j 6r4UM28EF7xvwVC2z280aVAFwI0_Jr0_Gr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r1j6r 4UM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xII jxv20xvE14v26r1Y6r17McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr 1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxAIw28IcxkI7VAKI48J MxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwV AFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUXVWUAwCIc40Y0x0EwIxGrwCI42IY6xIIjxv2 0xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI42IY6xAIw20EY4 v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AK xVWUJVW8JbIYCTnIWIevJa73UjIFyTuYvjfUYDGYDUUUU X-Originating-IP: [101.6.102.102] X-CM-SenderInfo: 5vkl1xw6lv2u4olvutnvoduhdfq/ X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KHOP_HELO_FCRDNS, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org Sender: "Libc-alpha" Add macros for rounding modes and accrued exception flags in order to make controlling FPCSR easier for users. Reference: RISC-V Unprivileged Spec v20191213, Section 11.2, Table 11.1 & 11.2 --- I'm implementing RISC-V support for netlib/f2c, and found that there is no definitions for FPCSR flag bits in glibc when writing codes for FPU exception controls. So I checked them in RISC-V specs and defined the accrued exception flags and rounding mode flags in this patch, making it easier for other users to control FPU status. Also, I think these macros should be documented somewhere but I'm not sure where should I doc them. I'll appreciate it if you could give some suggestions. For copyrights, this patch is covered by an existing copyright assignment of ISCAS/ISRC so I'm assuming that there shouldn't be a signed-off-by line in commit message. sysdeps/riscv/fpu_control.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/sysdeps/riscv/fpu_control.h b/sysdeps/riscv/fpu_control.h index c33798c6bb..5c883be4fe 100644 --- a/sysdeps/riscv/fpu_control.h +++ b/sysdeps/riscv/fpu_control.h @@ -36,6 +36,21 @@ extern fpu_control_t __fpu_control; # define _FPU_DEFAULT 0 # define _FPU_IEEE _FPU_DEFAULT +/* FPU rounding modes */ +# define _FPU_RM_RNE (0 << 5) +# define _FPU_RM_RTZ (1 << 5) +# define _FPU_RM_RDN (2 << 5) +# define _FPU_RM_RUP (3 << 5) +# define _FPU_RM_RMM (4 << 5) +# define _FPU_RM_DYN (7 << 5) + +/* FPU accrued exception flags */ +# define _FPU_EXCEPT_NV (1 << 0) +# define _FPU_EXCEPT_NZ (1 << 1) +# define _FPU_EXCEPT_OF (1 << 2) +# define _FPU_EXCEPT_UF (1 << 3) +# define _FPU_EXCEPT_NX (1 << 4) + /* Type of the control word. */ typedef unsigned int fpu_control_t __attribute__ ((__mode__ (__SI__)));