From patchwork Fri Feb 10 22:41:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 64718 X-Patchwork-Delegate: jlaw@ventanamicro.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8BCC338493FF for ; Fri, 10 Feb 2023 22:42:15 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by sourceware.org (Postfix) with ESMTPS id 8A2B2385841A for ; Fri, 10 Feb 2023 22:41:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8A2B2385841A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-ej1-x630.google.com with SMTP id p26so19418996ejx.13 for ; Fri, 10 Feb 2023 14:41:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/RyF/ntVgtCsYGnLFAVrw88rDa/CLJQ3LoKqFAtSIBc=; b=RpqyzydxQ1K+Kk+VpZq4mjbBW0X5IW5t/4/mnS0O7vtMohsquNe8bJ4YoGZksDDhIK W6Qj5arzulxX4Kg9YTh2iakz5HqGR2qSUB8oJvD04l5W3M8AvGyc+NFDJeUtDj8sJ9t+ aMt/7OkqE2SV95nY3e7qdHOP7DClx6ZZX8y0DLfhVvbauylCqjm9YY7dFoMIgQvBC8KI ZuFSw8AFY7iuokIQikpMJjNIhAJDrUHWwlDqIYJW4d6UmlEIZDEa8Y6U3WpxVcOJeWM6 ChrUy6/wnCQ58mb5Zq/a87v/5NjuTS1sSvZtonXn7yg3X2SIHUWekiXaloI2670XiZu3 pMTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/RyF/ntVgtCsYGnLFAVrw88rDa/CLJQ3LoKqFAtSIBc=; b=Tx/LT3145RrNzmU8CiO0WhqhBJtHF5an1eCRpYRvsmg/mIOK2rZ6KhCIpf3Njn9he3 qdORVi8KlkvlI88IohEKzP6vay4DTQcbC7OG3e8bJ8v7Mbk98qeUSRMwZpw0fUvB8xAo AUvV1lMZGwTPSzjnAKPkVDjrJf3AGXkwxfQ7lbcvLK5mmoLv/tooaT/UO201emjC9j3j ko/vulWtokpCVeImk7sMe1m5/wWhEDpKULqMCFbW0WBUNt6wuXgSxsHQ7SvRMJy2MQpZ qkWRAEh5pU16/WotnndQvu/2uEgstxFs+VrsjpYvsgraTNIPZuFvVrn+20usZMbCZVc2 CaXg== X-Gm-Message-State: AO0yUKUZeRWmNjEhKKqST60hvUcwMHHRUVDtUGxc2tN2cdY2fjvTYL/3 tfBIxKaTbGaAiE9NWvi/4sMcLYdsEwAlB8TmSl8= X-Google-Smtp-Source: AK7set9f9uRvlbM1duYYPMxG9O88K510A+L6wJOSzLLGCrUAd7lxhRM3X5nBX+w9lDgJnZzzqhvf0w== X-Received: by 2002:a17:907:988e:b0:884:fdb:6c41 with SMTP id ja14-20020a170907988e00b008840fdb6c41mr18384367ejc.43.1676068914991; Fri, 10 Feb 2023 14:41:54 -0800 (PST) Received: from ubuntu-focal.. ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id c15-20020a17090603cf00b0088bd62b1cbbsm2976956eja.192.2023.02.10.14.41.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 14:41:54 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Kito Cheng , Christoph Muellner , Palmer Dabbelt , Andrew Waterman , Vineet Gupta , Philipp Tomsich Subject: [RFC PATCH v1 01/10] docs: Document a canonical RTL for a conditional-zero insns Date: Fri, 10 Feb 2023 23:41:41 +0100 Message-Id: <20230210224150.2801962-2-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230210224150.2801962-1-philipp.tomsich@vrull.eu> References: <20230210224150.2801962-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" On RISC-V, conditional-zero (i.e., move a register value or zero to a destination register) instructions are part if the Zicond extension. To support architectures that have similar constructs, we define a canonical RTL representation that can be used in if-conversion. Signed-off-by: Philipp Tomsich --- gcc/doc/md.texi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 7235d34c4b3..579462ea67f 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -8347,6 +8347,23 @@ operand of @code{mult} is also a shift, then that is extended also. This transformation is only applied when it can be proven that the original operation had sufficient precision to prevent overflow. +@cindex @code{conditional-zero}, canonicalization of +@item +A machine that has an instruction that performs a conditional-zero +operation (i.e., an instruction that moves a register value or puts 0 +into the destination register) should specify the pattern for that +instruction as: +@smallexample +(define_insn "" + [(set (match_operand:@var{m} 0 @dots{}) + (and:@var{m} + (neg:@var{m} (@var{eq_or_ne} (match_operand:@var{m} 1 @dots{}) + (const_int 0))) + (match_operand:@var{m} 2 @dots{})))] + "@dots{}" + "@dots{}") +@end smallexample + @end itemize Further canonicalization rules are defined in the function From patchwork Fri Feb 10 22:41:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 64719 X-Patchwork-Delegate: jlaw@ventanamicro.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7CDDB3889E1D for ; Fri, 10 Feb 2023 22:42:18 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by sourceware.org (Postfix) with ESMTPS id 6E9853858025 for ; Fri, 10 Feb 2023 22:41:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6E9853858025 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-ej1-x632.google.com with SMTP id qb15so17413632ejc.1 for ; Fri, 10 Feb 2023 14:41:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Dc40va9Jbve37siWLFy+q0zRO1XQ0zQuQmXjjbFL/gc=; b=ZnAn/7p9yeIrb0jh7Jo8QFsVjXE6WT+cvrMBwTqvMb25boPZgGtw/Ycc5cHgpQ7p5J 6kWkOYGwEv+bBq7YApfvJbEwQe4+W3Uau//k1yMY9O2qogESUT7HOLqF0qxRSU0ozbjC v6+Gu0YQWyyGx8mQNY0xd8TlrZWld4oZwG374ZlRl71ppvmPMDjvonzPtoqX/NomcEv0 a17E4l3QkyqNcLFRR8jGsfwRfTGHaw22vX+ofiaevJXUMXtuUS2xlXH+Hk7x/sE+9tCD quP13LBhu5wwRBxgmARS1DVGc6ahe5Q+T928muMUj2/9u88HctqXe9Jx6LWVaufsNq53 6GdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Dc40va9Jbve37siWLFy+q0zRO1XQ0zQuQmXjjbFL/gc=; b=xKqxOzYf3FoE0YFJN8/HC8aCnA2c65UnrwiPqnOZMCxpw1r/bUYjhHH3uFgewYnIhc 0PBB5o2IMTEbXxh/RFrIpe9eJhlUjaYrNzOyHioS4EQU9nyCaZcW6XvzfMfSSEd8MMjJ rEOLw/gcC6IExq7Y3pLKSzmFBGVUvqijmNlZcDUhqL3YuL9JBB0IUpww6JzNteZVARv1 rElQ+EP0rpvEpMiG76ryu5nCdErZktoygzFWlSgMrXumjJFZwN/c+dxAwOHwkjFArzc9 9TBbe5LtjrRVw+5k6IIFSQgfCUrH0EZFp2Yh8q95yhOrQ6MTJkFKIP6ZnVWWRXJcNhBC s6HA== X-Gm-Message-State: AO0yUKUiiuYn47eiTRIo2/m8uk1r60i/GDXcgW5dF/NfSdSczRYtjIn0 Y2qOBOXUR9EQ8y0zmQ/hRahxWck67xTukmfp4cw= X-Google-Smtp-Source: AK7set+oz7rMcdOYfYlHfXFyv4wcM+dMgfVaf1krGvXkx86soqN7gwPKvsAy/rOw/2FL5lUxeB1Kkg== X-Received: by 2002:a17:906:6c97:b0:8ab:9657:3152 with SMTP id s23-20020a1709066c9700b008ab96573152mr12616272ejr.15.1676068915910; Fri, 10 Feb 2023 14:41:55 -0800 (PST) Received: from ubuntu-focal.. ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id c15-20020a17090603cf00b0088bd62b1cbbsm2976956eja.192.2023.02.10.14.41.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 14:41:55 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Kito Cheng , Christoph Muellner , Palmer Dabbelt , Andrew Waterman , Vineet Gupta , Philipp Tomsich Subject: [RFC PATCH v1 02/10] RISC-V: Recognize Zicond (conditional operations) extension Date: Fri, 10 Feb 2023 23:41:42 +0100 Message-Id: <20230210224150.2801962-3-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230210224150.2801962-1-philipp.tomsich@vrull.eu> References: <20230210224150.2801962-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This adds the RISC-V Zicond extension to the option parsing. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Recognize "zicond" as part of an architecture string. * config/riscv/riscv-opts.h (MASK_ZICOND): Define. (TARGET_ZICOND): Define. Signed-off-by: Philipp Tomsich --- gcc/common/config/riscv/riscv-common.cc | 3 +++ gcc/config/riscv/riscv-opts.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 787674003cb..999e1926db1 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -163,6 +163,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0}, {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0}, + {"zicond", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zawrs", ISA_SPEC_CLASS_NONE, 1, 0}, {"zba", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1181,6 +1183,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zicsr", &gcc_options::x_riscv_zi_subext, MASK_ZICSR}, {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI}, + {"zicond", &gcc_options::x_riscv_zi_subext, MASK_ZICOND}, {"zawrs", &gcc_options::x_riscv_za_subext, MASK_ZAWRS}, diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index ff398c0a2ae..61d5212da20 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -69,9 +69,11 @@ enum stack_protector_guard { #define MASK_ZICSR (1 << 0) #define MASK_ZIFENCEI (1 << 1) +#define MASK_ZICOND (1 << 2) #define TARGET_ZICSR ((riscv_zi_subext & MASK_ZICSR) != 0) #define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0) +#define TARGET_ZICOND ((riscv_zi_subext & MASK_ZICOND) != 0) #define MASK_ZAWRS (1 << 0) #define TARGET_ZAWRS ((riscv_za_subext & MASK_ZAWRS) != 0) From patchwork Fri Feb 10 22:41:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 64720 X-Patchwork-Delegate: jlaw@ventanamicro.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 205FE3888838 for ; Fri, 10 Feb 2023 22:42:20 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by sourceware.org (Postfix) with ESMTPS id 5E5BA385483E for ; Fri, 10 Feb 2023 22:41:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5E5BA385483E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-ej1-x62d.google.com with SMTP id sa10so19437243ejc.9 for ; Fri, 10 Feb 2023 14:41:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=i6zGWcBZ52cMsyLrbclSHuADcmLv0+USuFghN838pGY=; b=nUe25w13cXF9xickBcAZ7dR1XEmjc1a3JhrDMGB71rpjkEqjFds1+LBSgor/TQGoFR l4ZYZkU9mgkmO0fFaXUzqo67eELPkL+tEJiznQUT0sVM28Sdwrva4yYkVrQR8ywBY4MX IUpaKkPYmNi7i2ErxrgbeIrRd3aiUzlRvdn1llEIFnqD391eddvdTcnTfGrWlntncje4 z2pYQw4LKVTMjtWMcLEMyS9oGVRBTLETm7TsC759qIWWPyc1TTtHaXKNM4CncjfSQCGj jvGKeqQejwEzg8lOPv2uARhoNJnCYAh/5ClTF2QgugC0ebBW/UVWgRtx3kRlkNcyt0y8 lqQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=i6zGWcBZ52cMsyLrbclSHuADcmLv0+USuFghN838pGY=; b=J2BN68g1nW3DBGaV8x7NVYMf6/TxhFVzEe9t5VSQzrvjRT1W1IHzf6iv/24MTZydfC LsVidRdOEqzIWPP60tmHQQKSM5xks9kMPL0LOkwiO14CwgGZaCtbj+RSw5RzIUqioV4T 8CYcNneOaI9UgM4t9VsmjtP4T351SreW23P0f1En/zogHa+ubfngmmA/ABdpbKGU9zKl z2Abve+NS2YwUXVY+Q4fHQFT1dvihQaZYJAhsBh8ozKZEJ2kXJlsKcwwtg4t5tNL1k7h WzqpWdkBNUf0fk1PRkFNTzH7fkmLc9ZDU4DHtY+4ZZghaMXU1aiHBXzB9srotfPjexLa VhuQ== X-Gm-Message-State: AO0yUKXRl9Xh1mTqxn7afngRTCmnM6MWVuxdwa2SGq+yfgYxAV5QaKwz RsYAcE/zE4neYK/PumnY1umvM9oj0fy/drZbVeU= X-Google-Smtp-Source: AK7set+by17rhQIgC1l4njmtGK4ibCuSB4xyiqgbX6/p8Zp1pvYoaPcHwuEgdJTZ+gK9R/0oXTxfpA== X-Received: by 2002:a17:907:1c83:b0:884:c45f:1c04 with SMTP id nb3-20020a1709071c8300b00884c45f1c04mr23891187ejc.2.1676068916850; Fri, 10 Feb 2023 14:41:56 -0800 (PST) Received: from ubuntu-focal.. ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id c15-20020a17090603cf00b0088bd62b1cbbsm2976956eja.192.2023.02.10.14.41.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 14:41:56 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Kito Cheng , Christoph Muellner , Palmer Dabbelt , Andrew Waterman , Vineet Gupta , Philipp Tomsich Subject: [RFC PATCH v1 03/10] RISC-V: Generate czero.eqz/nez on noce_try_store_flag_mask if-conversion Date: Fri, 10 Feb 2023 23:41:43 +0100 Message-Id: <20230210224150.2801962-4-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230210224150.2801962-1-philipp.tomsich@vrull.eu> References: <20230210224150.2801962-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Adds a pattern to map the output of noce_try_store_flag_mask if-conversion in the combiner onto vt.maskc; the input patterns supported are similar to the following: (set (reg/v/f:DI 75 [ ]) (and:DI (neg:DI (ne:DI (reg:DI 82) (const_int 0 [0]))) (reg/v/f:DI 75 [ ]))) To ensure that the combine-pass doesn't get confused about profitability, we recognize the idiom as requiring a single instruction when the Zicond extension is present. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_rtx_costs): Recongnize the idiom for conditional-zero as a single instruction for TARGET_ZICOND * config/riscv/riscv.md: Include zicond.md. * config/riscv/zicond.md: New file. gcc/testsuite/ChangeLog: * gcc.target/riscv/zicond-ne-03.c: New test. * gcc.target/riscv/zicond-ne-04.c: New test. Signed-off-by: Philipp Tomsich --- gcc/config/riscv/riscv.cc | 15 ++++++++++ gcc/config/riscv/riscv.md | 1 + gcc/config/riscv/zicond.md | 30 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/zicond-ne-03.c | 13 ++++++++ gcc/testsuite/gcc.target/riscv/zicond-ne-04.c | 13 ++++++++ 5 files changed, 72 insertions(+) create mode 100644 gcc/config/riscv/zicond.md create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-ne-03.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-ne-04.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index e4d3e1a3229..7e69a652fc5 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2331,6 +2331,21 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN return false; case AND: + /* czero.eqz/nez */ + if ((TARGET_ZICOND) + && mode == word_mode + && GET_CODE (XEXP (x, 0)) == NEG) + { + rtx inner = XEXP (XEXP (x, 0), 0); + + if ((GET_CODE (inner) == EQ || GET_CODE (inner) == NE) + && CONST_INT_P (XEXP (inner, 1)) + && INTVAL (XEXP (inner, 1)) == 0) + { + *total = COSTS_N_INSNS (1); + return true; + } + } /* slli.uw pattern for zba. */ if (TARGET_ZBA && TARGET_64BIT && mode == DImode && GET_CODE (XEXP (x, 0)) == ASHIFT) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index e8b5fc6644d..7c632bb4d65 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -3228,3 +3228,4 @@ (define_insn "riscv_prefetchi_" (include "generic.md") (include "sifive-7.md") (include "vector.md") +(include "zicond.md") diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md new file mode 100644 index 00000000000..278e3a67802 --- /dev/null +++ b/gcc/config/riscv/zicond.md @@ -0,0 +1,30 @@ +;; Machine description for the RISC-V Zicond extension +;; Copyright (C) 2022-23 Free Software Foundation, Inc. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +(define_code_iterator eq_or_ne [eq ne]) +(define_code_attr eqz [(eq "nez") (ne "eqz")]) + +(define_insn "*czero." + [(set (match_operand:DI 0 "register_operand" "=r") + (and:DI (neg:DI (eq_or_ne:DI + (match_operand:DI 1 "register_operand" "r") + (const_int 0))) + (match_operand:DI 2 "register_operand" "r")))] + "TARGET_ZICOND" + "czero.\t%0,%2,%1") diff --git a/gcc/testsuite/gcc.target/riscv/zicond-ne-03.c b/gcc/testsuite/gcc.target/riscv/zicond-ne-03.c new file mode 100644 index 00000000000..887b1273ce7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-ne-03.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64 -mtune=thead-c906" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" "-Oz" } } */ + +long long ne3(long long a, long long b) +{ + if (a != 0) + return b; + + return 0; +} + +/* { dg-final { scan-assembler-times "czero.eqz" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zicond-ne-04.c b/gcc/testsuite/gcc.target/riscv/zicond-ne-04.c new file mode 100644 index 00000000000..6f6df06b4b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-ne-04.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64 -mtune=thead-c906" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +long long ne4(long long a, long long b) +{ + if (a != 0) + return 0; + + return b; +} + +/* { dg-final { scan-assembler-times "czero.nez" 1 } } */ From patchwork Fri Feb 10 22:41:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 64723 X-Patchwork-Delegate: jlaw@ventanamicro.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B47B738A8167 for ; Fri, 10 Feb 2023 22:42:54 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by sourceware.org (Postfix) with ESMTPS id 3C90B3865488 for ; Fri, 10 Feb 2023 22:41:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3C90B3865488 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-ej1-x632.google.com with SMTP id m2so19453358ejb.8 for ; Fri, 10 Feb 2023 14:41:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Y8ydSbASF54ZRRFvsooOPXgYS7OUOK4hSdnNQUHBXH0=; b=A4pfTHD/Y+wEGdfW3Q4Aw9O7fQmh4Bycnsh4XmVqFi/ttVpg94g1vOlUUcp+BhuFp/ EzhIQ1KW8rAW+sgf5ImVVTMmayUZobxM5H9kVx64Dg2yxPF4W6TgG+g0tTdC8GYwAUC1 NqP1ooZcZuLDv4FzKbtuIqlg746s5Vq3wdh1yFQTfZmbYGz4ZbN9E29Z87tjiE/yK20I /KMjpEq3QLLtRUPzq+09X1w33ZyZatE+uAVEqJ/b27CnA8ZLiLVvEvbdI9V1rbLXFBTE YJmveeoB1K+jAIvNNC0y90sODPAumf8rovabMrTUI6OiY69RTwhxH/JCGWDe5PG6ClET 3s7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Y8ydSbASF54ZRRFvsooOPXgYS7OUOK4hSdnNQUHBXH0=; b=mUzTF9UkLeZuC0WLgrWiaAkR25gUwV1FvmwtlU+E8mhiwbYFYLrOOqsDYRqZj/xYH7 gvsfBDOaZZ8xMfFZCTXD8tnlZ0zPVHzwC2DzNPQgEUFZkgtQV+yazj/z8WMjar2nQ6KD 9rCt7DSnQiq24W2VJLchfEmTwJ8fie4RMtxwDraiQ7OD6Ouh1piAKZYkmgfZhxPOifUv ET45kX6EmDeoJOD/WheUSskoixxbM08slBPeZrgrNGCgM3DxmKjytlTeYrxSObuGvCps G+YVS+hHPDmYEY2hDnwGcB3E94IsJzYf5kZE1yCVTNmI7BCPLxC8tGG1uWHbrETZM6kg wqPA== X-Gm-Message-State: AO0yUKVo/FlLLavVxWAGaTMutvpTwnyUPp7eU9abd8gcUR945ui2tgsu B2TJE2kdWacgqq4rb3IcO03uo6AWEDzJJCkp69k= X-Google-Smtp-Source: AK7set+wMYhfQefVXlgK68ZhZ6QkoTQTOvj7xfKdnzJm4dVwS1gO9lZISWsxWobCSdeI0jYK978Elg== X-Received: by 2002:a17:906:eb14:b0:87b:d409:f087 with SMTP id mb20-20020a170906eb1400b0087bd409f087mr17654163ejb.21.1676068917779; Fri, 10 Feb 2023 14:41:57 -0800 (PST) Received: from ubuntu-focal.. ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id c15-20020a17090603cf00b0088bd62b1cbbsm2976956eja.192.2023.02.10.14.41.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 14:41:57 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Kito Cheng , Christoph Muellner , Palmer Dabbelt , Andrew Waterman , Vineet Gupta , Philipp Tomsich Subject: [RFC PATCH v1 04/10] RISC-V: Support immediates in Zicond Date: Fri, 10 Feb 2023 23:41:44 +0100 Message-Id: <20230210224150.2801962-5-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230210224150.2801962-1-philipp.tomsich@vrull.eu> References: <20230210224150.2801962-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" When if-conversion encounters sequences using immediates, the sequences can't trivially map back onto czero.eqz/czero.nezt (even if benefitial) due to czero.eqz/czero.nez not having immediate forms. This adds a splitter to rewrite opportunities for Zicond that operate on an immediate by first putting the immediate into a register to enable the non-immediate czero.eqz/czero.nez instructions to operate on the value. Consider code, such as long func2 (long a, long c) { if (c) a = 2; else a = 5; return a; } which will be converted to func2: seqz a0,a2 neg a0,a0 andi a0,a0,3 addi a0,a0,2 ret Following this change, we generate li a0,3 czero.nez a0,a0,a2 addi a0,a0,2 ret This commit also introduces a simple unit test for if-conversion with immediate (literal) values as the sources for simple sets in the THEN and ELSE blocks. The test checks that the conditional-zero instruction (czero.eqz/nez) is emitted as part of the resulting branchless instruction sequence. gcc/ChangeLog: * config/riscv/zicond.md: Support immediates for czero.eqz/czero.nez through a splitter. gcc/testsuite/ChangeLog: * gcc.target/riscv/zicond-ifconv-imm.c: New test. Signed-off-by: Philipp Tomsich --- gcc/config/riscv/zicond.md | 20 +++++++++++++++++++ .../gcc.target/riscv/zicond-ifconv-imm.c | 19 ++++++++++++++++++ 2 files changed, 39 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-ifconv-imm.c diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md index 278e3a67802..19d0b35585b 100644 --- a/gcc/config/riscv/zicond.md +++ b/gcc/config/riscv/zicond.md @@ -28,3 +28,23 @@ (define_insn "*czero." (match_operand:DI 2 "register_operand" "r")))] "TARGET_ZICOND" "czero.\t%0,%2,%1") + +;; Zicond does not have immediate forms, so we need to do extra work +;; to support these: if we encounter a vt.maskc/n with an immediate, +;; we split this into a load-immediate followed by a czero.eqz/nez. +(define_split + [(set (match_operand:DI 0 "register_operand") + (and:DI (neg:DI (match_operator:DI 1 "equality_operator" + [(match_operand:DI 2 "register_operand") + (const_int 0)])) + (match_operand:DI 3 "immediate_operand"))) + (clobber (match_operand:DI 4 "register_operand"))] + "TARGET_ZICOND" + [(set (match_dup 4) (match_dup 3)) + (set (match_dup 0) (and:DI (neg:DI (match_dup 1)) + (match_dup 4)))] +{ + /* Eliminate the clobber/temporary, if it is not needed. */ + if (!rtx_equal_p (operands[0], operands[2])) + operands[4] = operands[0]; +}) diff --git a/gcc/testsuite/gcc.target/riscv/zicond-ifconv-imm.c b/gcc/testsuite/gcc.target/riscv/zicond-ifconv-imm.c new file mode 100644 index 00000000000..f410537a4f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-ifconv-imm.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +/* Each function below should emit a czero.nez instruction */ + +long +foo0 (long a, long b, long c) +{ + if (c) + a = 0; + else + a = 5; + return a; +} + +/* { dg-final { scan-assembler-times "czero.nez\t" 1 } } */ +/* { dg-final { scan-assembler-not "beqz\t" } } */ +/* { dg-final { scan-assembler-not "bnez\t" } } */ From patchwork Fri Feb 10 22:41:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 64722 X-Patchwork-Delegate: jlaw@ventanamicro.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 25C8A394243F for ; Fri, 10 Feb 2023 22:42:52 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [IPv6:2a00:1450:4864:20::634]) by sourceware.org (Postfix) with ESMTPS id 8560C385B50C for ; Fri, 10 Feb 2023 22:41:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8560C385B50C Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-ej1-x634.google.com with SMTP id sa10so19437403ejc.9 for ; Fri, 10 Feb 2023 14:41:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=r0VG19KAi8YPlbr+YiChDKjn4ByQFjvWavXUaw7v5+w=; b=qnaBcfShTv8Pv0du882wlIwbIYabdVU1nNJBYaj7n0BptB5+A5RxKonrU9gkGZRv06 uhN/zKCJkbxlp7IFKbW/x+ZxQEfVtVzd4n7G2fBB6LCJ9D5bqT5UIEJQA/gELLyZ8ioi 0IZkfuQ0GgCpdV3MaYHiDhpvZVCkgCiOvsKXHR3z8Vfe9qEJkeWNaPMgutmlSZV6uvl+ arPGI0Fj3/8QpCvjcmqqYPpGQDr7BtRpU0G7rieP8wU4lXz2fQlFHEEuf7LkSvz86WRL 3UmhyuLWxGAhSZjOIgWH5WpmfH+/U80ytKlyNpAJlOK7qEylZ8Tyavdl8Z0J4bjcQ8j4 LP4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r0VG19KAi8YPlbr+YiChDKjn4ByQFjvWavXUaw7v5+w=; b=sulIIlydSGTp9M9vhZKtRY5c8DUGovcx0308FhPztzP6YZeLR2Dnn/Q15exhthThSu rZ22Wxip/f+9qfGLxy1sMPuTTz43dy3MWCBg09I9oqMuBFnK1rDH/hWa41xoT9FSmxTr 8rD6IReOhwsnnB18N0hv3n0aNeNZHGrV37TBhbffnAEee/XXcC5ggE6WgNpLpu6LvVkY rrnPQNuimvgvHzgo1bKZQ2IvEqHBU9s6wwk7unyUJ2ihxgpFH012a97ugWj/MuVNFVSa wm1WN+ac/xI6efuyOhIeC6hAvQ9fJIVI8DFiJB+cJQM8erthus6uf5g+OYeLIYTwvzry 3BMg== X-Gm-Message-State: AO0yUKX564eHYQjnQIWMLdogsZkv4ckw1vH1vd/GLNCFJPU7DB5TGi26 U5USivSIO+nlnfDsoBbMKdU7U45g+Cjdm4i6MXI= X-Google-Smtp-Source: AK7set/1V0TKBF9EtgO7+ATAhwhIiqQqa62Bv5rBEPH75LA01dBD+9CfYMynajTQ96kA4StkrAUsXw== X-Received: by 2002:a17:906:9f0c:b0:8af:7b80:82ba with SMTP id fy12-20020a1709069f0c00b008af7b8082bamr2339151ejc.20.1676068918790; Fri, 10 Feb 2023 14:41:58 -0800 (PST) Received: from ubuntu-focal.. ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id c15-20020a17090603cf00b0088bd62b1cbbsm2976956eja.192.2023.02.10.14.41.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 14:41:58 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Kito Cheng , Christoph Muellner , Palmer Dabbelt , Andrew Waterman , Vineet Gupta , Philipp Tomsich Subject: [RFC PATCH v1 05/10] RISC-V: Support noce_try_store_flag_mask as czero.eqz/czero.nez Date: Fri, 10 Feb 2023 23:41:45 +0100 Message-Id: <20230210224150.2801962-6-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230210224150.2801962-1-philipp.tomsich@vrull.eu> References: <20230210224150.2801962-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" When if-conversion in noce_try_store_flag_mask starts the sequence off with an order-operator, our patterns for czero.eqz/nez will receive the result of the order-operator as a register argument; consequently, they can't know that the result will be either 1 or 0. To convey this information (and make czero.eqz/nez applicable), we wrap the result of the order-operator in a eq/ne against (const_int 0). This commit adds the split pattern to handle these cases. During if-conversion, if noce_try_store_flag_mask succeeds, we may see if (cur < next) { next = 0; } transformed into 27: r82:SI=ltu(r76:DI,r75:DI) REG_DEAD r76:DI 28: r81:SI=r82:SI^0x1 REG_DEAD r82:SI 29: r80:DI=zero_extend(r81:SI) REG_DEAD r81:SI This currently escapes the combiner, as RISC-V does not have a pattern to apply the 'slt' instruction to 'geu' verbs. By adding a pattern in this commit, we match such cases. gcc/ChangeLog: * config/riscv/predicates.md (anyge_operator): Define. (anygt_operator): Same. (anyle_operator): Same. (anylt_operator): Same. * config/riscv/riscv.md: Helpers for ge(u) & le(u). * config/riscv/zicond.md: Add split to wrap an an order-operator suitably for generating czero.eqz/nez gcc/testsuite/ChangeLog: * gcc.target/riscv/zicond-le-02.c: New test. * gcc.target/riscv/zicond-lt-03.c: New test. Signed-off-by: Philipp Tomsich --- gcc/config/riscv/predicates.md | 12 +++++ gcc/config/riscv/riscv.md | 26 ++++++++++ gcc/config/riscv/zicond.md | 50 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/zicond-le-02.c | 11 ++++ gcc/testsuite/gcc.target/riscv/zicond-lt-03.c | 16 ++++++ 5 files changed, 115 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-le-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-lt-03.c diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 034d088c656..6b6f867824e 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -204,6 +204,18 @@ (define_predicate "modular_operator" (define_predicate "equality_operator" (match_code "eq,ne")) +(define_predicate "anyge_operator" + (match_code "ge,geu")) + +(define_predicate "anygt_operator" + (match_code "gt,gtu")) + +(define_predicate "anyle_operator" + (match_code "le,leu")) + +(define_predicate "anylt_operator" + (match_code "lt,ltu")) + (define_predicate "order_operator" (match_code "eq,ne,lt,ltu,le,leu,ge,geu,gt,gtu")) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 7c632bb4d65..6f255a80379 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2668,6 +2668,19 @@ (define_insn "*sge_" [(set_attr "type" "slt") (set_attr "mode" "")]) +(define_split + [(set (match_operand:GPR 0 "register_operand") + (match_operator:GPR 1 "anyle_operator" + [(match_operand:X 2 "register_operand") + (match_operand:X 3 "register_operand")]))] + "TARGET_ZICOND" + [(set (match_dup 0) (match_dup 4)) + (set (match_dup 0) (eq:GPR (match_dup 0) (const_int 0)))] + { + operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == LE ? LT : LTU, + mode, operands[3], operands[2]); + }) + (define_insn "*slt_" [(set (match_operand:GPR 0 "register_operand" "= r") (any_lt:GPR (match_operand:X 1 "register_operand" " r") @@ -2689,6 +2702,19 @@ (define_insn "*sle_" [(set_attr "type" "slt") (set_attr "mode" "")]) +(define_split + [(set (match_operand:GPR 0 "register_operand") + (match_operator:GPR 1 "anyge_operator" + [(match_operand:X 2 "register_operand") + (match_operand:X 3 "register_operand")]))] + "TARGET_ZICOND" + [(set (match_dup 0) (match_dup 4)) + (set (match_dup 0) (eq:GPR (match_dup 0) (const_int 0)))] +{ + operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GE ? LT : LTU, + mode, operands[2], operands[3]); +}) + ;; ;; .................... ;; diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md index 19d0b35585b..9d1ce067150 100644 --- a/gcc/config/riscv/zicond.md +++ b/gcc/config/riscv/zicond.md @@ -48,3 +48,53 @@ (define_split if (!rtx_equal_p (operands[0], operands[2])) operands[4] = operands[0]; }) + +;; Make order operators digestible to the vt.maskc logic by +;; wrapping their result in a comparison against (const_int 0). + +;; "a >= b" is "!(a < b)" +(define_split + [(set (match_operand:X 0 "register_operand") + (and:X (neg:X (match_operator:X 1 "anyge_operator" + [(match_operand:X 2 "register_operand") + (match_operand:X 3 "arith_operand")])) + (match_operand:X 4 "register_operand"))) + (clobber (match_operand:X 5 "register_operand"))] + "TARGET_ZICOND" + [(set (match_dup 5) (match_dup 6)) + (set (match_dup 0) (and:X (neg:X (eq:X (match_dup 5) (const_int 0))) + (match_dup 4)))] +{ + operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GE ? LT : LTU, + mode, operands[2], operands[3]); +}) + +;; "a > b" +(define_split + [(set (match_operand:X 0 "register_operand") + (and:X (neg:X (match_operator:X 1 "anygt_operator" + [(match_operand:X 2 "register_operand") + (match_operand:X 3 "arith_operand")])) + (match_operand:X 4 "register_operand"))) + (clobber (match_operand:X 5 "register_operand"))] + "TARGET_ZICOND" + [(set (match_dup 5) (match_dup 1)) + (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 5) (const_int 0))) + (match_dup 4)))]) + +;; "a <= b" is "!(a > b)" +(define_split + [(set (match_operand:X 0 "register_operand") + (and:X (neg:X (match_operator:X 1 "anyle_operator" + [(match_operand:X 2 "register_operand") + (match_operand:X 3 "arith_operand")])) + (match_operand:X 4 "register_operand"))) + (clobber (match_operand:X 5 "register_operand"))] + "TARGET_ZICOND" + [(set (match_dup 5) (match_dup 6)) + (set (match_dup 0) (and:X (neg:X (eq:X (match_dup 5) (const_int 0))) + (match_dup 4)))] +{ + operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == LE ? GT : GTU, + mode, operands[2], operands[3]); +}) diff --git a/gcc/testsuite/gcc.target/riscv/zicond-le-02.c b/gcc/testsuite/gcc.target/riscv/zicond-le-02.c new file mode 100644 index 00000000000..32844bc0278 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-le-02.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" "-Oz" } } */ + +long long le2 (long long a, long long b, long long c) +{ + return (a <= c) ? b : 0; +} + +/* { dg-final { scan-assembler-times "sgt\t" 1 } } */ +/* { dg-final { scan-assembler-times "czero.nez\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zicond-lt-03.c b/gcc/testsuite/gcc.target/riscv/zicond-lt-03.c new file mode 100644 index 00000000000..1c4f0d6ba10 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-lt-03.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64 -mbranch-cost=4" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" "-Oz" } } */ + +long long sink (long long); + +long long lt3 (long long a, long long b) +{ + if (a < b) + b = 0; + + return sink(b); +} + +/* { dg-final { scan-assembler-times "slt\t" 1 } } */ +/* { dg-final { scan-assembler-times "czero.nez\t" 1 } } */ From patchwork Fri Feb 10 22:41:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 64724 X-Patchwork-Delegate: jlaw@ventanamicro.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6C0A23839DFA for ; Fri, 10 Feb 2023 22:43:01 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) by sourceware.org (Postfix) with ESMTPS id 5CA223843854 for ; Fri, 10 Feb 2023 22:42:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5CA223843854 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-ej1-x633.google.com with SMTP id dr8so19400213ejc.12 for ; Fri, 10 Feb 2023 14:42:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6bfJpaogWuH77eXZwmaIpN+g5lhozVj+w4TJU6MS6/k=; b=BndEm5MLXi4xHmXtnJ4bPJynAFV1nkuov1xu0i70I0wzXEsq8J+Ovau57tmjbSa06V HvnWRFAhAL+ZnLYlpngfN4FjZ1mtUT0JRo2WCGwXnZU9L/lEE/3prKTd/Z5Uhbtt1t3e b1oi1dpOnxaTnyp3tU7CY3pz4Qsb/hNnK/s08gLZXUZHuOOYOUrmR/pvzXw2j3cbErDc R5rpBFiSDruHuus0BbZ4KOaZ47WLsynSBNQNbrlV7eVWVrEDcKroXbXc20/a7PK9vON6 U9NSxw/T3LE4vxp3oDN9vh/UTiF0rw2I4aOg15+7576/O1ryAVCKQ+v8Z3hfO0z25wmo kSFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6bfJpaogWuH77eXZwmaIpN+g5lhozVj+w4TJU6MS6/k=; b=tdvjkMSzDmEdL/Zup1cXBRqGgbyoO59Dw/l8bQrS8uxpS654dIEmNW0Be8QWT1TvLC r8pe6sK7MUuY1QkNihj2TbwDKLC/QpfhOhb9L3FsO6pMLOUt8wOLRtxrcD8V6nPvhdsy +DL0+9Ywm28Vq3Jmt5EpB/yVZ6r6IS3fNkmlCaZbcfJSVi1kG1pr0ugppXVhLebaxkCY ckZTyVqzbgt3HTD1tgR296nkIOpRgKuiLFoPgBmVW+CdyegnBHPTTqt2olnM2sLUzp2K HE6EulcsGWDEENSBm3g9tpEvFf/tlZ8eVbdPx+IRFLGYfCwds/cRik9Ayh8yHUU7uj7K KLcg== X-Gm-Message-State: AO0yUKVrTXj9Comqyy6PJkUuzhdstxxHwLARdYq2UwXFNOgZ7JoE9/eZ my/DMc1GYnpkdUPM3sT/10DyI7a8p9datJ2d/GQ= X-Google-Smtp-Source: AK7set9hc9SseVevSCtLuvF1+q6olPw9d8ZfUonj4QPzpvtFMpKL3siDHfoO4dhuhyc/nwTF79nlLQ== X-Received: by 2002:a17:907:b13:b0:87f:2d81:1d2a with SMTP id h19-20020a1709070b1300b0087f2d811d2amr17283695ejl.35.1676068919776; Fri, 10 Feb 2023 14:41:59 -0800 (PST) Received: from ubuntu-focal.. ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id c15-20020a17090603cf00b0088bd62b1cbbsm2976956eja.192.2023.02.10.14.41.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 14:41:59 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Kito Cheng , Christoph Muellner , Palmer Dabbelt , Andrew Waterman , Vineet Gupta , Philipp Tomsich Subject: [RFC PATCH v1 06/10] RISC-V: Recognize sign-extract + and cases for czero.eqz/nez Date: Fri, 10 Feb 2023 23:41:46 +0100 Message-Id: <20230210224150.2801962-7-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230210224150.2801962-1-philipp.tomsich@vrull.eu> References: <20230210224150.2801962-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Users might use explicit arithmetic operations to create a mask and then and it, in a sequence like cond = (bits >> SHIFT) & 1; mask = ~(cond - 1); val &= mask; which will present as a single-bit sign-extract. Dependening on what combination of XVentanaCondOps and Zbs are available, this will map to the following sequences: - bexti + czero, if both Zbs and XVentanaCondOps are present - andi + czero, if only XVentanaCondOps is available and the sign-extract is operating on bits 10:0 (bit 11 can't be reached, as the immediate is sign-extended) - slli + srli + and, otherwise. gcc/ChangeLog: * config/riscv/zicond.md: Recognize SIGN_EXTRACT of a single-bit followed by AND for Zicond. gcc/testsuite/ChangeLog: * gcc.target/riscv/zicond-le-01.c: New test. Signed-off-by: Philipp Tomsich --- gcc/config/riscv/zicond.md | 45 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/zicond-le-01.c | 16 +++++++ 2 files changed, 61 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-le-01.c diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md index 9d1ce067150..15fdaa539f1 100644 --- a/gcc/config/riscv/zicond.md +++ b/gcc/config/riscv/zicond.md @@ -98,3 +98,48 @@ (define_split operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == LE ? GT : GTU, mode, operands[2], operands[3]); }) + +;; Users might use explicit arithmetic operations to create a mask and +;; then and it, in a sequence like +;; cond = (bits >> SHIFT) & 1; +;; mask = ~(cond - 1); +;; val &= mask; +;; which will present as a single-bit sign-extract in the combiner. +;; +;; This will give rise to any of the following cases: +;; - with Zbs and XVentanaCondOps: bexti + vt.maskc +;; - with XVentanaCondOps (but w/o Zbs): +;; - andi + vt.maskc, if the mask is representable in the immediate +;; (which requires extra care due to the immediate +;; being sign-extended) +;; - slli + srli + and +;; - otherwise: slli + srli + and + +;; With Zbb, we have bexti for all possible bits... +(define_split + [(set (match_operand:X 0 "register_operand") + (and:X (sign_extract:X (match_operand:X 1 "register_operand") + (const_int 1) + (match_operand 2 "immediate_operand")) + (match_operand:X 3 "register_operand"))) + (clobber (match_operand:X 4 "register_operand"))] + "TARGET_ZICOND && TARGET_ZBS" + [(set (match_dup 4) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2))) + (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 4) (const_int 0))) + (match_dup 3)))]) + +;; ...whereas RV64I only allows us access to bits 0..10 in a single andi. +(define_split + [(set (match_operand:X 0 "register_operand") + (and:X (sign_extract:X (match_operand:X 1 "register_operand") + (const_int 1) + (match_operand 2 "immediate_operand")) + (match_operand:X 3 "register_operand"))) + (clobber (match_operand:X 4 "register_operand"))] + "TARGET_ZICOND && !TARGET_ZBS && (UINTVAL (operands[2]) < 11)" + [(set (match_dup 4) (and:X (match_dup 1) (match_dup 2))) + (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 4) (const_int 0))) + (match_dup 3)))] +{ + operands[2] = GEN_INT(1 << UINTVAL(operands[2])); +}) diff --git a/gcc/testsuite/gcc.target/riscv/zicond-le-01.c b/gcc/testsuite/gcc.target/riscv/zicond-le-01.c new file mode 100644 index 00000000000..e5902d1ca5b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-le-01.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64 -mbranch-cost=4" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" "-Oz" } } */ + +long long sink (long long); + +long long le1 (long long a, long long b) +{ + if (a <= b) + b = 0; + + return sink(b); +} + +/* { dg-final { scan-assembler-times "sgt\t" 1 } } */ +/* { dg-final { scan-assembler-times "czero.eqz\t" 1 } } */ From patchwork Fri Feb 10 22:41:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 64726 X-Patchwork-Delegate: jlaw@ventanamicro.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 78B1B38845F9 for ; Fri, 10 Feb 2023 22:43:25 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [IPv6:2a00:1450:4864:20::634]) by sourceware.org (Postfix) with ESMTPS id 639A0383FB93 for ; Fri, 10 Feb 2023 22:42:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 639A0383FB93 Authentication-Results: sourceware.org; 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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id c15-20020a17090603cf00b0088bd62b1cbbsm2976956eja.192.2023.02.10.14.41.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 14:42:00 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Kito Cheng , Christoph Muellner , Palmer Dabbelt , Andrew Waterman , Vineet Gupta , Philipp Tomsich Subject: [RFC PATCH v1 07/10] RISC-V: Recognize bexti in negated if-conversion Date: Fri, 10 Feb 2023 23:41:47 +0100 Message-Id: <20230210224150.2801962-8-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230210224150.2801962-1-philipp.tomsich@vrull.eu> References: <20230210224150.2801962-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" While the positive case "if ((bits >> SHAMT) & 1)" for SHAMT 0..10 can trigger conversion into efficient branchless sequences - with Zbs (bexti + neg + and) - with Zicond (andi + czero.nez) the inverted/negated case results in andi a5,a0,1024 seqz a5,a5 neg a5,a5 and a5,a5,a1 due to how the sequence presents to the combine pass. This adds an additional splitter to reassociate the polarity reversed case into bexti + addi, if Zbs is present. gcc/ChangeLog: * config/riscv/zicond.md: Add split to reassociate "andi + seqz + neg" into "bexti + addi". Signed-off-by: Philipp Tomsich --- gcc/config/riscv/zicond.md | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md index 15fdaa539f1..0aad61c7009 100644 --- a/gcc/config/riscv/zicond.md +++ b/gcc/config/riscv/zicond.md @@ -143,3 +143,13 @@ (define_split { operands[2] = GEN_INT(1 << UINTVAL(operands[2])); }) + +(define_split + [(set (match_operand:X 0 "register_operand") + (neg:X (eq:X (zero_extract:X (match_operand:X 1 "register_operand") + (const_int 1) + (match_operand 2 "immediate_operand")) + (const_int 0))))] + "!TARGET_ZICOND && TARGET_ZBS" + [(set (match_dup 0) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2))) + (set (match_dup 0) (plus:X (match_dup 0) (const_int -1)))]) From patchwork Fri Feb 10 22:41:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 64725 X-Patchwork-Delegate: jlaw@ventanamicro.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A89D4394B023 for ; Fri, 10 Feb 2023 22:43:24 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by sourceware.org (Postfix) with ESMTPS id 7D8A43839DE6 for ; Fri, 10 Feb 2023 22:42:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7D8A43839DE6 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-ej1-x62e.google.com with SMTP id dr8so19400363ejc.12 for ; Fri, 10 Feb 2023 14:42:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tw+cw44dSezHP0okSUBWx0uR0iTmFc7R8//TepjhLmw=; b=eM4o2lZy/2IxzpXt2TG3yuF7L4AH/B7UaCm1Zsf22MhZ6iXmjJjg7JJeIYdjs5MYpO ErBX9iIxv1U1b5GzJFeMFWMVvhNoGSO7nF3ZkocMCT4DLkMRgmb0sTcOVbiUwGrBEKtn zJarMHoBw9V1ppWsZvaYHsw3dvEP9P2VrOkCgG6fnU5sE+sPCEOHay5ShoHDQdlhZf3j Tyfl1g+9T7bfFeyY6XXo4fmykl/stFXo1RiOqfBf8P5ZLrQH1WyWl06z7PCHiCMpgRfq KcU22FmGv/O8ECrOoovE2UjdWgXuFCBsJuNABFQZJSEzddR9gWMTK3CLSkk/nn7u6Gc3 olCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tw+cw44dSezHP0okSUBWx0uR0iTmFc7R8//TepjhLmw=; b=iZNxlF3B0h/Zs7SsFRLnwC1aTIQZUNIMLuieJs7PF7M1k+h+gxkhhelyKhNs2SawDn Zg5XLaWazCGv7xMFe5k/qLhjGMPLtfr8CgcEGvsvGyleDpHeDF036pos3LymbmBUp35z 2qwQkoUyObwe/iz/iitwiUkysF4ih+uWkPXTWqG//6+eGAEAOHxYN46ofnQNKwOxxSbS 6vf0hdo6rqyOx2WS9e8Q2kYHBLHbklDEul1/RjP5hnw9aaPH5hG2edA+hWX3R3WYqsXd lhtcPVMu528tKO/MJU4leesAmLVbp9BGyF0kyNZQ/457pYheyruaoaLZd075xWeR1FHx v51w== X-Gm-Message-State: AO0yUKX/WINFg0AlWMQ6oJi3AF+arAF6CyzrTdD6x1VAQENSGkY7nJ0D aNKlSB/EvT89YcVUvnlUjbmtoOeu4Agna2RqhiA= X-Google-Smtp-Source: AK7set9AcGUtV0GdCgUkV8FVZ70IkuQvrju3egVd+X3g+PnBDxATvNNSmQlw0gbRYjW5f/lyAhuVeQ== X-Received: by 2002:a17:906:a0c:b0:87b:db29:61af with SMTP id w12-20020a1709060a0c00b0087bdb2961afmr16757181ejf.24.1676068921767; Fri, 10 Feb 2023 14:42:01 -0800 (PST) Received: from ubuntu-focal.. ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id c15-20020a17090603cf00b0088bd62b1cbbsm2976956eja.192.2023.02.10.14.42.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 14:42:01 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Kito Cheng , Christoph Muellner , Palmer Dabbelt , Andrew Waterman , Vineet Gupta , Philipp Tomsich Subject: [RFC PATCH v1 08/10] ifcvt: add if-conversion to conditional-zero instructions Date: Fri, 10 Feb 2023 23:41:48 +0100 Message-Id: <20230210224150.2801962-9-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230210224150.2801962-1-philipp.tomsich@vrull.eu> References: <20230210224150.2801962-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Some architectures, as it the case on RISC-V with the proposed ZiCondOps and the vendor-defined XVentanaCondOps, define a conditional-zero instruction that is equivalent to: - the positive form: rd = (rc != 0) ? rs : 0 - the negated form: rd = (rc == 0) ? rs : 0 While noce_try_store_flag_mask will somewhat work for this case, it will generate a number of atomic RTX that will misdirect the cost calculation and may be too long (i.e., 4 RTX and more) to successfully merge at combine-time. Instead, we add two new transforms that attempt to build up what we define as the canonical form of a conditional-zero expression: (set (match_operand 0 "register_operand" "=r") (and (neg (eq_or_ne (match_operand 1 "register_operand" "r") (const_int 0))) (match_operand 2 "register_operand" "r"))) Architectures that provide a conditional-zero are thus expected to define an instruction matching this pattern in their backend. Based on this, we support the following cases: - noce_try_condzero: a ? a : b a ? b : 0 (and then/else swapped) !a ? b : 0 (and then/else swapped) - noce_try_condzero_arith: conditional-plus, conditional-minus, conditional-and, conditional-or, conditional-xor, conditional-shift, conditional-and Given that this is hooked into the CE passes, it is less powerful than a tree-pass (e.g., it can not transform cases where an extension, such as for uint16_t operations is in either the then or else-branch together with the arithmetic) but already covers a good array of cases and triggers across SPEC CPU 2017. Adding transformations in a tree pass should come in a future improvement. gcc/ChangeLog: * ifcvt.cc (noce_emit_insn): Add prototype. (noce_emit_condzero): Helper for noce_try_condzero and noce_try_condzero_arith transforms. (noce_try_condzero): New transform. (noce_try_condzero_arith): New transform for conditional arithmetic that can be built up by exploiting that the conditional-zero instruction will inject 0, which acts as the neutral element for operations. (noce_process_if_block): Call noce_try_condzero and noce_try_condzero_arith. gcc/testsuite/ChangeLog: * gcc.target/riscv/xventanacondops-and-01.c: New test. * gcc.target/riscv/xventanacondops-and-02.c: New test. * gcc.target/riscv/xventanacondops-eq-01.c: New test. * gcc.target/riscv/xventanacondops-eq-02.c: New test. * gcc.target/riscv/xventanacondops-lt-01.c: New test. * gcc.target/riscv/xventanacondops-ne-01.c: New test. * gcc.target/riscv/xventanacondops-xor-01.c: New test. Signed-off-by: Philipp Tomsich --- gcc/ifcvt.cc | 216 ++++++++++++++++++ .../gcc.target/riscv/zicond-and-01.c | 16 ++ .../gcc.target/riscv/zicond-and-02.c | 15 ++ gcc/testsuite/gcc.target/riscv/zicond-eq-01.c | 11 + gcc/testsuite/gcc.target/riscv/zicond-eq-02.c | 14 ++ gcc/testsuite/gcc.target/riscv/zicond-lt-01.c | 16 ++ gcc/testsuite/gcc.target/riscv/zicond-ne-01.c | 10 + .../gcc.target/riscv/zicond-xor-01.c | 14 ++ 8 files changed, 312 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-and-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-and-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-eq-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-eq-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-lt-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-ne-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/zicond-xor-01.c diff --git a/gcc/ifcvt.cc b/gcc/ifcvt.cc index 008796838f7..7ac3bd8f18e 100644 --- a/gcc/ifcvt.cc +++ b/gcc/ifcvt.cc @@ -97,6 +97,7 @@ static int find_if_case_2 (basic_block, edge, edge); static int dead_or_predicable (basic_block, basic_block, basic_block, edge, int); static void noce_emit_move_insn (rtx, rtx); +static rtx_insn *noce_emit_insn (rtx); static rtx_insn *block_has_only_trap (basic_block); static void need_cmov_or_rewire (basic_block, hash_set *, hash_map *); @@ -787,6 +788,9 @@ static rtx noce_get_alt_condition (struct noce_if_info *, rtx, rtx_insn **); static int noce_try_minmax (struct noce_if_info *); static int noce_try_abs (struct noce_if_info *); static int noce_try_sign_mask (struct noce_if_info *); +static rtx noce_emit_condzero (struct noce_if_info *, rtx, bool = false); +static int noce_try_condzero (struct noce_if_info *); +static int noce_try_condzero_arith (struct noce_if_info *); /* Return the comparison code for reversed condition for IF_INFO, or UNKNOWN if reversing the condition is not possible. */ @@ -1664,6 +1668,214 @@ noce_try_addcc (struct noce_if_info *if_info) return FALSE; } +/* Helper to noce_try_condzero: cond ? a : 0. */ +static rtx +noce_emit_condzero (struct noce_if_info *if_info, rtx a, bool reverse) +{ + /* The canonical form for a conditional-zero-or-value is: + (set (match_operand 0 "register_operand" "=r") + (and (neg (eq_or_ne (match_operand 1 "register_operand" "r") + (const_int 0))) + (match_operand 2 "register_operand" "r"))) + */ + + machine_mode opmode = GET_MODE (if_info->x); + enum rtx_code code = GET_CODE (if_info->cond); + rtx cond; + rtx op_a = XEXP (if_info->cond, 0); + rtx op_b = XEXP (if_info->cond, 1); + + /* If it is not a EQ/NE comparison against const0_rtx, canonicalize + by first synthesizing a truth-value and then building a NE + condition around it. */ + if ((code != EQ && code != NE) || XEXP (if_info->cond, 1) != const0_rtx) + { + rtx tmp = gen_reg_rtx (opmode); + + start_sequence (); + cond = gen_rtx_fmt_ee (code, opmode, op_a, op_b); + if (!noce_emit_insn (gen_rtx_SET (tmp, cond))) + { + end_sequence (); + + /* If we can't emit this pattern, try to reverse it and + invert the polarity of the second test. */ + start_sequence (); + cond = gen_rtx_fmt_ee (reverse_condition (code), opmode, op_a, op_b); + if (!noce_emit_insn (gen_rtx_SET (tmp, cond))) { + end_sequence (); + return NULL_RTX; + } + + /* We have recovered by reversing the first comparison, + so we need change the second one around as well... */ + reverse = !reverse; + } + rtx_insn *seq = get_insns (); + end_sequence (); + emit_insn (seq); + + /* Set up the second comparison that will be embedded in the + canonical conditional-zero-or-value RTX. */ + code = NE; + op_a = tmp; + op_b = const0_rtx; + } + + cond = gen_rtx_fmt_ee (reverse ? reverse_condition (code) : code, + opmode, op_a, op_b); + + /* Build (and (neg (eq_or_ne ... const0_rtx)) (reg )) */ + rtx target = gen_reg_rtx (opmode); + rtx czero = gen_rtx_AND (opmode, gen_rtx_NEG (opmode, cond), a); + noce_emit_move_insn (target, czero); + + return target; +} + +/* Use a conditional-zero instruction for "if (test) x = 0;", if available. */ +static int +noce_try_condzero (struct noce_if_info *if_info) +{ + rtx target; + rtx_insn *seq; + int reversep = 0; + /* Keep local copies of the constituent elements of if_info, as we + may be changing them. We are not allowed to modify if_info + though, as we may fail in this function and can't leave different + semantics behind for the next functions. */ + rtx a = if_info->a; + rtx b = if_info->b; + rtx x = if_info->x; + rtx cond = if_info->cond; + enum rtx_code code = GET_CODE (cond); + rtx cond_arg0 = XEXP (cond, 0); + rtx cond_arg1 = XEXP (cond, 1); + rtx orig_b = NULL_RTX; + + if (!noce_simple_bbs (if_info)) + return FALSE; + + /* We may encounter the form "(b != 0) ? b : a", which can be + simplified to "b | ((b != 0) ? 0 : a)". */ + if (code == NE && cond_arg1 == const0_rtx && + REG_P (b) && rtx_equal_p (b, cond_arg0)) + { + orig_b = b; + b = const0_rtx; + } + + /* We may encounter the form "(b == 0) ? b : a", which can be + simplied to "(b == 0) ? 0 : a". */ + if (code == EQ && cond_arg1 == const0_rtx && + REG_P (b) && rtx_equal_p (b, cond_arg0)) + { + b = const0_rtx; + } + + start_sequence (); + + if ((a == const0_rtx && (REG_P (b) || rtx_equal_p (b, x))) + || ((reversep = (noce_reversed_cond_code (if_info) != UNKNOWN)) + && b == const0_rtx && (REG_P (a) || rtx_equal_p (a, x)))) + { + target = noce_emit_condzero(if_info, reversep ? a : b, reversep); + + /* Handle the case where we replace b in "(b != 0) ? b : a" with + with const0_rtx to then emit "b | ((b != 0) ? 0 : a)". */ + if (orig_b && target) + target = expand_simple_binop (GET_MODE (x), IOR, orig_b, + target, x, 0, OPTAB_WIDEN); + + if (target) + { + if (target != if_info->x) + noce_emit_move_insn (if_info->x, target); + + seq = end_ifcvt_sequence (if_info); + if (!seq || !targetm.noce_conversion_profitable_p (seq, if_info)) + return FALSE; + + emit_insn_before_setloc (seq, if_info->jump, + INSN_LOCATION (if_info->insn_a)); + if_info->transform_name = "noce_try_condzero"; + + return TRUE; + } + } + + end_sequence (); + + return FALSE; +} + +/* Convert "if (test) x op= a;" to a branchless sequence using the + canonical form for a conditional-zero. */ +static int +noce_try_condzero_arith (struct noce_if_info *if_info) +{ + rtx target; + rtx_insn *seq; + rtx_code op = GET_CODE (if_info->a); + const rtx arg0 = XEXP (if_info->a, 0); + const rtx arg1 = XEXP (if_info->a, 1); + + if (!noce_simple_bbs (if_info)) + return FALSE; + + /* Check for no else condition. */ + if (!rtx_equal_p (if_info->x, if_info->b)) + return FALSE; + + if (op != PLUS && op != MINUS && op != IOR && op != XOR && + op != ASHIFT && op != ASHIFTRT && op != LSHIFTRT && op != AND) + return FALSE; + + if (!rtx_equal_p (if_info->x, arg0)) + return FALSE; + + start_sequence (); + + target = noce_emit_condzero(if_info, arg1, op != AND ? true : false); + + if (target) + { + rtx op1 = if_info->x; + + if (op == AND) + { + /* Emit "tmp = x & val;" followed by "tmp |= !cond ? x : 0;" */ + op1 = expand_simple_binop (GET_MODE (if_info->x), AND, op1, + arg1, NULL_RTX, 0, OPTAB_WIDEN); + op = IOR; + } + + if (op1) + target = expand_simple_binop (GET_MODE (if_info->x), op, op1, + target, if_info->x, 0, OPTAB_WIDEN); + } + + if (target) + { + if (target != if_info->x) + noce_emit_move_insn (if_info->x, target); + + seq = end_ifcvt_sequence (if_info); + if (!seq || !targetm.noce_conversion_profitable_p (seq, if_info)) + return FALSE; + + emit_insn_before_setloc(seq, if_info->jump, + INSN_LOCATION(if_info->insn_a)); + if_info->transform_name = "noce_try_condzero_arith"; + + return TRUE; + } + + end_sequence (); + + return FALSE; +} + /* Convert "if (test) x = 0;" to "x &= -(test == 0);" */ static int @@ -3967,8 +4179,12 @@ noce_process_if_block (struct noce_if_info *if_info) { if (noce_try_addcc (if_info)) goto success; + if (noce_try_condzero (if_info)) + goto success; if (noce_try_store_flag_mask (if_info)) goto success; + if (noce_try_condzero_arith (if_info)) + goto success; if (HAVE_conditional_move && noce_try_cmove_arith (if_info)) goto success; diff --git a/gcc/testsuite/gcc.target/riscv/zicond-and-01.c b/gcc/testsuite/gcc.target/riscv/zicond-and-01.c new file mode 100644 index 00000000000..d9b0ff00756 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-and-01.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64 -mbranch-cost=4" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +long and1(long a, long b, long c, long d) +{ + if (c < d) + a &= b; + + return a; +} + +/* { dg-final { scan-assembler-times "and\t" 1 } } */ +/* { dg-final { scan-assembler-times "slt" 1 } } */ +/* { dg-final { scan-assembler-times "czero.nez" 1 } } */ +/* { dg-final { scan-assembler-times "or\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zicond-and-02.c b/gcc/testsuite/gcc.target/riscv/zicond-and-02.c new file mode 100644 index 00000000000..80f417cfb54 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-and-02.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64 -mbranch-cost=4" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +int and2(int a, int b, long c) +{ + if (c) + a &= b; + + return a; +} + +/* { dg-final { scan-assembler-times "and\t" 1 } } */ +/* { dg-final { scan-assembler-times "czero.nez" 1 } } */ +/* { dg-final { scan-assembler-times "or\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zicond-eq-01.c b/gcc/testsuite/gcc.target/riscv/zicond-eq-01.c new file mode 100644 index 00000000000..4f933c1db60 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-eq-01.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +long +eq1 (long a, long b) +{ + return (a == 0) ? b : 0; +} + +/* { dg-final { scan-assembler-times "czero.nez" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zicond-eq-02.c b/gcc/testsuite/gcc.target/riscv/zicond-eq-02.c new file mode 100644 index 00000000000..a7bc747ab1d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-eq-02.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +long +eq2 (long a, long b) +{ + if (a == 0) + return b; + + return 0; +} + +/* { dg-final { scan-assembler-times "czero.nez" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zicond-lt-01.c b/gcc/testsuite/gcc.target/riscv/zicond-lt-01.c new file mode 100644 index 00000000000..830bfc6449f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-lt-01.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +long long sink (long long); + +long long lt3 (long long a, long long b) +{ + if (a < b) + b = 0; + + return sink(b); +} + +/* { dg-final { scan-assembler-times "czero.nez\t" 1 } } */ +/* { dg-final { scan-assembler-times "slt\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zicond-ne-01.c b/gcc/testsuite/gcc.target/riscv/zicond-ne-01.c new file mode 100644 index 00000000000..f25e601ae3c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-ne-01.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +long long ne1(long long a, long long b) +{ + return (a != 0) ? b : 0; +} + +/* { dg-final { scan-assembler-times "czero.eqz" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zicond-xor-01.c b/gcc/testsuite/gcc.target/riscv/zicond-xor-01.c new file mode 100644 index 00000000000..c45a3be2680 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zicond-xor-01.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicond -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +long xor1(long crc, long poly) +{ + if (crc & 1) + crc ^= poly; + + return crc; +} + +/* { dg-final { scan-assembler-times "czero.eqz" 1 } } */ +/* { dg-final { scan-assembler-times "xor\t" 1 } } */ From patchwork Fri Feb 10 22:41:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 64721 X-Patchwork-Delegate: jlaw@ventanamicro.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4B077382E6A2 for ; Fri, 10 Feb 2023 22:42:50 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by sourceware.org (Postfix) with ESMTPS id 4CC033834E58 for ; Fri, 10 Feb 2023 22:42:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4CC033834E58 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-ej1-x632.google.com with SMTP id ud5so19515594ejc.4 for ; Fri, 10 Feb 2023 14:42:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=d4BcXTMMaGo8ATHx2aUwkLXaxPowlSQ6bXfxaoWUx24=; b=nyF7yEtSQ4YnshSjO+tTQ63it7ewntyPh0PneS1o224QzvWEwrTKtQ4F4RCb/EuBl9 qlvGkszQ+5XpJihjAEPIbO2oIt1rqoVUX2vnp8qbvHMZu/Qkxx0OZ1zvvwFszeLTSSRk dSz5OVDtJR833bFnO3OLIzN36fUBJjGXqEJkboLRUpXRRaS83Y0JTYwUImmM9oFKi64b u/5pF9ST22gXC/SVS6GO6hbj3haGHZcAX4aIdx4aeYiV47ay0gZ2jcgxwMpKqSSyzF5H /GOndBgfqkbuWWkUcLEQfd9Mb+RiAiKQj2WBpiahokI8UINXBQ1APZjL/u4r9dkFP5K/ e5/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d4BcXTMMaGo8ATHx2aUwkLXaxPowlSQ6bXfxaoWUx24=; b=vN9OxXRo8RazYQZdXF47Sk62TC5FKh5kPZrD+yCNu7KNMErnH7rAou/KVDTB0a6Foc eXdVJC+01ETunusjk9xTmssRqaAkuA0iYNl+Mq9tRfDLgDE4BlsxGH4Vd29bUmKZmLaT CZzLtWhG6pNI1COngUqUVVDHLMi+VhHRi3cLIHzcHy6MctB/bESfzy4l7qIpBGg+gDV+ Bj66jbDSLSrc+RKky675UK41hdDp1YifAmKH0OYELkCxJr87+zWhKug5k2PmUyDJgden NyBFsC/EHuaAvKQ54HZSW9tPZgCTD4fmb5FU/fBGKKG3aQSUo4s2camxcRh4nf6LCqhA 6ghQ== X-Gm-Message-State: AO0yUKW/ZDkGRVF6+TADdEE++Rq4OktoC+IitmGGF1vId1ug5pTYR5fB VG0e0csi6JfbG3Gn81A6z0/h5zQ5eXEXaysgJSk= X-Google-Smtp-Source: AK7set+m6P4W3192c3jp7yTfRFWUJWozdYx50CoppmvrZikDYvL3ruO4i61ryXoGKPSQYvynd6b7bw== X-Received: by 2002:a17:907:72cb:b0:8af:5750:917 with SMTP id du11-20020a17090772cb00b008af57500917mr3812752ejc.35.1676068922874; Fri, 10 Feb 2023 14:42:02 -0800 (PST) Received: from ubuntu-focal.. ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id c15-20020a17090603cf00b0088bd62b1cbbsm2976956eja.192.2023.02.10.14.42.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 14:42:02 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Kito Cheng , Christoph Muellner , Palmer Dabbelt , Andrew Waterman , Vineet Gupta , Philipp Tomsich Subject: [RFC PATCH v1 09/10] RISC-V: Recognize xventanacondops extension Date: Fri, 10 Feb 2023 23:41:49 +0100 Message-Id: <20230210224150.2801962-10-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230210224150.2801962-1-philipp.tomsich@vrull.eu> References: <20230210224150.2801962-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This adds the xventanacondops extension to the option parsing and as a default for the ventana-vt1 core: gcc/Changelog: * common/config/riscv/riscv-common.cc: Recognize "xventanacondops" as part of an architecture string. * config/riscv/riscv-opts.h (MASK_XVENTANACONDOPS): Define. (TARGET_XVENTANACONDOPS): Define. * config/riscv/riscv.opt: Add "riscv_xventanacondops". Signed-off-by: Philipp Tomsich --- gcc/common/config/riscv/riscv-common.cc | 2 ++ gcc/config/riscv/riscv-opts.h | 3 +++ gcc/config/riscv/riscv.opt | 3 +++ 3 files changed, 8 insertions(+) diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 999e1926db1..a77a04d68d9 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -1250,6 +1250,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"svinval", &gcc_options::x_riscv_sv_subext, MASK_SVINVAL}, {"svnapot", &gcc_options::x_riscv_sv_subext, MASK_SVNAPOT}, + {"xventanacondops", &gcc_options::x_riscv_xventanacondops, MASK_XVENTANACONDOPS}, + {NULL, NULL, 0} }; diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 61d5212da20..d80e81c6c28 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -191,4 +191,7 @@ enum stack_protector_guard { ? 0 \ : 32 << (__builtin_popcount (riscv_zvl_flags) - 1)) +#define MASK_XVENTANACONDOPS (1 << 0) +#define TARGET_XVENTANACONDOPS ((riscv_xventanacondops & MASK_XVENTANACONDOPS) != 0) + #endif /* ! GCC_RISCV_OPTS_H */ diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index e78c99382cd..6ebaad43d0e 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -233,6 +233,9 @@ int riscv_zm_subext TargetVariable int riscv_sv_subext +TargetVariable +int riscv_xventanacondops = 0 + Enum Name(isa_spec_class) Type(enum riscv_isa_spec_class) Supported ISA specs (for use with the -misa-spec= option): From patchwork Fri Feb 10 22:41:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 64727 X-Patchwork-Delegate: jlaw@ventanamicro.com Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 489CD381DC6D for ; Fri, 10 Feb 2023 22:43:57 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) by sourceware.org (Postfix) with ESMTPS id 7A19D3881D08 for ; Fri, 10 Feb 2023 22:42:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7A19D3881D08 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-ej1-x62b.google.com with SMTP id qw12so19527867ejc.2 for ; Fri, 10 Feb 2023 14:42:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Z6xP3I1SuL+pOg/X0S8tbUXWX3ICsfqZdL1HSrRo5CY=; b=Ft8754HPyhSAKXMWit7YyHuOA4kA+IrukMeN/mkjwdAhMb+8VqugifOx7EnzGK3i8A StLh1xVZQTbrhYFutxjTKo8WOFok8Cgv420ckUbhSSzNsPxxShHye2sf5Z+J7Dqisu7R s1w1pcwN7XKSFGafWAVsE7KURRk1w7pgLnqtjXVQzVhqIYfL90vlmqPqyuMfft0Hp84U 1qwTdaBCbYJq3g0JrsWutb/mUsueHe8/L4d/5E+rTwcVPRrRBprfDxeHf0VrWeYx77It sy191xvT91j/9hwshlmG/Z4Z0qI7IHhixI0Yv/uK541P+wW714yhxSAqU11NgqTIs4VE tv3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z6xP3I1SuL+pOg/X0S8tbUXWX3ICsfqZdL1HSrRo5CY=; b=nzu9j1aS3K4m//SvNbdPfv2KkFCXnT+M93YqAr+TA81XvzzP7sw0dDwzsd+dicam39 x8HmOjdOYe7KhoOPSZJKUvuYziG/o5JiHdEjkIkM0uCKOf6BQ7lVynQC6l8vYipiEL0O fzM4ki3x00oqVB04ZyRL89GKR94j8y1vX1WVlWcuq6r5vTCntlOogQT0b8HsgGYcF1Q3 taobsu4XS+IS0BmxM+n0u0aIqZxp6eXxeaInUZYW20DstSul2hgrjZejsqPXTOFYJe66 XxF3m0g4T6HCmcGTrUdqLK5Z8ZYVPHWIjfeCR6rOPhm/mh/hoIgTlbBMseMtQxtBG/ad Egzw== X-Gm-Message-State: AO0yUKWvAbHv9gWXPnguHwlh9Fga2Q2Br8HcrOqG2oLBi6OJczshWaQm 0RUN3aj2RBJ8gDf6ElzDhGQ7PvFtdH/9/HIojJo= X-Google-Smtp-Source: AK7set/u6pff2EzCVRA3pp41k4IZ6CjsKbh0t1dr1z6KTZSNtJA+KQsxjeA8BiniEhHoqJw7Um8ffA== X-Received: by 2002:a17:906:8055:b0:884:d15e:10f8 with SMTP id x21-20020a170906805500b00884d15e10f8mr18629818ejw.51.1676068923794; Fri, 10 Feb 2023 14:42:03 -0800 (PST) Received: from ubuntu-focal.. ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id c15-20020a17090603cf00b0088bd62b1cbbsm2976956eja.192.2023.02.10.14.42.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Feb 2023 14:42:03 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Kito Cheng , Christoph Muellner , Palmer Dabbelt , Andrew Waterman , Vineet Gupta , Philipp Tomsich Subject: [RFC PATCH v1 10/10] RISC-V: Support XVentanaCondOps extension Date: Fri, 10 Feb 2023 23:41:50 +0100 Message-Id: <20230210224150.2801962-11-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230210224150.2801962-1-philipp.tomsich@vrull.eu> References: <20230210224150.2801962-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" The vendor-defined XVentanaCondOps extension adds two instructions with semantics identical to Zicond. This plugs the 2 new instruction in using the canonical RTX, which also matches the combiner-input for noce_try_store_flag_mask and noce_try_store_flag, defined for conditional-zero. For documentation on XVentanaCondOps, refer to: https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.1/ventana-custom-extensions-v1.0.1.pdf gcc/ChangeLog: * config/riscv/riscv.cc (riscv_rtx_costs): Recognize idiom for conditional zero as a single instruction for TARGET_XVENTANACONDOPS. * config/riscv/riscv.md: Include xventanacondops.md. * config/riscv/zicond.md: Enable splitters for TARGET_XVENTANACONDOPS. * config/riscv/xventanacondops.md: New file. gcc/testsuite/ChangeLog: * gcc.target/riscv/xventanacondops-and-01.c: New test. * gcc.target/riscv/xventanacondops-and-02.c: New test. * gcc.target/riscv/xventanacondops-eq-01.c: New test. * gcc.target/riscv/xventanacondops-eq-02.c: New test. * gcc.target/riscv/xventanacondops-ifconv-imm.c: New test. * gcc.target/riscv/xventanacondops-le-01.c: New test. * gcc.target/riscv/xventanacondops-le-02.c: New test. * gcc.target/riscv/xventanacondops-lt-01.c: New test. * gcc.target/riscv/xventanacondops-lt-03.c: New test. * gcc.target/riscv/xventanacondops-ne-01.c: New test. * gcc.target/riscv/xventanacondops-ne-03.c: New test. * gcc.target/riscv/xventanacondops-ne-04.c: New test. * gcc.target/riscv/xventanacondops-xor-01.c: New test. Signed-off-by: Philipp Tomsich --- gcc/config/riscv/riscv.cc | 4 +-- gcc/config/riscv/riscv.md | 5 ++-- gcc/config/riscv/xventanacondops.md | 29 +++++++++++++++++++ gcc/config/riscv/zicond.md | 15 +++++----- .../gcc.target/riscv/xventanacondops-and-01.c | 16 ++++++++++ .../gcc.target/riscv/xventanacondops-and-02.c | 15 ++++++++++ .../gcc.target/riscv/xventanacondops-eq-01.c | 11 +++++++ .../gcc.target/riscv/xventanacondops-eq-02.c | 14 +++++++++ .../riscv/xventanacondops-ifconv-imm.c | 19 ++++++++++++ .../gcc.target/riscv/xventanacondops-le-01.c | 16 ++++++++++ .../gcc.target/riscv/xventanacondops-le-02.c | 11 +++++++ .../gcc.target/riscv/xventanacondops-lt-01.c | 16 ++++++++++ .../gcc.target/riscv/xventanacondops-lt-03.c | 16 ++++++++++ .../gcc.target/riscv/xventanacondops-ne-01.c | 10 +++++++ .../gcc.target/riscv/xventanacondops-ne-03.c | 13 +++++++++ .../gcc.target/riscv/xventanacondops-ne-04.c | 13 +++++++++ .../gcc.target/riscv/xventanacondops-xor-01.c | 14 +++++++++ 17 files changed, 226 insertions(+), 11 deletions(-) create mode 100644 gcc/config/riscv/xventanacondops.md create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-and-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-and-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-eq-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-eq-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ifconv-imm.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-le-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-lt-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-lt-03.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ne-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 7e69a652fc5..94ac8f350e6 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2331,8 +2331,8 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN return false; case AND: - /* czero.eqz/nez */ - if ((TARGET_ZICOND) + /* czero.eqz/nez or vt.maskc/vt.maskcn */ + if ((TARGET_ZICOND || TARGET_XVENTANACONDOPS) && mode == word_mode && GET_CODE (XEXP (x, 0)) == NEG) { diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 6f255a80379..e6b73c316cb 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2673,7 +2673,7 @@ (define_split (match_operator:GPR 1 "anyle_operator" [(match_operand:X 2 "register_operand") (match_operand:X 3 "register_operand")]))] - "TARGET_ZICOND" + "TARGET_ZICOND || TARGET_XVENTANACONDOPS" [(set (match_dup 0) (match_dup 4)) (set (match_dup 0) (eq:GPR (match_dup 0) (const_int 0)))] { @@ -2707,7 +2707,7 @@ (define_split (match_operator:GPR 1 "anyge_operator" [(match_operand:X 2 "register_operand") (match_operand:X 3 "register_operand")]))] - "TARGET_ZICOND" + "TARGET_ZICOND || TARGET_XVENTANACONDOPS" [(set (match_dup 0) (match_dup 4)) (set (match_dup 0) (eq:GPR (match_dup 0) (const_int 0)))] { @@ -3255,3 +3255,4 @@ (define_insn "riscv_prefetchi_" (include "sifive-7.md") (include "vector.md") (include "zicond.md") +(include "xventanacondops.md") diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md new file mode 100644 index 00000000000..3cca14feaf9 --- /dev/null +++ b/gcc/config/riscv/xventanacondops.md @@ -0,0 +1,29 @@ +;; Machine description for X-Ventana-CondOps +;; Copyright (C) 2022 Free Software Foundation, Inc. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +(define_code_attr vt_n [(eq "n") (ne "")]) + +(define_insn "*vt.maskc" + [(set (match_operand:DI 0 "register_operand" "=r") + (and:DI (neg:DI (eq_or_ne:DI + (match_operand:DI 1 "register_operand" "r") + (const_int 0))) + (match_operand:DI 2 "register_operand" "r")))] + "TARGET_XVENTANACONDOPS" + "vt.maskc\t%0,%2,%1") diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md index 0aad61c7009..ea518bbb5b1 100644 --- a/gcc/config/riscv/zicond.md +++ b/gcc/config/riscv/zicond.md @@ -39,7 +39,7 @@ (define_split (const_int 0)])) (match_operand:DI 3 "immediate_operand"))) (clobber (match_operand:DI 4 "register_operand"))] - "TARGET_ZICOND" + "TARGET_ZICOND || TARGET_XVENTANACONDOPS" [(set (match_dup 4) (match_dup 3)) (set (match_dup 0) (and:DI (neg:DI (match_dup 1)) (match_dup 4)))] @@ -60,7 +60,7 @@ (define_split (match_operand:X 3 "arith_operand")])) (match_operand:X 4 "register_operand"))) (clobber (match_operand:X 5 "register_operand"))] - "TARGET_ZICOND" + "TARGET_ZICOND || TARGET_XVENTANACONDOPS" [(set (match_dup 5) (match_dup 6)) (set (match_dup 0) (and:X (neg:X (eq:X (match_dup 5) (const_int 0))) (match_dup 4)))] @@ -77,7 +77,7 @@ (define_split (match_operand:X 3 "arith_operand")])) (match_operand:X 4 "register_operand"))) (clobber (match_operand:X 5 "register_operand"))] - "TARGET_ZICOND" + "TARGET_ZICOND || TARGET_XVENTANACONDOPS" [(set (match_dup 5) (match_dup 1)) (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 5) (const_int 0))) (match_dup 4)))]) @@ -90,7 +90,7 @@ (define_split (match_operand:X 3 "arith_operand")])) (match_operand:X 4 "register_operand"))) (clobber (match_operand:X 5 "register_operand"))] - "TARGET_ZICOND" + "TARGET_ZICOND || TARGET_XVENTANACONDOPS" [(set (match_dup 5) (match_dup 6)) (set (match_dup 0) (and:X (neg:X (eq:X (match_dup 5) (const_int 0))) (match_dup 4)))] @@ -123,7 +123,7 @@ (define_split (match_operand 2 "immediate_operand")) (match_operand:X 3 "register_operand"))) (clobber (match_operand:X 4 "register_operand"))] - "TARGET_ZICOND && TARGET_ZBS" + "(TARGET_ZICOND || TARGET_XVENTANACONDOPS) && TARGET_ZBS" [(set (match_dup 4) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2))) (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 4) (const_int 0))) (match_dup 3)))]) @@ -136,7 +136,8 @@ (define_split (match_operand 2 "immediate_operand")) (match_operand:X 3 "register_operand"))) (clobber (match_operand:X 4 "register_operand"))] - "TARGET_ZICOND && !TARGET_ZBS && (UINTVAL (operands[2]) < 11)" + "(TARGET_ZICOND || TARGET_XVENTANACONDOPS) + && !TARGET_ZBS && (UINTVAL (operands[2]) < 11)" [(set (match_dup 4) (and:X (match_dup 1) (match_dup 2))) (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 4) (const_int 0))) (match_dup 3)))] @@ -150,6 +151,6 @@ (define_split (const_int 1) (match_operand 2 "immediate_operand")) (const_int 0))))] - "!TARGET_ZICOND && TARGET_ZBS" + "!(TARGET_ZICOND || TARGET_XVENTANACONDOPS) && TARGET_ZBS" [(set (match_dup 0) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2))) (set (match_dup 0) (plus:X (match_dup 0) (const_int -1)))]) diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-and-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-and-01.c new file mode 100644 index 00000000000..9b26cdf0513 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-and-01.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +long and1(long a, long b, long c, long d) +{ + if (c < d) + a &= b; + + return a; +} + +/* { dg-final { scan-assembler-times "and\t" 1 } } */ +/* { dg-final { scan-assembler-times "slt" 1 } } */ +/* { dg-final { scan-assembler-times "vt.maskcn" 1 } } */ +/* { dg-final { scan-assembler-times "or\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-and-02.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-and-02.c new file mode 100644 index 00000000000..66d2ec10211 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-and-02.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +int and2(int a, int b, long c) +{ + if (c) + a &= b; + + return a; +} + +/* { dg-final { scan-assembler-times "and\t" 1 } } */ +/* { dg-final { scan-assembler-times "vt.maskcn" 1 } } */ +/* { dg-final { scan-assembler-times "or\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-eq-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-eq-01.c new file mode 100644 index 00000000000..bc877d9e81b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-eq-01.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +long +eq1 (long a, long b) +{ + return (a == 0) ? b : 0; +} + +/* { dg-final { scan-assembler-times "vt.maskcn" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-eq-02.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-eq-02.c new file mode 100644 index 00000000000..28317613ba8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-eq-02.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +long +eq2 (long a, long b) +{ + if (a == 0) + return b; + + return 0; +} + +/* { dg-final { scan-assembler-times "vt.maskcn" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-ifconv-imm.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-ifconv-imm.c new file mode 100644 index 00000000000..0012e7b669c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-ifconv-imm.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +/* Each function below should emit a vt.maskcn instruction */ + +long +foo0 (long a, long b, long c) +{ + if (c) + a = 0; + else + a = 5; + return a; +} + +/* { dg-final { scan-assembler-times "vt.maskcn\t" 1 } } */ +/* { dg-final { scan-assembler-not "beqz\t" } } */ +/* { dg-final { scan-assembler-not "bnez\t" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c new file mode 100644 index 00000000000..eb463e3c161 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zba_zbb_zbs_xventanacondops -mabi=lp64 -mbranch-cost=4" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" "-Oz" } } */ + +long long sink (long long); + +long long le1 (long long a, long long b) +{ + if (a <= b) + b = 0; + + return sink(b); +} + +/* { dg-final { scan-assembler-times "sgt\t" 1 } } */ +/* { dg-final { scan-assembler-times "vt.maskc\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-le-02.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-le-02.c new file mode 100644 index 00000000000..daa115d70c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-le-02.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zba_zbb_zbs_xventanacondops -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" "-Oz" } } */ + +long long le2 (long long a, long long b, long long c) +{ + return (a <= c) ? b : 0; +} + +/* { dg-final { scan-assembler-times "sgt\t" 1 } } */ +/* { dg-final { scan-assembler-times "vt.maskcn\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-lt-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-lt-01.c new file mode 100644 index 00000000000..18762ee2bd0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-lt-01.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +long long sink (long long); + +long long lt3 (long long a, long long b) +{ + if (a < b) + b = 0; + + return sink(b); +} + +/* { dg-final { scan-assembler-times "vt.maskcn\t" 1 } } */ +/* { dg-final { scan-assembler-times "slt\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-lt-03.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-lt-03.c new file mode 100644 index 00000000000..f671f357f91 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-lt-03.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zba_zbb_zbs_xventanacondops -mabi=lp64 -mbranch-cost=4" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" "-Oz" } } */ + +long long sink (long long); + +long long lt3 (long long a, long long b) +{ + if (a < b) + b = 0; + + return sink(b); +} + +/* { dg-final { scan-assembler-times "slt\t" 1 } } */ +/* { dg-final { scan-assembler-times "vt.maskcn\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-01.c new file mode 100644 index 00000000000..be8375ba5cf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-01.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +long long ne1(long long a, long long b) +{ + return (a != 0) ? b : 0; +} + +/* { dg-final { scan-assembler-times "vt.maskc" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c new file mode 100644 index 00000000000..4a762a1ed61 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64 -mtune=thead-c906" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" "-Oz" } } */ + +long long ne3(long long a, long long b) +{ + if (a != 0) + return b; + + return 0; +} + +/* { dg-final { scan-assembler-times "vt.maskc" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c new file mode 100644 index 00000000000..18b35ac7070 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64 -mtune=thead-c906" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +long long ne4(long long a, long long b) +{ + if (a != 0) + return 0; + + return b; +} + +/* { dg-final { scan-assembler-times "vt.maskcn" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c new file mode 100644 index 00000000000..43020790a22 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +long xor1(long crc, long poly) +{ + if (crc & 1) + crc ^= poly; + + return crc; +} + +/* { dg-final { scan-assembler-times "vt.maskc" 1 } } */ +/* { dg-final { scan-assembler-times "xor\t" 1 } } */