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[58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 07 Feb 2023 14:48:06 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: c1vUbRWtUKQC+qjT2yn9DWr1xkXR0sr67TsIYmyi3rjB10lIkajZCzZ0B+HO5 rpt8nd4ubykk5gc//6q69r4RmSMDerRY13uWzQUB4aHmRyl2tgt56xu7LzNDnJEA8KZaqnT RNX1uUJmKCPa6htE/HeUsLamQnca/xrkbZalUEXcnWn03dw4fmxH/ynKAciuC6YRMhIeW7V mz9pbXWv2PlSPdYPQwKx53gOF9CYjw+i9pBl2bhDF5rXyH29EZP/FgSUPL1t5qTDo9v1yDG oknuSfxw/VrSWdemx4tJHFjz1ECofq3JwhABdGHVHHiZHZ6asLOoKSY79DFfAjqQik4wS/u oq48mvxOoR7/Vi0hfQcT3OhDRz/SjBa5C1r3ZpXVCLCWTyGVE8TUDy1rz7pUmsnu/921uoO X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vwmul.v C++ api TETS Date: Tue, 7 Feb 2023 14:48:05 +0800 Message-Id: <20230207064805.45508-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vwmul_vv-1.C: New test. * g++.target/riscv/rvv/base/vwmul_vv-2.C: New test. * g++.target/riscv/rvv/base/vwmul_vv-3.C: New test. * g++.target/riscv/rvv/base/vwmul_vv_mu-1.C: New test. * g++.target/riscv/rvv/base/vwmul_vv_mu-2.C: New test. * g++.target/riscv/rvv/base/vwmul_vv_mu-3.C: New test. * g++.target/riscv/rvv/base/vwmul_vv_tu-1.C: New test. * g++.target/riscv/rvv/base/vwmul_vv_tu-2.C: New test. * g++.target/riscv/rvv/base/vwmul_vv_tu-3.C: New test. * g++.target/riscv/rvv/base/vwmul_vv_tum-1.C: New test. * g++.target/riscv/rvv/base/vwmul_vv_tum-2.C: New test. * g++.target/riscv/rvv/base/vwmul_vv_tum-3.C: New test. * g++.target/riscv/rvv/base/vwmul_vv_tumu-1.C: New test. * g++.target/riscv/rvv/base/vwmul_vv_tumu-2.C: New test. * g++.target/riscv/rvv/base/vwmul_vv_tumu-3.C: New test. * g++.target/riscv/rvv/base/vwmul_vx-1.C: New test. * g++.target/riscv/rvv/base/vwmul_vx-2.C: New test. * g++.target/riscv/rvv/base/vwmul_vx-3.C: New test. * g++.target/riscv/rvv/base/vwmul_vx_mu-1.C: New test. * g++.target/riscv/rvv/base/vwmul_vx_mu-2.C: New test. * g++.target/riscv/rvv/base/vwmul_vx_mu-3.C: New test. * g++.target/riscv/rvv/base/vwmul_vx_tu-1.C: New test. * g++.target/riscv/rvv/base/vwmul_vx_tu-2.C: New test. * g++.target/riscv/rvv/base/vwmul_vx_tu-3.C: New test. * g++.target/riscv/rvv/base/vwmul_vx_tum-1.C: New test. * g++.target/riscv/rvv/base/vwmul_vx_tum-2.C: New test. * g++.target/riscv/rvv/base/vwmul_vx_tum-3.C: New test. * g++.target/riscv/rvv/base/vwmul_vx_tumu-1.C: New test. * g++.target/riscv/rvv/base/vwmul_vx_tumu-2.C: New test. * g++.target/riscv/rvv/base/vwmul_vx_tumu-3.C: New test. --- .../g++.target/riscv/rvv/base/vwmul_vv-1.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwmul_vv-2.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwmul_vv-3.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwmul_vv_mu-1.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwmul_vv_mu-2.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwmul_vv_mu-3.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwmul_vv_tu-1.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwmul_vv_tu-2.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwmul_vv_tu-3.C | 111 +++++++++ .../riscv/rvv/base/vwmul_vv_tum-1.C | 111 +++++++++ .../riscv/rvv/base/vwmul_vv_tum-2.C | 111 +++++++++ .../riscv/rvv/base/vwmul_vv_tum-3.C | 111 +++++++++ .../riscv/rvv/base/vwmul_vv_tumu-1.C | 111 +++++++++ .../riscv/rvv/base/vwmul_vv_tumu-2.C | 111 +++++++++ .../riscv/rvv/base/vwmul_vv_tumu-3.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwmul_vx-1.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwmul_vx-2.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwmul_vx-3.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwmul_vx_mu-1.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwmul_vx_mu-2.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwmul_vx_mu-3.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwmul_vx_tu-1.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwmul_vx_tu-2.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwmul_vx_tu-3.C | 111 +++++++++ .../riscv/rvv/base/vwmul_vx_tum-1.C | 111 +++++++++ .../riscv/rvv/base/vwmul_vx_tum-2.C | 111 +++++++++ .../riscv/rvv/base/vwmul_vx_tum-3.C | 111 +++++++++ .../riscv/rvv/base/vwmul_vx_tumu-1.C | 111 +++++++++ .../riscv/rvv/base/vwmul_vx_tumu-2.C | 111 +++++++++ .../riscv/rvv/base/vwmul_vx_tumu-3.C | 111 +++++++++ 30 files changed, 3960 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tumu-3.C diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv-1.C new file mode 100644 index 00000000000..975cadd372d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv-1.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul(vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul(vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul(vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul(vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul(vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul(vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul(vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul(vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul(vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul(vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul(vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul(vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul(vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul(vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul(vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vwmul(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv-2.C new file mode 100644 index 00000000000..e93ca697389 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv-2.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul(vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul(vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul(vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul(vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul(vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul(vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul(vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul(vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul(vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul(vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul(vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul(vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul(vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul(vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul(vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint16mf4_t test___riscv_vwmul(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv-3.C new file mode 100644 index 00000000000..d55c1af6705 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv-3.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul(vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul(vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul(vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul(vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul(vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul(vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul(vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul(vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul(vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul(vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul(vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul(vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul(vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul(vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul(vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint16mf4_t test___riscv_vwmul(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_mu-1.C new file mode 100644 index 00000000000..a54a54101b0 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_mu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_mu-2.C new file mode 100644 index 00000000000..e9ad592caf2 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_mu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_mu-3.C new file mode 100644 index 00000000000..706ae97b6c8 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_mu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tu-1.C new file mode 100644 index 00000000000..e9483dce3d9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tu(vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul_tu(vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul_tu(vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul_tu(vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul_tu(vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul_tu(vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul_tu(vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul_tu(vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul_tu(vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul_tu(vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul_tu(vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul_tu(vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul_tu(vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul_tu(vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul_tu(vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tu-2.C new file mode 100644 index 00000000000..35f01024f54 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tu(vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul_tu(vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul_tu(vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul_tu(vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul_tu(vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul_tu(vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul_tu(vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul_tu(vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul_tu(vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul_tu(vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul_tu(vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul_tu(vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul_tu(vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul_tu(vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul_tu(vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tu-3.C new file mode 100644 index 00000000000..bc5b27b49cc --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tu(vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul_tu(vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul_tu(vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul_tu(vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul_tu(vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul_tu(vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul_tu(vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul_tu(vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul_tu(vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul_tu(vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul_tu(vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul_tu(vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul_tu(vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul_tu(vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul_tu(vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tum-1.C new file mode 100644 index 00000000000..105d91c2f28 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tum-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tum-2.C new file mode 100644 index 00000000000..c2cdde3452a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tum-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tum-3.C new file mode 100644 index 00000000000..b6945ecac94 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tum-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tumu-1.C new file mode 100644 index 00000000000..1c50f12371c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tumu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tumu-2.C new file mode 100644 index 00000000000..c8c96775946 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tumu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tumu-3.C new file mode 100644 index 00000000000..8919583b985 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vv_tumu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmul\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx-1.C new file mode 100644 index 00000000000..e4f10fad895 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx-1.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vwmul(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx-2.C new file mode 100644 index 00000000000..dc64a100b76 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx-2.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,31); +} + + +vint16mf4_t test___riscv_vwmul(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx-3.C new file mode 100644 index 00000000000..2978e23a01d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx-3.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(op1,op2,32); +} + + +vint16mf4_t test___riscv_vwmul(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_mu-1.C new file mode 100644 index 00000000000..42572b15f3e --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_mu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_mu-2.C new file mode 100644 index 00000000000..fe3caef57e8 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_mu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_mu-3.C new file mode 100644 index 00000000000..ac960f36237 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_mu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tu-1.C new file mode 100644 index 00000000000..72da245aa35 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tu(vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul_tu(vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul_tu(vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul_tu(vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul_tu(vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul_tu(vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul_tu(vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul_tu(vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul_tu(vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul_tu(vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul_tu(vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul_tu(vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul_tu(vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul_tu(vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul_tu(vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tu-2.C new file mode 100644 index 00000000000..a3dca75be39 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tu(vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul_tu(vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul_tu(vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul_tu(vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul_tu(vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul_tu(vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul_tu(vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul_tu(vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul_tu(vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul_tu(vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul_tu(vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul_tu(vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul_tu(vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul_tu(vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul_tu(vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tu-3.C new file mode 100644 index 00000000000..40748cd5273 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tu(vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul_tu(vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul_tu(vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul_tu(vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul_tu(vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul_tu(vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul_tu(vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul_tu(vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul_tu(vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul_tu(vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul_tu(vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul_tu(vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul_tu(vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul_tu(vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul_tu(vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tum-1.C new file mode 100644 index 00000000000..10ee63acc1c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tum-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tum-2.C new file mode 100644 index 00000000000..138b8228d86 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tum-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tum-3.C new file mode 100644 index 00000000000..137e9347999 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tum-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tumu-1.C new file mode 100644 index 00000000000..92ab4755f24 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tumu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmul_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmul_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmul_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmul_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmul_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmul_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmul_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmul_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmul_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmul_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmul_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmul_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmul_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmul_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tumu-2.C new file mode 100644 index 00000000000..30877b6e0ec --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tumu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmul_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmul_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmul_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmul_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmul_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmul_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmul_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmul_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmul_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmul_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmul_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmul_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmul_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmul_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tumu-3.C new file mode 100644 index 00000000000..d1efd5a34cd --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmul_vx_tumu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmul_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmul_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmul_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmul_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmul_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmul_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmul_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmul_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmul_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmul_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmul_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmul_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmul_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmul_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmul_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwmul_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmul\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */