From patchwork Tue Feb 7 06:43:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?6ZKf5bGF5ZOy?= X-Patchwork-Id: 64423 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9FEB13858C2F for ; Tue, 7 Feb 2023 06:43:41 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg153.qq.com (smtpbg153.qq.com [13.245.218.24]) by sourceware.org (Postfix) with ESMTPS id 468033858D1E for ; Tue, 7 Feb 2023 06:43:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 468033858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp80t1675752187tlg2lq89 Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 07 Feb 2023 14:43:06 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: +ujAKkuGAaVgXHATAJ35HMkD3/STPwrtxvFJYNHGGpshFMjkSgXTFkFGl67/6 Fycl7guyEHaxLUmsjGSoUQR2/W0RdaO/31SkWyNTNWDRAiPofZH5Xf5V8N6q7sLfdAtsprL KdevEGw/J1GmMEfQA46ZIhBoYh1sdBgMedX3aEeS2yVO85Tddv1Bekwgwghqgkg29cB6xy5 t3id04uMybLCoHvafpctrHtTfxfQEXMSAAE1esH6hfTRQyc7Ng+yChEnwutwEU9OZ8SLVGN MZnKaHauukI58Nccf8m+2FqNVJv65ShFH/TdgmOmpsMNv478e0RopMu9W8itjWtlKR0e7ZU CpcsUbH11s8hdFb1IpQJ9TbprUDXo9NVzbqu2IH0DFjJnfv1x+hYLkF9KEiHw== X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vwsub.w C++ api TESTS Date: Tue, 7 Feb 2023 14:43:05 +0800 Message-Id: <20230207064305.41749-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vwsub_wv-1.C: New test. * g++.target/riscv/rvv/base/vwsub_wv-2.C: New test. * g++.target/riscv/rvv/base/vwsub_wv-3.C: New test. * g++.target/riscv/rvv/base/vwsub_wv_mu-1.C: New test. * g++.target/riscv/rvv/base/vwsub_wv_mu-2.C: New test. * g++.target/riscv/rvv/base/vwsub_wv_mu-3.C: New test. * g++.target/riscv/rvv/base/vwsub_wv_tu-1.C: New test. * g++.target/riscv/rvv/base/vwsub_wv_tu-2.C: New test. * g++.target/riscv/rvv/base/vwsub_wv_tu-3.C: New test. * g++.target/riscv/rvv/base/vwsub_wv_tum-1.C: New test. * g++.target/riscv/rvv/base/vwsub_wv_tum-2.C: New test. * g++.target/riscv/rvv/base/vwsub_wv_tum-3.C: New test. * g++.target/riscv/rvv/base/vwsub_wv_tumu-1.C: New test. * g++.target/riscv/rvv/base/vwsub_wv_tumu-2.C: New test. * g++.target/riscv/rvv/base/vwsub_wv_tumu-3.C: New test. * g++.target/riscv/rvv/base/vwsub_wx-1.C: New test. * g++.target/riscv/rvv/base/vwsub_wx-2.C: New test. * g++.target/riscv/rvv/base/vwsub_wx-3.C: New test. * g++.target/riscv/rvv/base/vwsub_wx_mu-1.C: New test. * g++.target/riscv/rvv/base/vwsub_wx_mu-2.C: New test. * g++.target/riscv/rvv/base/vwsub_wx_mu-3.C: New test. * g++.target/riscv/rvv/base/vwsub_wx_tu-1.C: New test. * g++.target/riscv/rvv/base/vwsub_wx_tu-2.C: New test. * g++.target/riscv/rvv/base/vwsub_wx_tu-3.C: New test. * g++.target/riscv/rvv/base/vwsub_wx_tum-1.C: New test. * g++.target/riscv/rvv/base/vwsub_wx_tum-2.C: New test. * g++.target/riscv/rvv/base/vwsub_wx_tum-3.C: New test. * g++.target/riscv/rvv/base/vwsub_wx_tumu-1.C: New test. * g++.target/riscv/rvv/base/vwsub_wx_tumu-2.C: New test. * g++.target/riscv/rvv/base/vwsub_wx_tumu-3.C: New test. --- .../g++.target/riscv/rvv/base/vwsub_wv-1.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwsub_wv-2.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwsub_wv-3.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwsub_wv_mu-1.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwsub_wv_mu-2.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwsub_wv_mu-3.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwsub_wv_tu-1.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwsub_wv_tu-2.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwsub_wv_tu-3.C | 111 +++++++++ .../riscv/rvv/base/vwsub_wv_tum-1.C | 111 +++++++++ .../riscv/rvv/base/vwsub_wv_tum-2.C | 111 +++++++++ .../riscv/rvv/base/vwsub_wv_tum-3.C | 111 +++++++++ .../riscv/rvv/base/vwsub_wv_tumu-1.C | 111 +++++++++ .../riscv/rvv/base/vwsub_wv_tumu-2.C | 111 +++++++++ .../riscv/rvv/base/vwsub_wv_tumu-3.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwsub_wx-1.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwsub_wx-2.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwsub_wx-3.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwsub_wx_mu-1.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwsub_wx_mu-2.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwsub_wx_mu-3.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwsub_wx_tu-1.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwsub_wx_tu-2.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwsub_wx_tu-3.C | 111 +++++++++ .../riscv/rvv/base/vwsub_wx_tum-1.C | 111 +++++++++ .../riscv/rvv/base/vwsub_wx_tum-2.C | 111 +++++++++ .../riscv/rvv/base/vwsub_wx_tum-3.C | 111 +++++++++ .../riscv/rvv/base/vwsub_wx_tumu-1.C | 111 +++++++++ .../riscv/rvv/base/vwsub_wx_tumu-2.C | 111 +++++++++ .../riscv/rvv/base/vwsub_wx_tumu-3.C | 111 +++++++++ 30 files changed, 3960 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tumu-3.C diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv-1.C new file mode 100644 index 00000000000..73c3f53d8dc --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv-1.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwsub_wv(vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwsub_wv(vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,vl); +} + + +vint16m1_t test___riscv_vwsub_wv(vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,vl); +} + + +vint16m2_t test___riscv_vwsub_wv(vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,vl); +} + + +vint16m4_t test___riscv_vwsub_wv(vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,vl); +} + + +vint16m8_t test___riscv_vwsub_wv(vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwsub_wv(vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,vl); +} + + +vint32m1_t test___riscv_vwsub_wv(vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,vl); +} + + +vint32m2_t test___riscv_vwsub_wv(vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,vl); +} + + +vint32m4_t test___riscv_vwsub_wv(vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,vl); +} + + +vint32m8_t test___riscv_vwsub_wv(vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,vl); +} + + +vint64m1_t test___riscv_vwsub_wv(vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,vl); +} + + +vint64m2_t test___riscv_vwsub_wv(vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,vl); +} + + +vint64m4_t test___riscv_vwsub_wv(vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,vl); +} + + +vint64m8_t test___riscv_vwsub_wv(vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vwsub_wv(vbool64_t mask,vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwsub_wv(vbool32_t mask,vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwsub_wv(vbool16_t mask,vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwsub_wv(vbool8_t mask,vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwsub_wv(vbool4_t mask,vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwsub_wv(vbool2_t mask,vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwsub_wv(vbool64_t mask,vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwsub_wv(vbool32_t mask,vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwsub_wv(vbool16_t mask,vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwsub_wv(vbool8_t mask,vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwsub_wv(vbool4_t mask,vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwsub_wv(vbool64_t mask,vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwsub_wv(vbool32_t mask,vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwsub_wv(vbool16_t mask,vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwsub_wv(vbool8_t mask,vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv-2.C new file mode 100644 index 00000000000..1ef2c56fd27 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv-2.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwsub_wv(vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,31); +} + + +vint16mf2_t test___riscv_vwsub_wv(vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,31); +} + + +vint16m1_t test___riscv_vwsub_wv(vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,31); +} + + +vint16m2_t test___riscv_vwsub_wv(vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,31); +} + + +vint16m4_t test___riscv_vwsub_wv(vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,31); +} + + +vint16m8_t test___riscv_vwsub_wv(vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,31); +} + + +vint32mf2_t test___riscv_vwsub_wv(vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,31); +} + + +vint32m1_t test___riscv_vwsub_wv(vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,31); +} + + +vint32m2_t test___riscv_vwsub_wv(vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,31); +} + + +vint32m4_t test___riscv_vwsub_wv(vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,31); +} + + +vint32m8_t test___riscv_vwsub_wv(vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,31); +} + + +vint64m1_t test___riscv_vwsub_wv(vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,31); +} + + +vint64m2_t test___riscv_vwsub_wv(vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,31); +} + + +vint64m4_t test___riscv_vwsub_wv(vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,31); +} + + +vint64m8_t test___riscv_vwsub_wv(vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,31); +} + + +vint16mf4_t test___riscv_vwsub_wv(vbool64_t mask,vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwsub_wv(vbool32_t mask,vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vwsub_wv(vbool16_t mask,vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vwsub_wv(vbool8_t mask,vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vwsub_wv(vbool4_t mask,vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vwsub_wv(vbool2_t mask,vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwsub_wv(vbool64_t mask,vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vwsub_wv(vbool32_t mask,vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vwsub_wv(vbool16_t mask,vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vwsub_wv(vbool8_t mask,vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vwsub_wv(vbool4_t mask,vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vwsub_wv(vbool64_t mask,vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vwsub_wv(vbool32_t mask,vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vwsub_wv(vbool16_t mask,vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vwsub_wv(vbool8_t mask,vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv-3.C new file mode 100644 index 00000000000..3231000a07f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv-3.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwsub_wv(vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,32); +} + + +vint16mf2_t test___riscv_vwsub_wv(vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,32); +} + + +vint16m1_t test___riscv_vwsub_wv(vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,32); +} + + +vint16m2_t test___riscv_vwsub_wv(vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,32); +} + + +vint16m4_t test___riscv_vwsub_wv(vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,32); +} + + +vint16m8_t test___riscv_vwsub_wv(vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,32); +} + + +vint32mf2_t test___riscv_vwsub_wv(vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,32); +} + + +vint32m1_t test___riscv_vwsub_wv(vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,32); +} + + +vint32m2_t test___riscv_vwsub_wv(vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,32); +} + + +vint32m4_t test___riscv_vwsub_wv(vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,32); +} + + +vint32m8_t test___riscv_vwsub_wv(vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,32); +} + + +vint64m1_t test___riscv_vwsub_wv(vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,32); +} + + +vint64m2_t test___riscv_vwsub_wv(vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,32); +} + + +vint64m4_t test___riscv_vwsub_wv(vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,32); +} + + +vint64m8_t test___riscv_vwsub_wv(vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv(op1,op2,32); +} + + +vint16mf4_t test___riscv_vwsub_wv(vbool64_t mask,vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwsub_wv(vbool32_t mask,vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vwsub_wv(vbool16_t mask,vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vwsub_wv(vbool8_t mask,vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vwsub_wv(vbool4_t mask,vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vwsub_wv(vbool2_t mask,vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwsub_wv(vbool64_t mask,vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vwsub_wv(vbool32_t mask,vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vwsub_wv(vbool16_t mask,vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vwsub_wv(vbool8_t mask,vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vwsub_wv(vbool4_t mask,vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vwsub_wv(vbool64_t mask,vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vwsub_wv(vbool32_t mask,vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vwsub_wv(vbool16_t mask,vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vwsub_wv(vbool8_t mask,vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_mu-1.C new file mode 100644 index 00000000000..d637d17eb07 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_mu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwsub_wv_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwsub_wv_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwsub_wv_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwsub_wv_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwsub_wv_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwsub_wv_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwsub_wv_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwsub_wv_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwsub_wv_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwsub_wv_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwsub_wv_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwsub_wv_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwsub_wv_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwsub_wv_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwsub_wv_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_mu-2.C new file mode 100644 index 00000000000..ef94215b6db --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_mu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwsub_wv_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwsub_wv_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwsub_wv_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwsub_wv_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwsub_wv_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwsub_wv_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwsub_wv_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwsub_wv_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwsub_wv_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwsub_wv_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwsub_wv_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwsub_wv_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwsub_wv_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwsub_wv_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwsub_wv_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_mu-3.C new file mode 100644 index 00000000000..1c6f91edab7 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_mu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwsub_wv_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwsub_wv_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwsub_wv_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwsub_wv_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwsub_wv_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwsub_wv_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwsub_wv_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwsub_wv_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwsub_wv_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwsub_wv_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwsub_wv_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwsub_wv_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwsub_wv_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwsub_wv_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwsub_wv_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tu-1.C new file mode 100644 index 00000000000..d77477e129a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwsub_wv_tu(vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwsub_wv_tu(vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwsub_wv_tu(vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwsub_wv_tu(vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwsub_wv_tu(vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwsub_wv_tu(vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwsub_wv_tu(vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwsub_wv_tu(vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwsub_wv_tu(vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwsub_wv_tu(vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwsub_wv_tu(vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwsub_wv_tu(vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwsub_wv_tu(vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwsub_wv_tu(vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwsub_wv_tu(vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tu-2.C new file mode 100644 index 00000000000..80fe4106ae5 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwsub_wv_tu(vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwsub_wv_tu(vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwsub_wv_tu(vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwsub_wv_tu(vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwsub_wv_tu(vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwsub_wv_tu(vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwsub_wv_tu(vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwsub_wv_tu(vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwsub_wv_tu(vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwsub_wv_tu(vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwsub_wv_tu(vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwsub_wv_tu(vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwsub_wv_tu(vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwsub_wv_tu(vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwsub_wv_tu(vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tu-3.C new file mode 100644 index 00000000000..d557f91de59 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwsub_wv_tu(vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwsub_wv_tu(vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwsub_wv_tu(vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwsub_wv_tu(vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwsub_wv_tu(vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwsub_wv_tu(vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwsub_wv_tu(vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwsub_wv_tu(vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwsub_wv_tu(vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwsub_wv_tu(vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwsub_wv_tu(vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwsub_wv_tu(vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwsub_wv_tu(vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwsub_wv_tu(vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwsub_wv_tu(vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tum-1.C new file mode 100644 index 00000000000..74591889ac2 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tum-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwsub_wv_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwsub_wv_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwsub_wv_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwsub_wv_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwsub_wv_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwsub_wv_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwsub_wv_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwsub_wv_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwsub_wv_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwsub_wv_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwsub_wv_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwsub_wv_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwsub_wv_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwsub_wv_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwsub_wv_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tum-2.C new file mode 100644 index 00000000000..e3e9340a6aa --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tum-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwsub_wv_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwsub_wv_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwsub_wv_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwsub_wv_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwsub_wv_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwsub_wv_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwsub_wv_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwsub_wv_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwsub_wv_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwsub_wv_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwsub_wv_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwsub_wv_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwsub_wv_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwsub_wv_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwsub_wv_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tum-3.C new file mode 100644 index 00000000000..41f134f14e5 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tum-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwsub_wv_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwsub_wv_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwsub_wv_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwsub_wv_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwsub_wv_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwsub_wv_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwsub_wv_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwsub_wv_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwsub_wv_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwsub_wv_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwsub_wv_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwsub_wv_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwsub_wv_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwsub_wv_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwsub_wv_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tumu-1.C new file mode 100644 index 00000000000..aee6c23342e --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tumu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwsub_wv_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwsub_wv_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwsub_wv_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwsub_wv_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwsub_wv_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwsub_wv_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwsub_wv_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwsub_wv_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwsub_wv_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwsub_wv_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwsub_wv_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwsub_wv_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwsub_wv_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwsub_wv_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwsub_wv_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tumu-2.C new file mode 100644 index 00000000000..c9e833a65a4 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tumu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwsub_wv_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwsub_wv_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwsub_wv_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwsub_wv_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwsub_wv_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwsub_wv_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwsub_wv_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwsub_wv_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwsub_wv_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwsub_wv_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwsub_wv_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwsub_wv_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwsub_wv_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwsub_wv_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwsub_wv_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tumu-3.C new file mode 100644 index 00000000000..02d72987c3b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wv_tumu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwsub_wv_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwsub_wv_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwsub_wv_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwsub_wv_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwsub_wv_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwsub_wv_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwsub_wv_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwsub_wv_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwsub_wv_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwsub_wv_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwsub_wv_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwsub_wv_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwsub_wv_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwsub_wv_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwsub_wv_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwsub_wv_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsub\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx-1.C new file mode 100644 index 00000000000..2a09333658e --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx-1.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwsub_wx(vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,vl); +} + + +vint16mf2_t test___riscv_vwsub_wx(vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,vl); +} + + +vint16m1_t test___riscv_vwsub_wx(vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,vl); +} + + +vint16m2_t test___riscv_vwsub_wx(vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,vl); +} + + +vint16m4_t test___riscv_vwsub_wx(vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,vl); +} + + +vint16m8_t test___riscv_vwsub_wx(vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,vl); +} + + +vint32mf2_t test___riscv_vwsub_wx(vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,vl); +} + + +vint32m1_t test___riscv_vwsub_wx(vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,vl); +} + + +vint32m2_t test___riscv_vwsub_wx(vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,vl); +} + + +vint32m4_t test___riscv_vwsub_wx(vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,vl); +} + + +vint32m8_t test___riscv_vwsub_wx(vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,vl); +} + + +vint64m1_t test___riscv_vwsub_wx(vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,vl); +} + + +vint64m2_t test___riscv_vwsub_wx(vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,vl); +} + + +vint64m4_t test___riscv_vwsub_wx(vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,vl); +} + + +vint64m8_t test___riscv_vwsub_wx(vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,vl); +} + + +vint16mf4_t test___riscv_vwsub_wx(vbool64_t mask,vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,vl); +} + + +vint16mf2_t test___riscv_vwsub_wx(vbool32_t mask,vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,vl); +} + + +vint16m1_t test___riscv_vwsub_wx(vbool16_t mask,vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,vl); +} + + +vint16m2_t test___riscv_vwsub_wx(vbool8_t mask,vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,vl); +} + + +vint16m4_t test___riscv_vwsub_wx(vbool4_t mask,vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,vl); +} + + +vint16m8_t test___riscv_vwsub_wx(vbool2_t mask,vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,vl); +} + + +vint32mf2_t test___riscv_vwsub_wx(vbool64_t mask,vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,vl); +} + + +vint32m1_t test___riscv_vwsub_wx(vbool32_t mask,vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,vl); +} + + +vint32m2_t test___riscv_vwsub_wx(vbool16_t mask,vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,vl); +} + + +vint32m4_t test___riscv_vwsub_wx(vbool8_t mask,vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,vl); +} + + +vint32m8_t test___riscv_vwsub_wx(vbool4_t mask,vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,vl); +} + + +vint64m1_t test___riscv_vwsub_wx(vbool64_t mask,vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,vl); +} + + +vint64m2_t test___riscv_vwsub_wx(vbool32_t mask,vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,vl); +} + + +vint64m4_t test___riscv_vwsub_wx(vbool16_t mask,vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,vl); +} + + +vint64m8_t test___riscv_vwsub_wx(vbool8_t mask,vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx-2.C new file mode 100644 index 00000000000..d223690df53 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx-2.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwsub_wx(vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,31); +} + + +vint16mf2_t test___riscv_vwsub_wx(vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,31); +} + + +vint16m1_t test___riscv_vwsub_wx(vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,31); +} + + +vint16m2_t test___riscv_vwsub_wx(vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,31); +} + + +vint16m4_t test___riscv_vwsub_wx(vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,31); +} + + +vint16m8_t test___riscv_vwsub_wx(vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,31); +} + + +vint32mf2_t test___riscv_vwsub_wx(vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,31); +} + + +vint32m1_t test___riscv_vwsub_wx(vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,31); +} + + +vint32m2_t test___riscv_vwsub_wx(vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,31); +} + + +vint32m4_t test___riscv_vwsub_wx(vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,31); +} + + +vint32m8_t test___riscv_vwsub_wx(vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,31); +} + + +vint64m1_t test___riscv_vwsub_wx(vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,31); +} + + +vint64m2_t test___riscv_vwsub_wx(vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,31); +} + + +vint64m4_t test___riscv_vwsub_wx(vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,31); +} + + +vint64m8_t test___riscv_vwsub_wx(vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,31); +} + + +vint16mf4_t test___riscv_vwsub_wx(vbool64_t mask,vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,31); +} + + +vint16mf2_t test___riscv_vwsub_wx(vbool32_t mask,vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,31); +} + + +vint16m1_t test___riscv_vwsub_wx(vbool16_t mask,vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,31); +} + + +vint16m2_t test___riscv_vwsub_wx(vbool8_t mask,vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,31); +} + + +vint16m4_t test___riscv_vwsub_wx(vbool4_t mask,vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,31); +} + + +vint16m8_t test___riscv_vwsub_wx(vbool2_t mask,vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,31); +} + + +vint32mf2_t test___riscv_vwsub_wx(vbool64_t mask,vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,31); +} + + +vint32m1_t test___riscv_vwsub_wx(vbool32_t mask,vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,31); +} + + +vint32m2_t test___riscv_vwsub_wx(vbool16_t mask,vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,31); +} + + +vint32m4_t test___riscv_vwsub_wx(vbool8_t mask,vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,31); +} + + +vint32m8_t test___riscv_vwsub_wx(vbool4_t mask,vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,31); +} + + +vint64m1_t test___riscv_vwsub_wx(vbool64_t mask,vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,31); +} + + +vint64m2_t test___riscv_vwsub_wx(vbool32_t mask,vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,31); +} + + +vint64m4_t test___riscv_vwsub_wx(vbool16_t mask,vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,31); +} + + +vint64m8_t test___riscv_vwsub_wx(vbool8_t mask,vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx-3.C new file mode 100644 index 00000000000..45279a394a8 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx-3.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwsub_wx(vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,32); +} + + +vint16mf2_t test___riscv_vwsub_wx(vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,32); +} + + +vint16m1_t test___riscv_vwsub_wx(vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,32); +} + + +vint16m2_t test___riscv_vwsub_wx(vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,32); +} + + +vint16m4_t test___riscv_vwsub_wx(vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,32); +} + + +vint16m8_t test___riscv_vwsub_wx(vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,32); +} + + +vint32mf2_t test___riscv_vwsub_wx(vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,32); +} + + +vint32m1_t test___riscv_vwsub_wx(vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,32); +} + + +vint32m2_t test___riscv_vwsub_wx(vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,32); +} + + +vint32m4_t test___riscv_vwsub_wx(vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,32); +} + + +vint32m8_t test___riscv_vwsub_wx(vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,32); +} + + +vint64m1_t test___riscv_vwsub_wx(vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,32); +} + + +vint64m2_t test___riscv_vwsub_wx(vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,32); +} + + +vint64m4_t test___riscv_vwsub_wx(vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,32); +} + + +vint64m8_t test___riscv_vwsub_wx(vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx(op1,0xAA,32); +} + + +vint16mf4_t test___riscv_vwsub_wx(vbool64_t mask,vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,32); +} + + +vint16mf2_t test___riscv_vwsub_wx(vbool32_t mask,vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,32); +} + + +vint16m1_t test___riscv_vwsub_wx(vbool16_t mask,vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,32); +} + + +vint16m2_t test___riscv_vwsub_wx(vbool8_t mask,vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,32); +} + + +vint16m4_t test___riscv_vwsub_wx(vbool4_t mask,vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,32); +} + + +vint16m8_t test___riscv_vwsub_wx(vbool2_t mask,vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,32); +} + + +vint32mf2_t test___riscv_vwsub_wx(vbool64_t mask,vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,32); +} + + +vint32m1_t test___riscv_vwsub_wx(vbool32_t mask,vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,32); +} + + +vint32m2_t test___riscv_vwsub_wx(vbool16_t mask,vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,32); +} + + +vint32m4_t test___riscv_vwsub_wx(vbool8_t mask,vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,32); +} + + +vint32m8_t test___riscv_vwsub_wx(vbool4_t mask,vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,32); +} + + +vint64m1_t test___riscv_vwsub_wx(vbool64_t mask,vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,32); +} + + +vint64m2_t test___riscv_vwsub_wx(vbool32_t mask,vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,32); +} + + +vint64m4_t test___riscv_vwsub_wx(vbool16_t mask,vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,32); +} + + +vint64m8_t test___riscv_vwsub_wx(vbool8_t mask,vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx(mask,op1,0xAA,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_mu-1.C new file mode 100644 index 00000000000..39fd99e18ad --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_mu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwsub_wx_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vint16mf2_t test___riscv_vwsub_wx_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vint16m1_t test___riscv_vwsub_wx_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vint16m2_t test___riscv_vwsub_wx_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vint16m4_t test___riscv_vwsub_wx_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vint16m8_t test___riscv_vwsub_wx_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vint32mf2_t test___riscv_vwsub_wx_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vint32m1_t test___riscv_vwsub_wx_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vint32m2_t test___riscv_vwsub_wx_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vint32m4_t test___riscv_vwsub_wx_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vint32m8_t test___riscv_vwsub_wx_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vint64m1_t test___riscv_vwsub_wx_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vint64m2_t test___riscv_vwsub_wx_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vint64m4_t test___riscv_vwsub_wx_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vint64m8_t test___riscv_vwsub_wx_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_mu-2.C new file mode 100644 index 00000000000..d8e26c0f7d7 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_mu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwsub_wx_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,31); +} + + +vint16mf2_t test___riscv_vwsub_wx_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,31); +} + + +vint16m1_t test___riscv_vwsub_wx_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,31); +} + + +vint16m2_t test___riscv_vwsub_wx_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,31); +} + + +vint16m4_t test___riscv_vwsub_wx_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,31); +} + + +vint16m8_t test___riscv_vwsub_wx_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,31); +} + + +vint32mf2_t test___riscv_vwsub_wx_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,31); +} + + +vint32m1_t test___riscv_vwsub_wx_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,31); +} + + +vint32m2_t test___riscv_vwsub_wx_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,31); +} + + +vint32m4_t test___riscv_vwsub_wx_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,31); +} + + +vint32m8_t test___riscv_vwsub_wx_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,31); +} + + +vint64m1_t test___riscv_vwsub_wx_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,31); +} + + +vint64m2_t test___riscv_vwsub_wx_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,31); +} + + +vint64m4_t test___riscv_vwsub_wx_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,31); +} + + +vint64m8_t test___riscv_vwsub_wx_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_mu-3.C new file mode 100644 index 00000000000..0e361d52e62 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_mu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwsub_wx_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,32); +} + + +vint16mf2_t test___riscv_vwsub_wx_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,32); +} + + +vint16m1_t test___riscv_vwsub_wx_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,32); +} + + +vint16m2_t test___riscv_vwsub_wx_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,32); +} + + +vint16m4_t test___riscv_vwsub_wx_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,32); +} + + +vint16m8_t test___riscv_vwsub_wx_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,32); +} + + +vint32mf2_t test___riscv_vwsub_wx_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,32); +} + + +vint32m1_t test___riscv_vwsub_wx_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,32); +} + + +vint32m2_t test___riscv_vwsub_wx_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,32); +} + + +vint32m4_t test___riscv_vwsub_wx_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,32); +} + + +vint32m8_t test___riscv_vwsub_wx_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,32); +} + + +vint64m1_t test___riscv_vwsub_wx_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,32); +} + + +vint64m2_t test___riscv_vwsub_wx_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,32); +} + + +vint64m4_t test___riscv_vwsub_wx_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,32); +} + + +vint64m8_t test___riscv_vwsub_wx_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_mu(mask,merge,op1,0xAA,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tu-1.C new file mode 100644 index 00000000000..a253bb6dbd2 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwsub_wx_tu(vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,vl); +} + + +vint16mf2_t test___riscv_vwsub_wx_tu(vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,vl); +} + + +vint16m1_t test___riscv_vwsub_wx_tu(vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,vl); +} + + +vint16m2_t test___riscv_vwsub_wx_tu(vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,vl); +} + + +vint16m4_t test___riscv_vwsub_wx_tu(vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,vl); +} + + +vint16m8_t test___riscv_vwsub_wx_tu(vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,vl); +} + + +vint32mf2_t test___riscv_vwsub_wx_tu(vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,vl); +} + + +vint32m1_t test___riscv_vwsub_wx_tu(vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,vl); +} + + +vint32m2_t test___riscv_vwsub_wx_tu(vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,vl); +} + + +vint32m4_t test___riscv_vwsub_wx_tu(vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,vl); +} + + +vint32m8_t test___riscv_vwsub_wx_tu(vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,vl); +} + + +vint64m1_t test___riscv_vwsub_wx_tu(vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,vl); +} + + +vint64m2_t test___riscv_vwsub_wx_tu(vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,vl); +} + + +vint64m4_t test___riscv_vwsub_wx_tu(vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,vl); +} + + +vint64m8_t test___riscv_vwsub_wx_tu(vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tu-2.C new file mode 100644 index 00000000000..1eb145ea4ef --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwsub_wx_tu(vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,31); +} + + +vint16mf2_t test___riscv_vwsub_wx_tu(vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,31); +} + + +vint16m1_t test___riscv_vwsub_wx_tu(vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,31); +} + + +vint16m2_t test___riscv_vwsub_wx_tu(vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,31); +} + + +vint16m4_t test___riscv_vwsub_wx_tu(vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,31); +} + + +vint16m8_t test___riscv_vwsub_wx_tu(vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,31); +} + + +vint32mf2_t test___riscv_vwsub_wx_tu(vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,31); +} + + +vint32m1_t test___riscv_vwsub_wx_tu(vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,31); +} + + +vint32m2_t test___riscv_vwsub_wx_tu(vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,31); +} + + +vint32m4_t test___riscv_vwsub_wx_tu(vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,31); +} + + +vint32m8_t test___riscv_vwsub_wx_tu(vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,31); +} + + +vint64m1_t test___riscv_vwsub_wx_tu(vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,31); +} + + +vint64m2_t test___riscv_vwsub_wx_tu(vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,31); +} + + +vint64m4_t test___riscv_vwsub_wx_tu(vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,31); +} + + +vint64m8_t test___riscv_vwsub_wx_tu(vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tu-3.C new file mode 100644 index 00000000000..56b2f3677a7 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwsub_wx_tu(vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,32); +} + + +vint16mf2_t test___riscv_vwsub_wx_tu(vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,32); +} + + +vint16m1_t test___riscv_vwsub_wx_tu(vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,32); +} + + +vint16m2_t test___riscv_vwsub_wx_tu(vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,32); +} + + +vint16m4_t test___riscv_vwsub_wx_tu(vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,32); +} + + +vint16m8_t test___riscv_vwsub_wx_tu(vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,32); +} + + +vint32mf2_t test___riscv_vwsub_wx_tu(vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,32); +} + + +vint32m1_t test___riscv_vwsub_wx_tu(vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,32); +} + + +vint32m2_t test___riscv_vwsub_wx_tu(vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,32); +} + + +vint32m4_t test___riscv_vwsub_wx_tu(vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,32); +} + + +vint32m8_t test___riscv_vwsub_wx_tu(vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,32); +} + + +vint64m1_t test___riscv_vwsub_wx_tu(vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,32); +} + + +vint64m2_t test___riscv_vwsub_wx_tu(vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,32); +} + + +vint64m4_t test___riscv_vwsub_wx_tu(vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,32); +} + + +vint64m8_t test___riscv_vwsub_wx_tu(vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tu(merge,op1,0xAA,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tum-1.C new file mode 100644 index 00000000000..6d403facaf8 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tum-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwsub_wx_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vint16mf2_t test___riscv_vwsub_wx_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vint16m1_t test___riscv_vwsub_wx_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vint16m2_t test___riscv_vwsub_wx_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vint16m4_t test___riscv_vwsub_wx_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vint16m8_t test___riscv_vwsub_wx_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vint32mf2_t test___riscv_vwsub_wx_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vint32m1_t test___riscv_vwsub_wx_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vint32m2_t test___riscv_vwsub_wx_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vint32m4_t test___riscv_vwsub_wx_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vint32m8_t test___riscv_vwsub_wx_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vint64m1_t test___riscv_vwsub_wx_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vint64m2_t test___riscv_vwsub_wx_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vint64m4_t test___riscv_vwsub_wx_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vint64m8_t test___riscv_vwsub_wx_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tum-2.C new file mode 100644 index 00000000000..4f39d244f45 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tum-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwsub_wx_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,31); +} + + +vint16mf2_t test___riscv_vwsub_wx_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,31); +} + + +vint16m1_t test___riscv_vwsub_wx_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,31); +} + + +vint16m2_t test___riscv_vwsub_wx_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,31); +} + + +vint16m4_t test___riscv_vwsub_wx_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,31); +} + + +vint16m8_t test___riscv_vwsub_wx_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,31); +} + + +vint32mf2_t test___riscv_vwsub_wx_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,31); +} + + +vint32m1_t test___riscv_vwsub_wx_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,31); +} + + +vint32m2_t test___riscv_vwsub_wx_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,31); +} + + +vint32m4_t test___riscv_vwsub_wx_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,31); +} + + +vint32m8_t test___riscv_vwsub_wx_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,31); +} + + +vint64m1_t test___riscv_vwsub_wx_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,31); +} + + +vint64m2_t test___riscv_vwsub_wx_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,31); +} + + +vint64m4_t test___riscv_vwsub_wx_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,31); +} + + +vint64m8_t test___riscv_vwsub_wx_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tum-3.C new file mode 100644 index 00000000000..d8df066beb7 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tum-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwsub_wx_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,32); +} + + +vint16mf2_t test___riscv_vwsub_wx_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,32); +} + + +vint16m1_t test___riscv_vwsub_wx_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,32); +} + + +vint16m2_t test___riscv_vwsub_wx_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,32); +} + + +vint16m4_t test___riscv_vwsub_wx_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,32); +} + + +vint16m8_t test___riscv_vwsub_wx_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,32); +} + + +vint32mf2_t test___riscv_vwsub_wx_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,32); +} + + +vint32m1_t test___riscv_vwsub_wx_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,32); +} + + +vint32m2_t test___riscv_vwsub_wx_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,32); +} + + +vint32m4_t test___riscv_vwsub_wx_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,32); +} + + +vint32m8_t test___riscv_vwsub_wx_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,32); +} + + +vint64m1_t test___riscv_vwsub_wx_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,32); +} + + +vint64m2_t test___riscv_vwsub_wx_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,32); +} + + +vint64m4_t test___riscv_vwsub_wx_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,32); +} + + +vint64m8_t test___riscv_vwsub_wx_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tum(mask,merge,op1,0xAA,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tumu-1.C new file mode 100644 index 00000000000..d08185bdc1d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tumu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwsub_wx_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vint16mf2_t test___riscv_vwsub_wx_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vint16m1_t test___riscv_vwsub_wx_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vint16m2_t test___riscv_vwsub_wx_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vint16m4_t test___riscv_vwsub_wx_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vint16m8_t test___riscv_vwsub_wx_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vint32mf2_t test___riscv_vwsub_wx_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vint32m1_t test___riscv_vwsub_wx_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vint32m2_t test___riscv_vwsub_wx_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vint32m4_t test___riscv_vwsub_wx_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vint32m8_t test___riscv_vwsub_wx_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vint64m1_t test___riscv_vwsub_wx_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vint64m2_t test___riscv_vwsub_wx_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vint64m4_t test___riscv_vwsub_wx_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vint64m8_t test___riscv_vwsub_wx_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tumu-2.C new file mode 100644 index 00000000000..01ab6335071 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tumu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwsub_wx_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vint16mf2_t test___riscv_vwsub_wx_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vint16m1_t test___riscv_vwsub_wx_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vint16m2_t test___riscv_vwsub_wx_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vint16m4_t test___riscv_vwsub_wx_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vint16m8_t test___riscv_vwsub_wx_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vint32mf2_t test___riscv_vwsub_wx_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vint32m1_t test___riscv_vwsub_wx_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vint32m2_t test___riscv_vwsub_wx_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vint32m4_t test___riscv_vwsub_wx_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vint32m8_t test___riscv_vwsub_wx_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vint64m1_t test___riscv_vwsub_wx_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vint64m2_t test___riscv_vwsub_wx_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vint64m4_t test___riscv_vwsub_wx_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vint64m8_t test___riscv_vwsub_wx_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tumu-3.C new file mode 100644 index 00000000000..9a58c760b64 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsub_wx_tumu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwsub_wx_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vint16mf2_t test___riscv_vwsub_wx_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vint16m1_t test___riscv_vwsub_wx_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vint16m2_t test___riscv_vwsub_wx_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vint16m4_t test___riscv_vwsub_wx_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vint16m8_t test___riscv_vwsub_wx_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vint32mf2_t test___riscv_vwsub_wx_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vint32m1_t test___riscv_vwsub_wx_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vint32m2_t test___riscv_vwsub_wx_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vint32m4_t test___riscv_vwsub_wx_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vint32m8_t test___riscv_vwsub_wx_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vint64m1_t test___riscv_vwsub_wx_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vint64m2_t test___riscv_vwsub_wx_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vint64m4_t test___riscv_vwsub_wx_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vint64m8_t test___riscv_vwsub_wx_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwsub_wx_tumu(mask,merge,op1,0xAA,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsub\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */