From patchwork Tue Feb 7 06:41:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 64422 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D96B73858022 for ; Tue, 7 Feb 2023 06:42:20 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgeu2.qq.com (smtpbgeu2.qq.com [18.194.254.142]) by sourceware.org (Postfix) with ESMTPS id 17A323858D1E for ; Tue, 7 Feb 2023 06:41:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 17A323858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp64t1675752107t162axdh Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 07 Feb 2023 14:41:46 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: FoXWTrug123N8nPfPjMgDMaG1fmcXBY01jhItLLBn/qqFIcEAqLnuEGAkKY4A 2gdrZdG0YVQCfvpwfr3WBhmY0kT28P31btr9ZVX9ePEAiunPkwzj5+oQ0Qnd6cw4lwC+LoZ la05XK4l/jk525L3EF274erY+KRdnVjgy2oO2rVLvraNkkZGiqbqupHGWb7O0Oceqtesct3 EmRxmGdJ5Bup+JRvA5zib9G3t57xyqvMQNWIZPugwUP07OCTV/e/JLk3MS/duVi9GuY0VBr O4OSa2gyDRaP6J7H3nU8Du7MQQuYyb0f6/Hc1b/sn0y08/f8+eOWmQVPdRQgGYvloH/r9Yv il6grcNR04WBO80j718OCFF01rkjUYqLb8ugU5kiyuD4NpWTOk3BdROOjyrTi/bALgnlODu X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vwsubu.v C++ API test Date: Tue, 7 Feb 2023 14:41:45 +0800 Message-Id: <20230207064145.41499-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_PASS, TXREP, T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vwsubu_vv-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_vv-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_vv-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_vv_mu-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_vv_mu-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_vv_mu-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_vv_tu-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_vv_tu-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_vv_tu-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_vv_tum-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_vv_tum-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_vv_tum-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_vv_tumu-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_vv_tumu-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_vv_tumu-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_vx-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_vx-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_vx-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_vx_mu-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_vx_mu-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_vx_mu-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_vx_tu-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_vx_tu-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_vx_tu-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_vx_tum-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_vx_tum-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_vx_tum-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_vx_tumu-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_vx_tumu-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_vx_tumu-3.C: New test. --- .../g++.target/riscv/rvv/base/vwsubu_vv-1.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwsubu_vv-2.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwsubu_vv-3.C | 216 ++++++++++++++++++ .../riscv/rvv/base/vwsubu_vv_mu-1.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vv_mu-2.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vv_mu-3.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vv_tu-1.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vv_tu-2.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vv_tu-3.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vv_tum-1.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vv_tum-2.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vv_tum-3.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vv_tumu-1.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vv_tumu-2.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vv_tumu-3.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwsubu_vx-1.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwsubu_vx-2.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwsubu_vx-3.C | 216 ++++++++++++++++++ .../riscv/rvv/base/vwsubu_vx_mu-1.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vx_mu-2.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vx_mu-3.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vx_tu-1.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vx_tu-2.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vx_tu-3.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vx_tum-1.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vx_tum-2.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vx_tum-3.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vx_tumu-1.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vx_tumu-2.C | 111 +++++++++ .../riscv/rvv/base/vwsubu_vx_tumu-3.C | 111 +++++++++ 30 files changed, 3960 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tumu-3.C diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv-1.C new file mode 100644 index 00000000000..4db7f81caee --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv-1.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vv(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_vv(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_vv(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_vv(vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_vv(vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_vv(vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_vv(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_vv(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_vv(vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_vv(vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_vv(vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_vv(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_vv(vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_vv(vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_vv(vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vwsubu_vv(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_vv(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_vv(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_vv(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_vv(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_vv(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_vv(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_vv(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_vv(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_vv(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_vv(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_vv(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_vv(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_vv(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_vv(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv-2.C new file mode 100644 index 00000000000..0567509af84 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv-2.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vv(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_vv(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_vv(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_vv(vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_vv(vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_vv(vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_vv(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_vv(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_vv(vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_vv(vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_vv(vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_vv(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_vv(vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_vv(vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_vv(vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,31); +} + + +vuint16mf4_t test___riscv_vwsubu_vv(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_vv(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_vv(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_vv(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_vv(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_vv(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_vv(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_vv(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_vv(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_vv(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_vv(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_vv(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_vv(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_vv(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_vv(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv-3.C new file mode 100644 index 00000000000..a2474055ec9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv-3.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vv(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_vv(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_vv(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_vv(vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_vv(vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_vv(vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_vv(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_vv(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_vv(vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_vv(vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_vv(vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_vv(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_vv(vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_vv(vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_vv(vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(op1,op2,32); +} + + +vuint16mf4_t test___riscv_vwsubu_vv(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_vv(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_vv(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_vv(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_vv(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_vv(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_vv(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_vv(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_vv(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_vv(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_vv(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_vv(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_vv(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_vv(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_vv(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_mu-1.C new file mode 100644 index 00000000000..88d7d19d5e6 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_mu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vv_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_vv_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_vv_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_vv_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_vv_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_vv_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_vv_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_vv_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_vv_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_vv_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_vv_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_vv_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_vv_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_vv_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_vv_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_mu-2.C new file mode 100644 index 00000000000..7cd12165fe0 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_mu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vv_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_vv_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_vv_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_vv_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_vv_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_vv_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_vv_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_vv_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_vv_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_vv_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_vv_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_vv_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_vv_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_vv_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_vv_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_mu-3.C new file mode 100644 index 00000000000..df9b83e0f31 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_mu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vv_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_vv_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_vv_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_vv_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_vv_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_vv_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_vv_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_vv_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_vv_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_vv_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_vv_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_vv_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_vv_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_vv_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_vv_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tu-1.C new file mode 100644 index 00000000000..c3aaa4bced6 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vv_tu(vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_vv_tu(vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_vv_tu(vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_vv_tu(vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_vv_tu(vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_vv_tu(vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_vv_tu(vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_vv_tu(vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_vv_tu(vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_vv_tu(vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_vv_tu(vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_vv_tu(vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_vv_tu(vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_vv_tu(vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_vv_tu(vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tu-2.C new file mode 100644 index 00000000000..b643e35c5bf --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vv_tu(vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_vv_tu(vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_vv_tu(vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_vv_tu(vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_vv_tu(vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_vv_tu(vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_vv_tu(vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_vv_tu(vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_vv_tu(vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_vv_tu(vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_vv_tu(vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_vv_tu(vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_vv_tu(vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_vv_tu(vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_vv_tu(vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tu-3.C new file mode 100644 index 00000000000..96a9d638369 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vv_tu(vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_vv_tu(vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_vv_tu(vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_vv_tu(vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_vv_tu(vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_vv_tu(vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_vv_tu(vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_vv_tu(vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_vv_tu(vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_vv_tu(vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_vv_tu(vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_vv_tu(vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_vv_tu(vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_vv_tu(vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_vv_tu(vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tum-1.C new file mode 100644 index 00000000000..139cf2f50a1 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tum-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vv_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_vv_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_vv_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_vv_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_vv_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_vv_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_vv_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_vv_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_vv_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_vv_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_vv_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_vv_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_vv_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_vv_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_vv_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tum-2.C new file mode 100644 index 00000000000..cfbc96ef38e --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tum-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vv_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_vv_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_vv_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_vv_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_vv_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_vv_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_vv_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_vv_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_vv_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_vv_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_vv_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_vv_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_vv_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_vv_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_vv_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tum-3.C new file mode 100644 index 00000000000..79f36d8c0f5 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tum-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vv_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_vv_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_vv_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_vv_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_vv_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_vv_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_vv_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_vv_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_vv_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_vv_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_vv_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_vv_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_vv_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_vv_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_vv_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tumu-1.C new file mode 100644 index 00000000000..b71a6e83608 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tumu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vv_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_vv_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_vv_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_vv_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_vv_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_vv_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_vv_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_vv_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_vv_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_vv_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_vv_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_vv_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_vv_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_vv_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_vv_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tumu-2.C new file mode 100644 index 00000000000..b3078fc640d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tumu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vv_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_vv_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_vv_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_vv_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_vv_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_vv_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_vv_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_vv_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_vv_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_vv_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_vv_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_vv_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_vv_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_vv_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_vv_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tumu-3.C new file mode 100644 index 00000000000..f8af559aed9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vv_tumu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vv_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_vv_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_vv_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_vv_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_vv_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_vv_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_vv_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_vv_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_vv_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_vv_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_vv_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_vv_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_vv_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_vv_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_vv_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwsubu_vv_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx-1.C new file mode 100644 index 00000000000..1b8dcca2864 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx-1.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vx(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_vx(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_vx(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_vx(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_vx(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_vx(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_vx(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_vx(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_vx(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_vx(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_vx(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_vx(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_vx(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_vx(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_vx(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vwsubu_vx(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_vx(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_vx(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_vx(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_vx(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_vx(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_vx(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_vx(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_vx(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_vx(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_vx(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_vx(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_vx(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_vx(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_vx(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx-2.C new file mode 100644 index 00000000000..d6c4415f763 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx-2.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vx(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_vx(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_vx(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_vx(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_vx(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_vx(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_vx(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_vx(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_vx(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_vx(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_vx(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_vx(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_vx(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_vx(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_vx(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,31); +} + + +vuint16mf4_t test___riscv_vwsubu_vx(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_vx(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_vx(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_vx(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_vx(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_vx(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_vx(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_vx(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_vx(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_vx(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_vx(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_vx(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_vx(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_vx(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_vx(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx-3.C new file mode 100644 index 00000000000..8abb5f24f57 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx-3.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vx(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_vx(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_vx(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_vx(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_vx(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_vx(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_vx(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_vx(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_vx(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_vx(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_vx(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_vx(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_vx(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_vx(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_vx(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(op1,op2,32); +} + + +vuint16mf4_t test___riscv_vwsubu_vx(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_vx(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_vx(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_vx(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_vx(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_vx(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_vx(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_vx(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_vx(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_vx(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_vx(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_vx(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_vx(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_vx(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_vx(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_mu-1.C new file mode 100644 index 00000000000..e6ea78ab3ec --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_mu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vx_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_vx_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_vx_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_vx_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_vx_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_vx_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_vx_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_vx_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_vx_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_vx_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_vx_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_vx_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_vx_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_vx_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_vx_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_mu-2.C new file mode 100644 index 00000000000..9529a30d305 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_mu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vx_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_vx_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_vx_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_vx_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_vx_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_vx_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_vx_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_vx_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_vx_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_vx_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_vx_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_vx_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_vx_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_vx_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_vx_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_mu-3.C new file mode 100644 index 00000000000..030b4aeb4b4 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_mu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vx_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_vx_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_vx_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_vx_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_vx_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_vx_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_vx_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_vx_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_vx_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_vx_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_vx_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_vx_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_vx_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_vx_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_vx_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tu-1.C new file mode 100644 index 00000000000..c83f7cfbfe0 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vx_tu(vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_vx_tu(vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_vx_tu(vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_vx_tu(vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_vx_tu(vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_vx_tu(vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_vx_tu(vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_vx_tu(vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_vx_tu(vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_vx_tu(vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_vx_tu(vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_vx_tu(vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_vx_tu(vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_vx_tu(vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_vx_tu(vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tu-2.C new file mode 100644 index 00000000000..1945a356c40 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vx_tu(vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_vx_tu(vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_vx_tu(vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_vx_tu(vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_vx_tu(vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_vx_tu(vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_vx_tu(vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_vx_tu(vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_vx_tu(vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_vx_tu(vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_vx_tu(vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_vx_tu(vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_vx_tu(vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_vx_tu(vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_vx_tu(vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tu-3.C new file mode 100644 index 00000000000..0a9c93bbdd1 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vx_tu(vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_vx_tu(vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_vx_tu(vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_vx_tu(vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_vx_tu(vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_vx_tu(vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_vx_tu(vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_vx_tu(vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_vx_tu(vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_vx_tu(vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_vx_tu(vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_vx_tu(vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_vx_tu(vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_vx_tu(vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_vx_tu(vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tum-1.C new file mode 100644 index 00000000000..e76d4dbce58 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tum-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vx_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_vx_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_vx_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_vx_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_vx_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_vx_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_vx_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_vx_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_vx_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_vx_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_vx_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_vx_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_vx_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_vx_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_vx_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tum-2.C new file mode 100644 index 00000000000..d9200e14436 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tum-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vx_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_vx_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_vx_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_vx_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_vx_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_vx_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_vx_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_vx_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_vx_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_vx_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_vx_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_vx_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_vx_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_vx_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_vx_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tum-3.C new file mode 100644 index 00000000000..68bb7b46062 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tum-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vx_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_vx_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_vx_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_vx_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_vx_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_vx_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_vx_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_vx_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_vx_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_vx_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_vx_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_vx_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_vx_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_vx_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_vx_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tumu-1.C new file mode 100644 index 00000000000..4286106e624 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tumu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vx_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwsubu_vx_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwsubu_vx_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwsubu_vx_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwsubu_vx_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwsubu_vx_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwsubu_vx_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwsubu_vx_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwsubu_vx_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwsubu_vx_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwsubu_vx_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwsubu_vx_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwsubu_vx_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwsubu_vx_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwsubu_vx_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tumu-2.C new file mode 100644 index 00000000000..4d87f64712b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tumu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vx_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwsubu_vx_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwsubu_vx_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwsubu_vx_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwsubu_vx_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwsubu_vx_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwsubu_vx_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwsubu_vx_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwsubu_vx_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwsubu_vx_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwsubu_vx_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwsubu_vx_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwsubu_vx_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwsubu_vx_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwsubu_vx_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tumu-3.C new file mode 100644 index 00000000000..134696af101 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_vx_tumu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwsubu_vx_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwsubu_vx_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwsubu_vx_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwsubu_vx_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwsubu_vx_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwsubu_vx_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwsubu_vx_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwsubu_vx_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwsubu_vx_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwsubu_vx_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwsubu_vx_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwsubu_vx_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwsubu_vx_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwsubu_vx_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwsubu_vx_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwsubu_vx_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */