From patchwork Tue Feb 7 06:35:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 64417 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6BEF03858D39 for ; Tue, 7 Feb 2023 06:36:29 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgbr1.qq.com (smtpbgbr1.qq.com [54.207.19.206]) by sourceware.org (Postfix) with ESMTPS id 52BED3858D1E for ; Tue, 7 Feb 2023 06:35:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 52BED3858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp66t1675751751t3ppuwkd Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 07 Feb 2023 14:35:50 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: VpEAAF+twMLIAIjXoStKqjG2G6357ZeKGUxqaAkfloHEAKeEwRbWv6ZqM/ULN SFZEUCzP3PXQVp1JiX23iLKbhqP3DqFFcGMFmzVBOWdfuL0pUPycCBfj58qk/8T5WgoMkRb 1xqvSiWx/WHXv7BLptzfIemD/HFU6yLh6bhDmc0ZRGsaeNSheDcL58zRHqbowmhiSOzoG6f t4agt0z2lZUSrIaBzQ5FyyZSzeqyLkj5f/P3/lGW+PTWKWkNkrCybAfVyngKlQy0mW12z2N GYjFCE4h8tFtpyadD/Et2VKytt8U8IwUe41f576dmSomHDdyzAu1HfkKmj4PVfOXrzMbKE0 U8kizmY/T6E/+WLnXoHIQDLqeyZrLzTQASQtAjJl9kBhUbOaFsRvIWXF0OWqdYmy/L7Tiia X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vwaddu.v C API tests Date: Tue, 7 Feb 2023 14:35:49 +0800 Message-Id: <20230207063549.40062-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vwaddu_vv-1.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vv-2.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vv-3.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vv_m-1.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vv_m-2.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vv_m-3.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vv_mu-1.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vv_mu-2.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vv_mu-3.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vv_tu-1.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vv_tu-2.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vv_tu-3.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vv_tum-1.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vv_tum-2.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vv_tum-3.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vv_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vv_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vv_tumu-3.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vx-1.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vx-2.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vx-3.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vx_m-1.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vx_m-2.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vx_m-3.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vx_mu-1.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vx_mu-2.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vx_mu-3.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vx_tu-1.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vx_tu-2.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vx_tu-3.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vx_tum-1.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vx_tum-2.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vx_tum-3.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vx_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vx_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vwaddu_vx_tumu-3.c: New test. --- .../gcc.target/riscv/rvv/base/vwaddu_vv-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwaddu_vv-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwaddu_vv-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwaddu_vv_m-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwaddu_vv_m-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwaddu_vv_m-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_vv_mu-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_vv_mu-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_vv_mu-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_vv_tu-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_vv_tu-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_vv_tu-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_vv_tum-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_vv_tum-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_vv_tum-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_vv_tumu-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_vv_tumu-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_vv_tumu-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwaddu_vx-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwaddu_vx-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwaddu_vx-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwaddu_vx_m-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwaddu_vx_m-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwaddu_vx_m-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_vx_mu-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_vx_mu-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_vx_mu-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_vx_tu-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_vx_tu-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_vx_tu-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_vx_tum-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_vx_tum-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_vx_tum-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_vx_tumu-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_vx_tumu-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_vx_tumu-3.c | 111 ++++++++++++++++++ 36 files changed, 3996 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tumu-3.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv-1.c new file mode 100644 index 00000000000..ad052b2b656 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vv_u16mf4(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf4(op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_vv_u16mf2(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf2(op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_vv_u16m1(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m1(op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_vv_u16m2(vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m2(op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_vv_u16m4(vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m4(op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_vv_u16m8(vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m8(op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_vv_u32mf2(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32mf2(op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_vv_u32m1(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m1(op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_vv_u32m2(vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m2(op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_vv_u32m4(vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m4(op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_vv_u32m8(vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m8(op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_vv_u64m1(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m1(op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_vv_u64m2(vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m2(op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_vv_u64m4(vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m4(op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_vv_u64m8(vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m8(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv-2.c new file mode 100644 index 00000000000..b6323fc4668 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vv_u16mf4(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf4(op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_vv_u16mf2(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf2(op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_vv_u16m1(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m1(op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_vv_u16m2(vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m2(op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_vv_u16m4(vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m4(op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_vv_u16m8(vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m8(op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_vv_u32mf2(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32mf2(op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_vv_u32m1(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m1(op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_vv_u32m2(vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m2(op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_vv_u32m4(vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m4(op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_vv_u32m8(vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m8(op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_vv_u64m1(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m1(op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_vv_u64m2(vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m2(op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_vv_u64m4(vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m4(op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_vv_u64m8(vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m8(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv-3.c new file mode 100644 index 00000000000..87840c61f87 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vv_u16mf4(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf4(op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_vv_u16mf2(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf2(op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_vv_u16m1(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m1(op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_vv_u16m2(vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m2(op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_vv_u16m4(vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m4(op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_vv_u16m8(vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m8(op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_vv_u32mf2(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32mf2(op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_vv_u32m1(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m1(op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_vv_u32m2(vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m2(op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_vv_u32m4(vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m4(op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_vv_u32m8(vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m8(op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_vv_u64m1(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m1(op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_vv_u64m2(vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m2(op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_vv_u64m4(vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m4(op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_vv_u64m8(vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m8(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_m-1.c new file mode 100644 index 00000000000..cea4cda9034 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_m-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vv_u16mf4_m(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf4_m(mask,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_vv_u16mf2_m(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf2_m(mask,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_vv_u16m1_m(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m1_m(mask,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_vv_u16m2_m(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m2_m(mask,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_vv_u16m4_m(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m4_m(mask,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_vv_u16m8_m(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m8_m(mask,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_vv_u32mf2_m(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32mf2_m(mask,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_vv_u32m1_m(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m1_m(mask,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_vv_u32m2_m(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m2_m(mask,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_vv_u32m4_m(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m4_m(mask,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_vv_u32m8_m(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m8_m(mask,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_vv_u64m1_m(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m1_m(mask,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_vv_u64m2_m(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m2_m(mask,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_vv_u64m4_m(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m4_m(mask,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_vv_u64m8_m(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m8_m(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_m-2.c new file mode 100644 index 00000000000..d60b8024a87 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_m-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vv_u16mf4_m(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf4_m(mask,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_vv_u16mf2_m(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf2_m(mask,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_vv_u16m1_m(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m1_m(mask,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_vv_u16m2_m(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m2_m(mask,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_vv_u16m4_m(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m4_m(mask,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_vv_u16m8_m(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m8_m(mask,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_vv_u32mf2_m(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32mf2_m(mask,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_vv_u32m1_m(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m1_m(mask,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_vv_u32m2_m(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m2_m(mask,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_vv_u32m4_m(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m4_m(mask,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_vv_u32m8_m(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m8_m(mask,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_vv_u64m1_m(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m1_m(mask,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_vv_u64m2_m(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m2_m(mask,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_vv_u64m4_m(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m4_m(mask,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_vv_u64m8_m(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m8_m(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_m-3.c new file mode 100644 index 00000000000..5358e69ed2f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_m-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vv_u16mf4_m(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf4_m(mask,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_vv_u16mf2_m(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf2_m(mask,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_vv_u16m1_m(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m1_m(mask,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_vv_u16m2_m(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m2_m(mask,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_vv_u16m4_m(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m4_m(mask,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_vv_u16m8_m(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m8_m(mask,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_vv_u32mf2_m(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32mf2_m(mask,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_vv_u32m1_m(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m1_m(mask,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_vv_u32m2_m(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m2_m(mask,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_vv_u32m4_m(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m4_m(mask,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_vv_u32m8_m(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m8_m(mask,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_vv_u64m1_m(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m1_m(mask,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_vv_u64m2_m(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m2_m(mask,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_vv_u64m4_m(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m4_m(mask,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_vv_u64m8_m(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m8_m(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_mu-1.c new file mode 100644 index 00000000000..dd611c6058e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_mu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf4_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_vv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf2_mu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_vv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m1_mu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_vv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m2_mu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_vv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m4_mu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_vv_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m8_mu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_vv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32mf2_mu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_vv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m1_mu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_vv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m2_mu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_vv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m4_mu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_vv_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m8_mu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_vv_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m1_mu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_vv_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m2_mu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_vv_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m4_mu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_vv_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m8_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_mu-2.c new file mode 100644 index 00000000000..2b7431fbfe0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_mu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf4_mu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_vv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf2_mu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_vv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m1_mu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_vv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m2_mu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_vv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m4_mu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_vv_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m8_mu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_vv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32mf2_mu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_vv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m1_mu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_vv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m2_mu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_vv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m4_mu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_vv_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m8_mu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_vv_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m1_mu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_vv_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m2_mu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_vv_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m4_mu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_vv_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m8_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_mu-3.c new file mode 100644 index 00000000000..aa760640e83 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_mu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf4_mu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_vv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf2_mu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_vv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m1_mu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_vv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m2_mu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_vv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m4_mu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_vv_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m8_mu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_vv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32mf2_mu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_vv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m1_mu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_vv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m2_mu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_vv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m4_mu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_vv_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m8_mu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_vv_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m1_mu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_vv_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m2_mu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_vv_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m4_mu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_vv_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m8_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tu-1.c new file mode 100644 index 00000000000..5f4b52393a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vv_u16mf4_tu(vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf4_tu(merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_vv_u16mf2_tu(vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf2_tu(merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_vv_u16m1_tu(vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m1_tu(merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_vv_u16m2_tu(vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m2_tu(merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_vv_u16m4_tu(vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m4_tu(merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_vv_u16m8_tu(vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m8_tu(merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_vv_u32mf2_tu(vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32mf2_tu(merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_vv_u32m1_tu(vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m1_tu(merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_vv_u32m2_tu(vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m2_tu(merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_vv_u32m4_tu(vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m4_tu(merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_vv_u32m8_tu(vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m8_tu(merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_vv_u64m1_tu(vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m1_tu(merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_vv_u64m2_tu(vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m2_tu(merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_vv_u64m4_tu(vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m4_tu(merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_vv_u64m8_tu(vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m8_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tu-2.c new file mode 100644 index 00000000000..67ab6d76730 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vv_u16mf4_tu(vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf4_tu(merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_vv_u16mf2_tu(vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf2_tu(merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_vv_u16m1_tu(vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m1_tu(merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_vv_u16m2_tu(vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m2_tu(merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_vv_u16m4_tu(vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m4_tu(merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_vv_u16m8_tu(vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m8_tu(merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_vv_u32mf2_tu(vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32mf2_tu(merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_vv_u32m1_tu(vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m1_tu(merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_vv_u32m2_tu(vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m2_tu(merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_vv_u32m4_tu(vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m4_tu(merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_vv_u32m8_tu(vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m8_tu(merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_vv_u64m1_tu(vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m1_tu(merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_vv_u64m2_tu(vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m2_tu(merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_vv_u64m4_tu(vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m4_tu(merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_vv_u64m8_tu(vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m8_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tu-3.c new file mode 100644 index 00000000000..98236d3e34d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vv_u16mf4_tu(vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf4_tu(merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_vv_u16mf2_tu(vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf2_tu(merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_vv_u16m1_tu(vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m1_tu(merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_vv_u16m2_tu(vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m2_tu(merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_vv_u16m4_tu(vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m4_tu(merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_vv_u16m8_tu(vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m8_tu(merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_vv_u32mf2_tu(vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32mf2_tu(merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_vv_u32m1_tu(vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m1_tu(merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_vv_u32m2_tu(vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m2_tu(merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_vv_u32m4_tu(vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m4_tu(merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_vv_u32m8_tu(vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m8_tu(merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_vv_u64m1_tu(vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m1_tu(merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_vv_u64m2_tu(vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m2_tu(merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_vv_u64m4_tu(vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m4_tu(merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_vv_u64m8_tu(vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m8_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tum-1.c new file mode 100644 index 00000000000..c11daff049e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tum-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf4_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_vv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf2_tum(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_vv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m1_tum(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_vv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m2_tum(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_vv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m4_tum(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_vv_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m8_tum(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_vv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32mf2_tum(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_vv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m1_tum(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_vv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m2_tum(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_vv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m4_tum(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_vv_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m8_tum(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_vv_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m1_tum(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_vv_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m2_tum(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_vv_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m4_tum(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_vv_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m8_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tum-2.c new file mode 100644 index 00000000000..3058d6a714f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tum-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf4_tum(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_vv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf2_tum(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_vv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m1_tum(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_vv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m2_tum(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_vv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m4_tum(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_vv_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m8_tum(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_vv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32mf2_tum(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_vv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m1_tum(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_vv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m2_tum(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_vv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m4_tum(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_vv_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m8_tum(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_vv_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m1_tum(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_vv_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m2_tum(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_vv_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m4_tum(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_vv_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m8_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tum-3.c new file mode 100644 index 00000000000..fd6a920dd18 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tum-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf4_tum(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_vv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf2_tum(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_vv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m1_tum(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_vv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m2_tum(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_vv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m4_tum(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_vv_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m8_tum(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_vv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32mf2_tum(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_vv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m1_tum(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_vv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m2_tum(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_vv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m4_tum(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_vv_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m8_tum(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_vv_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m1_tum(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_vv_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m2_tum(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_vv_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m4_tum(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_vv_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m8_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tumu-1.c new file mode 100644 index 00000000000..ea61b4d1a14 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tumu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf4_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_vv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf2_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_vv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m1_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_vv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m2_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_vv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m4_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_vv_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m8_tumu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_vv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32mf2_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_vv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m1_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_vv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m2_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_vv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m4_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_vv_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m8_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_vv_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m1_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_vv_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m2_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_vv_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m4_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_vv_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m8_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tumu-2.c new file mode 100644 index 00000000000..225a5de6053 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tumu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf4_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_vv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf2_tumu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_vv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m1_tumu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_vv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m2_tumu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_vv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m4_tumu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_vv_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m8_tumu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_vv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32mf2_tumu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_vv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m1_tumu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_vv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m2_tumu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_vv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m4_tumu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_vv_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m8_tumu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_vv_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m1_tumu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_vv_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m2_tumu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_vv_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m4_tumu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_vv_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m8_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tumu-3.c new file mode 100644 index 00000000000..902fe89f898 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vv_tumu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf4_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_vv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16mf2_tumu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_vv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m1_tumu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_vv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m2_tumu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_vv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m4_tumu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_vv_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u16m8_tumu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_vv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32mf2_tumu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_vv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m1_tumu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_vv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m2_tumu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_vv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m4_tumu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_vv_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u32m8_tumu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_vv_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m1_tumu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_vv_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m2_tumu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_vv_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m4_tumu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_vv_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_vv_u64m8_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx-1.c new file mode 100644 index 00000000000..cb0f2e75816 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vx_u16mf4(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf4(op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_vx_u16mf2(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf2(op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_vx_u16m1(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m1(op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_vx_u16m2(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m2(op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_vx_u16m4(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m4(op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_vx_u16m8(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m8(op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_vx_u32mf2(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32mf2(op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_vx_u32m1(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m1(op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_vx_u32m2(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m2(op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_vx_u32m4(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m4(op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_vx_u32m8(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m8(op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_vx_u64m1(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m1(op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_vx_u64m2(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m2(op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_vx_u64m4(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m4(op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_vx_u64m8(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m8(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx-2.c new file mode 100644 index 00000000000..9cc055a2ec4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vx_u16mf4(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf4(op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_vx_u16mf2(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf2(op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_vx_u16m1(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m1(op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_vx_u16m2(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m2(op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_vx_u16m4(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m4(op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_vx_u16m8(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m8(op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_vx_u32mf2(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32mf2(op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_vx_u32m1(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m1(op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_vx_u32m2(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m2(op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_vx_u32m4(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m4(op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_vx_u32m8(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m8(op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_vx_u64m1(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m1(op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_vx_u64m2(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m2(op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_vx_u64m4(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m4(op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_vx_u64m8(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m8(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx-3.c new file mode 100644 index 00000000000..5553a474d77 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vx_u16mf4(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf4(op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_vx_u16mf2(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf2(op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_vx_u16m1(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m1(op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_vx_u16m2(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m2(op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_vx_u16m4(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m4(op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_vx_u16m8(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m8(op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_vx_u32mf2(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32mf2(op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_vx_u32m1(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m1(op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_vx_u32m2(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m2(op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_vx_u32m4(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m4(op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_vx_u32m8(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m8(op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_vx_u64m1(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m1(op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_vx_u64m2(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m2(op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_vx_u64m4(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m4(op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_vx_u64m8(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m8(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_m-1.c new file mode 100644 index 00000000000..4b01b8a391f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_m-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vx_u16mf4_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf4_m(mask,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_vx_u16mf2_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf2_m(mask,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_vx_u16m1_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m1_m(mask,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_vx_u16m2_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m2_m(mask,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_vx_u16m4_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m4_m(mask,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_vx_u16m8_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m8_m(mask,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_vx_u32mf2_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32mf2_m(mask,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_vx_u32m1_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m1_m(mask,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_vx_u32m2_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m2_m(mask,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_vx_u32m4_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m4_m(mask,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_vx_u32m8_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m8_m(mask,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_vx_u64m1_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m1_m(mask,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_vx_u64m2_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m2_m(mask,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_vx_u64m4_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m4_m(mask,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_vx_u64m8_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m8_m(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_m-2.c new file mode 100644 index 00000000000..a30bb6c4d15 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_m-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vx_u16mf4_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf4_m(mask,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_vx_u16mf2_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf2_m(mask,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_vx_u16m1_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m1_m(mask,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_vx_u16m2_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m2_m(mask,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_vx_u16m4_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m4_m(mask,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_vx_u16m8_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m8_m(mask,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_vx_u32mf2_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32mf2_m(mask,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_vx_u32m1_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m1_m(mask,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_vx_u32m2_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m2_m(mask,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_vx_u32m4_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m4_m(mask,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_vx_u32m8_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m8_m(mask,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_vx_u64m1_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m1_m(mask,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_vx_u64m2_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m2_m(mask,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_vx_u64m4_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m4_m(mask,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_vx_u64m8_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m8_m(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_m-3.c new file mode 100644 index 00000000000..f0003730778 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_m-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vx_u16mf4_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf4_m(mask,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_vx_u16mf2_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf2_m(mask,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_vx_u16m1_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m1_m(mask,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_vx_u16m2_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m2_m(mask,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_vx_u16m4_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m4_m(mask,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_vx_u16m8_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m8_m(mask,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_vx_u32mf2_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32mf2_m(mask,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_vx_u32m1_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m1_m(mask,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_vx_u32m2_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m2_m(mask,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_vx_u32m4_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m4_m(mask,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_vx_u32m8_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m8_m(mask,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_vx_u64m1_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m1_m(mask,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_vx_u64m2_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m2_m(mask,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_vx_u64m4_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m4_m(mask,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_vx_u64m8_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m8_m(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_mu-1.c new file mode 100644 index 00000000000..7ff41bd1c2d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_mu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf4_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_vx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf2_mu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_vx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m1_mu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_vx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m2_mu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_vx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m4_mu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_vx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m8_mu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_vx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32mf2_mu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_vx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m1_mu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_vx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m2_mu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_vx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m4_mu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_vx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m8_mu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_vx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m1_mu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_vx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m2_mu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_vx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m4_mu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_vx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m8_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_mu-2.c new file mode 100644 index 00000000000..544e59e9618 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_mu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf4_mu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_vx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf2_mu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_vx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m1_mu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_vx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m2_mu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_vx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m4_mu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_vx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m8_mu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_vx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32mf2_mu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_vx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m1_mu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_vx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m2_mu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_vx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m4_mu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_vx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m8_mu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_vx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m1_mu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_vx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m2_mu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_vx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m4_mu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_vx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m8_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_mu-3.c new file mode 100644 index 00000000000..b074441058a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_mu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf4_mu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_vx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf2_mu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_vx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m1_mu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_vx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m2_mu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_vx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m4_mu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_vx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m8_mu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_vx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32mf2_mu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_vx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m1_mu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_vx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m2_mu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_vx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m4_mu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_vx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m8_mu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_vx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m1_mu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_vx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m2_mu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_vx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m4_mu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_vx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m8_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tu-1.c new file mode 100644 index 00000000000..1510f847afd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vx_u16mf4_tu(vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf4_tu(merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_vx_u16mf2_tu(vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf2_tu(merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_vx_u16m1_tu(vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m1_tu(merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_vx_u16m2_tu(vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m2_tu(merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_vx_u16m4_tu(vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m4_tu(merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_vx_u16m8_tu(vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m8_tu(merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_vx_u32mf2_tu(vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32mf2_tu(merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_vx_u32m1_tu(vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m1_tu(merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_vx_u32m2_tu(vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m2_tu(merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_vx_u32m4_tu(vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m4_tu(merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_vx_u32m8_tu(vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m8_tu(merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_vx_u64m1_tu(vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m1_tu(merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_vx_u64m2_tu(vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m2_tu(merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_vx_u64m4_tu(vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m4_tu(merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_vx_u64m8_tu(vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m8_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tu-2.c new file mode 100644 index 00000000000..d705efad2bb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vx_u16mf4_tu(vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf4_tu(merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_vx_u16mf2_tu(vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf2_tu(merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_vx_u16m1_tu(vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m1_tu(merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_vx_u16m2_tu(vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m2_tu(merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_vx_u16m4_tu(vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m4_tu(merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_vx_u16m8_tu(vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m8_tu(merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_vx_u32mf2_tu(vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32mf2_tu(merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_vx_u32m1_tu(vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m1_tu(merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_vx_u32m2_tu(vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m2_tu(merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_vx_u32m4_tu(vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m4_tu(merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_vx_u32m8_tu(vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m8_tu(merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_vx_u64m1_tu(vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m1_tu(merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_vx_u64m2_tu(vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m2_tu(merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_vx_u64m4_tu(vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m4_tu(merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_vx_u64m8_tu(vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m8_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tu-3.c new file mode 100644 index 00000000000..4cb1cd07cc6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vx_u16mf4_tu(vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf4_tu(merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_vx_u16mf2_tu(vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf2_tu(merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_vx_u16m1_tu(vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m1_tu(merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_vx_u16m2_tu(vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m2_tu(merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_vx_u16m4_tu(vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m4_tu(merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_vx_u16m8_tu(vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m8_tu(merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_vx_u32mf2_tu(vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32mf2_tu(merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_vx_u32m1_tu(vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m1_tu(merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_vx_u32m2_tu(vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m2_tu(merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_vx_u32m4_tu(vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m4_tu(merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_vx_u32m8_tu(vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m8_tu(merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_vx_u64m1_tu(vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m1_tu(merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_vx_u64m2_tu(vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m2_tu(merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_vx_u64m4_tu(vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m4_tu(merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_vx_u64m8_tu(vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m8_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tum-1.c new file mode 100644 index 00000000000..30400d82097 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tum-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf4_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_vx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf2_tum(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_vx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m1_tum(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_vx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m2_tum(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_vx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m4_tum(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_vx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m8_tum(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_vx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32mf2_tum(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_vx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m1_tum(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_vx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m2_tum(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_vx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m4_tum(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_vx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m8_tum(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_vx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m1_tum(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_vx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m2_tum(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_vx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m4_tum(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_vx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m8_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tum-2.c new file mode 100644 index 00000000000..9bf5b8d64a3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tum-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf4_tum(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_vx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf2_tum(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_vx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m1_tum(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_vx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m2_tum(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_vx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m4_tum(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_vx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m8_tum(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_vx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32mf2_tum(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_vx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m1_tum(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_vx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m2_tum(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_vx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m4_tum(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_vx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m8_tum(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_vx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m1_tum(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_vx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m2_tum(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_vx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m4_tum(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_vx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m8_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tum-3.c new file mode 100644 index 00000000000..e02044515c0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tum-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf4_tum(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_vx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf2_tum(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_vx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m1_tum(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_vx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m2_tum(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_vx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m4_tum(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_vx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m8_tum(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_vx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32mf2_tum(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_vx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m1_tum(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_vx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m2_tum(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_vx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m4_tum(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_vx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m8_tum(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_vx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m1_tum(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_vx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m2_tum(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_vx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m4_tum(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_vx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m8_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tumu-1.c new file mode 100644 index 00000000000..b0ca5020d60 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tumu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf4_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_vx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf2_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_vx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m1_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_vx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m2_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_vx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m4_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_vx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m8_tumu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_vx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32mf2_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_vx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m1_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_vx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m2_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_vx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m4_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_vx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m8_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_vx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m1_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_vx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m2_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_vx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m4_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_vx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m8_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tumu-2.c new file mode 100644 index 00000000000..bd66322b13f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tumu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf4_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_vx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf2_tumu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_vx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m1_tumu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_vx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m2_tumu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_vx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m4_tumu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_vx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m8_tumu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_vx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32mf2_tumu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_vx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m1_tumu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_vx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m2_tumu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_vx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m4_tumu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_vx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m8_tumu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_vx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m1_tumu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_vx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m2_tumu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_vx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m4_tumu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_vx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m8_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tumu-3.c new file mode 100644 index 00000000000..47ea619d0c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_vx_tumu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_vx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf4_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_vx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16mf2_tumu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_vx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m1_tumu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_vx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m2_tumu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_vx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m4_tumu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_vx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u16m8_tumu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_vx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32mf2_tumu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_vx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m1_tumu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_vx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m2_tumu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_vx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m4_tumu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_vx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u32m8_tumu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_vx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m1_tumu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_vx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m2_tumu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_vx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m4_tumu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_vx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_vx_u64m8_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwaddu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */