From patchwork Tue Feb 7 06:34:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 64416 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 90A923858436 for ; Tue, 7 Feb 2023 06:35:26 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgeu1.qq.com (smtpbgeu1.qq.com [52.59.177.22]) by sourceware.org (Postfix) with ESMTPS id B5B2C3858D33 for ; Tue, 7 Feb 2023 06:34:53 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B5B2C3858D33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp66t1675751688tmsdec6j Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 07 Feb 2023 14:34:47 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: 0laiA9+vjADjipUY8liTVC1P4L8/cOd5dmTzkx1eJz76UOAk1ec1J+vZoPIbX L3hYlkQ5egZXBq7d4vJHbgLw7FiEmm41hC0xMx7FSt50ZeufIc2KOSWzW3NxW0SKEe4VP5u iTbuhcPf/C3s97BK4vmx18mtWde4xOA9Ni6O0aS3NcNxmWlTel/IYnk9M4bV1muT1a+bLL8 hld9qaJk6v9sZCs0cZgZs+3jAM+n6wMV8OEyqkS2tllUOI+DcHH6eJfioMuXgVZY34H6DTT 2I66dhyxeASmvypRjdnO+O2WdcK2N29LNWHRC49bZtmqFnj8ZLqCa/yMjgvw9DJrr/6dGL5 322tSeM86KJKP2LVajMh4hQ3mFR1arQVHft5Fdvo3ap3b5qiPbUzpu61UDottXWew133x63 X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vwaddu.w C API tests Date: Tue, 7 Feb 2023 14:34:47 +0800 Message-Id: <20230207063447.39828-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_PASS, TXREP, T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vwaddu_wv-1.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wv-2.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wv-3.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wv_m-1.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wv_m-2.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wv_m-3.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wv_mu-1.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wv_mu-2.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wv_mu-3.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wv_tu-1.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wv_tu-2.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wv_tu-3.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wv_tum-1.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wv_tum-2.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wv_tum-3.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wv_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wv_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wv_tumu-3.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wx-1.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wx-2.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wx-3.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wx_m-1.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wx_m-2.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wx_m-3.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wx_mu-1.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wx_mu-2.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wx_mu-3.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wx_tu-1.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wx_tu-2.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wx_tu-3.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wx_tum-1.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wx_tum-2.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wx_tum-3.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wx_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wx_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vwaddu_wx_tumu-3.c: New test. --- .../gcc.target/riscv/rvv/base/vwaddu_wv-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwaddu_wv-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwaddu_wv-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwaddu_wv_m-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwaddu_wv_m-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwaddu_wv_m-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_wv_mu-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_wv_mu-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_wv_mu-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_wv_tu-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_wv_tu-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_wv_tu-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_wv_tum-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_wv_tum-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_wv_tum-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_wv_tumu-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_wv_tumu-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_wv_tumu-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwaddu_wx-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwaddu_wx-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwaddu_wx-3.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwaddu_wx_m-1.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwaddu_wx_m-2.c | 111 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vwaddu_wx_m-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_wx_mu-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_wx_mu-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_wx_mu-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_wx_tu-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_wx_tu-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_wx_tu-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_wx_tum-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_wx_tum-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_wx_tum-3.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_wx_tumu-1.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_wx_tumu-2.c | 111 ++++++++++++++++++ .../riscv/rvv/base/vwaddu_wx_tumu-3.c | 111 ++++++++++++++++++ 36 files changed, 3996 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tumu-3.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv-1.c new file mode 100644 index 00000000000..6551c149170 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wv_u16mf4(vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf4(op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_wv_u16mf2(vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf2(op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_wv_u16m1(vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m1(op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_wv_u16m2(vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m2(op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_wv_u16m4(vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m4(op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_wv_u16m8(vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m8(op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_wv_u32mf2(vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32mf2(op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_wv_u32m1(vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m1(op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_wv_u32m2(vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m2(op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_wv_u32m4(vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m4(op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_wv_u32m8(vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m8(op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_wv_u64m1(vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m1(op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_wv_u64m2(vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m2(op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_wv_u64m4(vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m4(op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_wv_u64m8(vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m8(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv-2.c new file mode 100644 index 00000000000..3330babccdd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wv_u16mf4(vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf4(op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_wv_u16mf2(vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf2(op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_wv_u16m1(vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m1(op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_wv_u16m2(vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m2(op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_wv_u16m4(vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m4(op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_wv_u16m8(vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m8(op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_wv_u32mf2(vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32mf2(op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_wv_u32m1(vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m1(op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_wv_u32m2(vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m2(op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_wv_u32m4(vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m4(op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_wv_u32m8(vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m8(op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_wv_u64m1(vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m1(op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_wv_u64m2(vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m2(op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_wv_u64m4(vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m4(op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_wv_u64m8(vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m8(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv-3.c new file mode 100644 index 00000000000..934b21826d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wv_u16mf4(vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf4(op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_wv_u16mf2(vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf2(op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_wv_u16m1(vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m1(op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_wv_u16m2(vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m2(op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_wv_u16m4(vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m4(op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_wv_u16m8(vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m8(op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_wv_u32mf2(vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32mf2(op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_wv_u32m1(vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m1(op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_wv_u32m2(vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m2(op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_wv_u32m4(vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m4(op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_wv_u32m8(vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m8(op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_wv_u64m1(vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m1(op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_wv_u64m2(vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m2(op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_wv_u64m4(vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m4(op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_wv_u64m8(vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m8(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_m-1.c new file mode 100644 index 00000000000..49d348493d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_m-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wv_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf4_m(mask,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_wv_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf2_m(mask,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_wv_u16m1_m(vbool16_t mask,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m1_m(mask,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_wv_u16m2_m(vbool8_t mask,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m2_m(mask,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_wv_u16m4_m(vbool4_t mask,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m4_m(mask,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_wv_u16m8_m(vbool2_t mask,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m8_m(mask,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_wv_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32mf2_m(mask,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_wv_u32m1_m(vbool32_t mask,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m1_m(mask,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_wv_u32m2_m(vbool16_t mask,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m2_m(mask,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_wv_u32m4_m(vbool8_t mask,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m4_m(mask,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_wv_u32m8_m(vbool4_t mask,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m8_m(mask,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_wv_u64m1_m(vbool64_t mask,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m1_m(mask,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_wv_u64m2_m(vbool32_t mask,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m2_m(mask,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_wv_u64m4_m(vbool16_t mask,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m4_m(mask,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_wv_u64m8_m(vbool8_t mask,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m8_m(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_m-2.c new file mode 100644 index 00000000000..6ef899d323d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_m-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wv_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf4_m(mask,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_wv_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf2_m(mask,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_wv_u16m1_m(vbool16_t mask,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m1_m(mask,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_wv_u16m2_m(vbool8_t mask,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m2_m(mask,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_wv_u16m4_m(vbool4_t mask,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m4_m(mask,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_wv_u16m8_m(vbool2_t mask,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m8_m(mask,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_wv_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32mf2_m(mask,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_wv_u32m1_m(vbool32_t mask,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m1_m(mask,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_wv_u32m2_m(vbool16_t mask,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m2_m(mask,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_wv_u32m4_m(vbool8_t mask,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m4_m(mask,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_wv_u32m8_m(vbool4_t mask,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m8_m(mask,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_wv_u64m1_m(vbool64_t mask,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m1_m(mask,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_wv_u64m2_m(vbool32_t mask,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m2_m(mask,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_wv_u64m4_m(vbool16_t mask,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m4_m(mask,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_wv_u64m8_m(vbool8_t mask,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m8_m(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_m-3.c new file mode 100644 index 00000000000..000cc486bb8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_m-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wv_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf4_m(mask,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_wv_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf2_m(mask,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_wv_u16m1_m(vbool16_t mask,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m1_m(mask,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_wv_u16m2_m(vbool8_t mask,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m2_m(mask,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_wv_u16m4_m(vbool4_t mask,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m4_m(mask,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_wv_u16m8_m(vbool2_t mask,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m8_m(mask,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_wv_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32mf2_m(mask,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_wv_u32m1_m(vbool32_t mask,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m1_m(mask,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_wv_u32m2_m(vbool16_t mask,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m2_m(mask,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_wv_u32m4_m(vbool8_t mask,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m4_m(mask,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_wv_u32m8_m(vbool4_t mask,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m8_m(mask,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_wv_u64m1_m(vbool64_t mask,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m1_m(mask,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_wv_u64m2_m(vbool32_t mask,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m2_m(mask,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_wv_u64m4_m(vbool16_t mask,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m4_m(mask,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_wv_u64m8_m(vbool8_t mask,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m8_m(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_mu-1.c new file mode 100644 index 00000000000..6940e3a40d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_mu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf4_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_wv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf2_mu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_wv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m1_mu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_wv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m2_mu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_wv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m4_mu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_wv_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m8_mu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_wv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32mf2_mu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_wv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m1_mu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_wv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m2_mu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_wv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m4_mu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_wv_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m8_mu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_wv_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m1_mu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_wv_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m2_mu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_wv_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m4_mu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_wv_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m8_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_mu-2.c new file mode 100644 index 00000000000..1ad558121cc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_mu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf4_mu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_wv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf2_mu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_wv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m1_mu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_wv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m2_mu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_wv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m4_mu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_wv_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m8_mu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_wv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32mf2_mu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_wv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m1_mu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_wv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m2_mu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_wv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m4_mu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_wv_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m8_mu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_wv_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m1_mu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_wv_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m2_mu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_wv_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m4_mu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_wv_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m8_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_mu-3.c new file mode 100644 index 00000000000..ec3b6407d73 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_mu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf4_mu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_wv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf2_mu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_wv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m1_mu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_wv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m2_mu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_wv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m4_mu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_wv_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m8_mu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_wv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32mf2_mu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_wv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m1_mu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_wv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m2_mu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_wv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m4_mu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_wv_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m8_mu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_wv_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m1_mu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_wv_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m2_mu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_wv_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m4_mu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_wv_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m8_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tu-1.c new file mode 100644 index 00000000000..4d3525c2c72 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wv_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf4_tu(merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_wv_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf2_tu(merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_wv_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m1_tu(merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_wv_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m2_tu(merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_wv_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m4_tu(merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_wv_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m8_tu(merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_wv_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32mf2_tu(merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_wv_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m1_tu(merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_wv_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m2_tu(merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_wv_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m4_tu(merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_wv_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m8_tu(merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_wv_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m1_tu(merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_wv_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m2_tu(merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_wv_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m4_tu(merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_wv_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m8_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tu-2.c new file mode 100644 index 00000000000..164cbafe98d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wv_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf4_tu(merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_wv_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf2_tu(merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_wv_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m1_tu(merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_wv_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m2_tu(merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_wv_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m4_tu(merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_wv_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m8_tu(merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_wv_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32mf2_tu(merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_wv_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m1_tu(merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_wv_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m2_tu(merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_wv_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m4_tu(merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_wv_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m8_tu(merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_wv_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m1_tu(merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_wv_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m2_tu(merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_wv_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m4_tu(merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_wv_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m8_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tu-3.c new file mode 100644 index 00000000000..0e4ba5e0954 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wv_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf4_tu(merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_wv_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf2_tu(merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_wv_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m1_tu(merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_wv_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m2_tu(merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_wv_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m4_tu(merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_wv_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m8_tu(merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_wv_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32mf2_tu(merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_wv_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m1_tu(merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_wv_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m2_tu(merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_wv_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m4_tu(merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_wv_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m8_tu(merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_wv_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m1_tu(merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_wv_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m2_tu(merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_wv_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m4_tu(merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_wv_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m8_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tum-1.c new file mode 100644 index 00000000000..9f5627c0c7d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tum-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf4_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_wv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf2_tum(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_wv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m1_tum(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_wv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m2_tum(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_wv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m4_tum(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_wv_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m8_tum(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_wv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32mf2_tum(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_wv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m1_tum(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_wv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m2_tum(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_wv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m4_tum(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_wv_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m8_tum(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_wv_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m1_tum(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_wv_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m2_tum(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_wv_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m4_tum(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_wv_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m8_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tum-2.c new file mode 100644 index 00000000000..e0fbb960a55 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tum-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf4_tum(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_wv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf2_tum(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_wv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m1_tum(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_wv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m2_tum(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_wv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m4_tum(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_wv_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m8_tum(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_wv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32mf2_tum(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_wv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m1_tum(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_wv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m2_tum(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_wv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m4_tum(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_wv_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m8_tum(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_wv_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m1_tum(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_wv_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m2_tum(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_wv_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m4_tum(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_wv_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m8_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tum-3.c new file mode 100644 index 00000000000..0c0a837cf37 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tum-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf4_tum(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_wv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf2_tum(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_wv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m1_tum(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_wv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m2_tum(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_wv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m4_tum(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_wv_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m8_tum(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_wv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32mf2_tum(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_wv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m1_tum(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_wv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m2_tum(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_wv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m4_tum(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_wv_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m8_tum(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_wv_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m1_tum(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_wv_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m2_tum(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_wv_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m4_tum(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_wv_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m8_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tumu-1.c new file mode 100644 index 00000000000..4947ae5d882 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tumu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf4_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_wv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf2_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vwaddu_wv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m1_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vwaddu_wv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m2_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vwaddu_wv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m4_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vwaddu_wv_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m8_tumu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_wv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32mf2_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vwaddu_wv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m1_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vwaddu_wv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m2_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vwaddu_wv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m4_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vwaddu_wv_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m8_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vwaddu_wv_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m1_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vwaddu_wv_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m2_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vwaddu_wv_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m4_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vwaddu_wv_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m8_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tumu-2.c new file mode 100644 index 00000000000..7d37f39b94b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tumu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf4_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vwaddu_wv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf2_tumu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vwaddu_wv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m1_tumu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vwaddu_wv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m2_tumu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vwaddu_wv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m4_tumu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vwaddu_wv_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m8_tumu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vwaddu_wv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32mf2_tumu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vwaddu_wv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m1_tumu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vwaddu_wv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m2_tumu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vwaddu_wv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m4_tumu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vwaddu_wv_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m8_tumu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vwaddu_wv_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m1_tumu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vwaddu_wv_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m2_tumu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vwaddu_wv_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m4_tumu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vwaddu_wv_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m8_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tumu-3.c new file mode 100644 index 00000000000..45ef9e6343e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wv_tumu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf4_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vwaddu_wv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16mf2_tumu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vwaddu_wv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m1_tumu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vwaddu_wv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m2_tumu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vwaddu_wv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m4_tumu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vwaddu_wv_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u16m8_tumu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vwaddu_wv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32mf2_tumu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vwaddu_wv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m1_tumu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vwaddu_wv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m2_tumu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vwaddu_wv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m4_tumu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vwaddu_wv_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u32m8_tumu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vwaddu_wv_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m1_tumu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vwaddu_wv_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m2_tumu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vwaddu_wv_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m4_tumu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vwaddu_wv_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwaddu_wv_u64m8_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwaddu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx-1.c new file mode 100644 index 00000000000..aafc884fca3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wx_u16mf4(vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf4(op1,0xAA,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_wx_u16mf2(vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf2(op1,0xAA,vl); +} + + +vuint16m1_t test___riscv_vwaddu_wx_u16m1(vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m1(op1,0xAA,vl); +} + + +vuint16m2_t test___riscv_vwaddu_wx_u16m2(vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m2(op1,0xAA,vl); +} + + +vuint16m4_t test___riscv_vwaddu_wx_u16m4(vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m4(op1,0xAA,vl); +} + + +vuint16m8_t test___riscv_vwaddu_wx_u16m8(vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m8(op1,0xAA,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_wx_u32mf2(vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32mf2(op1,0xAA,vl); +} + + +vuint32m1_t test___riscv_vwaddu_wx_u32m1(vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m1(op1,0xAA,vl); +} + + +vuint32m2_t test___riscv_vwaddu_wx_u32m2(vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m2(op1,0xAA,vl); +} + + +vuint32m4_t test___riscv_vwaddu_wx_u32m4(vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m4(op1,0xAA,vl); +} + + +vuint32m8_t test___riscv_vwaddu_wx_u32m8(vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m8(op1,0xAA,vl); +} + + +vuint64m1_t test___riscv_vwaddu_wx_u64m1(vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m1(op1,0xAA,vl); +} + + +vuint64m2_t test___riscv_vwaddu_wx_u64m2(vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m2(op1,0xAA,vl); +} + + +vuint64m4_t test___riscv_vwaddu_wx_u64m4(vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m4(op1,0xAA,vl); +} + + +vuint64m8_t test___riscv_vwaddu_wx_u64m8(vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m8(op1,0xAA,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx-2.c new file mode 100644 index 00000000000..015e9689bf8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wx_u16mf4(vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf4(op1,0xAA,31); +} + + +vuint16mf2_t test___riscv_vwaddu_wx_u16mf2(vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf2(op1,0xAA,31); +} + + +vuint16m1_t test___riscv_vwaddu_wx_u16m1(vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m1(op1,0xAA,31); +} + + +vuint16m2_t test___riscv_vwaddu_wx_u16m2(vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m2(op1,0xAA,31); +} + + +vuint16m4_t test___riscv_vwaddu_wx_u16m4(vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m4(op1,0xAA,31); +} + + +vuint16m8_t test___riscv_vwaddu_wx_u16m8(vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m8(op1,0xAA,31); +} + + +vuint32mf2_t test___riscv_vwaddu_wx_u32mf2(vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32mf2(op1,0xAA,31); +} + + +vuint32m1_t test___riscv_vwaddu_wx_u32m1(vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m1(op1,0xAA,31); +} + + +vuint32m2_t test___riscv_vwaddu_wx_u32m2(vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m2(op1,0xAA,31); +} + + +vuint32m4_t test___riscv_vwaddu_wx_u32m4(vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m4(op1,0xAA,31); +} + + +vuint32m8_t test___riscv_vwaddu_wx_u32m8(vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m8(op1,0xAA,31); +} + + +vuint64m1_t test___riscv_vwaddu_wx_u64m1(vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m1(op1,0xAA,31); +} + + +vuint64m2_t test___riscv_vwaddu_wx_u64m2(vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m2(op1,0xAA,31); +} + + +vuint64m4_t test___riscv_vwaddu_wx_u64m4(vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m4(op1,0xAA,31); +} + + +vuint64m8_t test___riscv_vwaddu_wx_u64m8(vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m8(op1,0xAA,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx-3.c new file mode 100644 index 00000000000..fc2fee472bb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wx_u16mf4(vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf4(op1,0xAA,32); +} + + +vuint16mf2_t test___riscv_vwaddu_wx_u16mf2(vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf2(op1,0xAA,32); +} + + +vuint16m1_t test___riscv_vwaddu_wx_u16m1(vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m1(op1,0xAA,32); +} + + +vuint16m2_t test___riscv_vwaddu_wx_u16m2(vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m2(op1,0xAA,32); +} + + +vuint16m4_t test___riscv_vwaddu_wx_u16m4(vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m4(op1,0xAA,32); +} + + +vuint16m8_t test___riscv_vwaddu_wx_u16m8(vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m8(op1,0xAA,32); +} + + +vuint32mf2_t test___riscv_vwaddu_wx_u32mf2(vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32mf2(op1,0xAA,32); +} + + +vuint32m1_t test___riscv_vwaddu_wx_u32m1(vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m1(op1,0xAA,32); +} + + +vuint32m2_t test___riscv_vwaddu_wx_u32m2(vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m2(op1,0xAA,32); +} + + +vuint32m4_t test___riscv_vwaddu_wx_u32m4(vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m4(op1,0xAA,32); +} + + +vuint32m8_t test___riscv_vwaddu_wx_u32m8(vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m8(op1,0xAA,32); +} + + +vuint64m1_t test___riscv_vwaddu_wx_u64m1(vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m1(op1,0xAA,32); +} + + +vuint64m2_t test___riscv_vwaddu_wx_u64m2(vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m2(op1,0xAA,32); +} + + +vuint64m4_t test___riscv_vwaddu_wx_u64m4(vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m4(op1,0xAA,32); +} + + +vuint64m8_t test___riscv_vwaddu_wx_u64m8(vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m8(op1,0xAA,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_m-1.c new file mode 100644 index 00000000000..2df9fe931d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_m-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wx_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf4_m(mask,op1,0xAA,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_wx_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf2_m(mask,op1,0xAA,vl); +} + + +vuint16m1_t test___riscv_vwaddu_wx_u16m1_m(vbool16_t mask,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m1_m(mask,op1,0xAA,vl); +} + + +vuint16m2_t test___riscv_vwaddu_wx_u16m2_m(vbool8_t mask,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m2_m(mask,op1,0xAA,vl); +} + + +vuint16m4_t test___riscv_vwaddu_wx_u16m4_m(vbool4_t mask,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m4_m(mask,op1,0xAA,vl); +} + + +vuint16m8_t test___riscv_vwaddu_wx_u16m8_m(vbool2_t mask,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m8_m(mask,op1,0xAA,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_wx_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32mf2_m(mask,op1,0xAA,vl); +} + + +vuint32m1_t test___riscv_vwaddu_wx_u32m1_m(vbool32_t mask,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m1_m(mask,op1,0xAA,vl); +} + + +vuint32m2_t test___riscv_vwaddu_wx_u32m2_m(vbool16_t mask,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m2_m(mask,op1,0xAA,vl); +} + + +vuint32m4_t test___riscv_vwaddu_wx_u32m4_m(vbool8_t mask,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m4_m(mask,op1,0xAA,vl); +} + + +vuint32m8_t test___riscv_vwaddu_wx_u32m8_m(vbool4_t mask,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m8_m(mask,op1,0xAA,vl); +} + + +vuint64m1_t test___riscv_vwaddu_wx_u64m1_m(vbool64_t mask,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m1_m(mask,op1,0xAA,vl); +} + + +vuint64m2_t test___riscv_vwaddu_wx_u64m2_m(vbool32_t mask,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m2_m(mask,op1,0xAA,vl); +} + + +vuint64m4_t test___riscv_vwaddu_wx_u64m4_m(vbool16_t mask,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m4_m(mask,op1,0xAA,vl); +} + + +vuint64m8_t test___riscv_vwaddu_wx_u64m8_m(vbool8_t mask,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m8_m(mask,op1,0xAA,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_m-2.c new file mode 100644 index 00000000000..557285dd4e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_m-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wx_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf4_m(mask,op1,0xAA,31); +} + + +vuint16mf2_t test___riscv_vwaddu_wx_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf2_m(mask,op1,0xAA,31); +} + + +vuint16m1_t test___riscv_vwaddu_wx_u16m1_m(vbool16_t mask,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m1_m(mask,op1,0xAA,31); +} + + +vuint16m2_t test___riscv_vwaddu_wx_u16m2_m(vbool8_t mask,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m2_m(mask,op1,0xAA,31); +} + + +vuint16m4_t test___riscv_vwaddu_wx_u16m4_m(vbool4_t mask,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m4_m(mask,op1,0xAA,31); +} + + +vuint16m8_t test___riscv_vwaddu_wx_u16m8_m(vbool2_t mask,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m8_m(mask,op1,0xAA,31); +} + + +vuint32mf2_t test___riscv_vwaddu_wx_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32mf2_m(mask,op1,0xAA,31); +} + + +vuint32m1_t test___riscv_vwaddu_wx_u32m1_m(vbool32_t mask,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m1_m(mask,op1,0xAA,31); +} + + +vuint32m2_t test___riscv_vwaddu_wx_u32m2_m(vbool16_t mask,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m2_m(mask,op1,0xAA,31); +} + + +vuint32m4_t test___riscv_vwaddu_wx_u32m4_m(vbool8_t mask,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m4_m(mask,op1,0xAA,31); +} + + +vuint32m8_t test___riscv_vwaddu_wx_u32m8_m(vbool4_t mask,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m8_m(mask,op1,0xAA,31); +} + + +vuint64m1_t test___riscv_vwaddu_wx_u64m1_m(vbool64_t mask,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m1_m(mask,op1,0xAA,31); +} + + +vuint64m2_t test___riscv_vwaddu_wx_u64m2_m(vbool32_t mask,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m2_m(mask,op1,0xAA,31); +} + + +vuint64m4_t test___riscv_vwaddu_wx_u64m4_m(vbool16_t mask,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m4_m(mask,op1,0xAA,31); +} + + +vuint64m8_t test___riscv_vwaddu_wx_u64m8_m(vbool8_t mask,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m8_m(mask,op1,0xAA,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_m-3.c new file mode 100644 index 00000000000..fe807dfbcb0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_m-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wx_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf4_m(mask,op1,0xAA,32); +} + + +vuint16mf2_t test___riscv_vwaddu_wx_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf2_m(mask,op1,0xAA,32); +} + + +vuint16m1_t test___riscv_vwaddu_wx_u16m1_m(vbool16_t mask,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m1_m(mask,op1,0xAA,32); +} + + +vuint16m2_t test___riscv_vwaddu_wx_u16m2_m(vbool8_t mask,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m2_m(mask,op1,0xAA,32); +} + + +vuint16m4_t test___riscv_vwaddu_wx_u16m4_m(vbool4_t mask,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m4_m(mask,op1,0xAA,32); +} + + +vuint16m8_t test___riscv_vwaddu_wx_u16m8_m(vbool2_t mask,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m8_m(mask,op1,0xAA,32); +} + + +vuint32mf2_t test___riscv_vwaddu_wx_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32mf2_m(mask,op1,0xAA,32); +} + + +vuint32m1_t test___riscv_vwaddu_wx_u32m1_m(vbool32_t mask,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m1_m(mask,op1,0xAA,32); +} + + +vuint32m2_t test___riscv_vwaddu_wx_u32m2_m(vbool16_t mask,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m2_m(mask,op1,0xAA,32); +} + + +vuint32m4_t test___riscv_vwaddu_wx_u32m4_m(vbool8_t mask,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m4_m(mask,op1,0xAA,32); +} + + +vuint32m8_t test___riscv_vwaddu_wx_u32m8_m(vbool4_t mask,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m8_m(mask,op1,0xAA,32); +} + + +vuint64m1_t test___riscv_vwaddu_wx_u64m1_m(vbool64_t mask,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m1_m(mask,op1,0xAA,32); +} + + +vuint64m2_t test___riscv_vwaddu_wx_u64m2_m(vbool32_t mask,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m2_m(mask,op1,0xAA,32); +} + + +vuint64m4_t test___riscv_vwaddu_wx_u64m4_m(vbool16_t mask,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m4_m(mask,op1,0xAA,32); +} + + +vuint64m8_t test___riscv_vwaddu_wx_u64m8_m(vbool8_t mask,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m8_m(mask,op1,0xAA,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_mu-1.c new file mode 100644 index 00000000000..20c54dada6b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_mu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf4_mu(mask,merge,op1,0xAA,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_wx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf2_mu(mask,merge,op1,0xAA,vl); +} + + +vuint16m1_t test___riscv_vwaddu_wx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m1_mu(mask,merge,op1,0xAA,vl); +} + + +vuint16m2_t test___riscv_vwaddu_wx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m2_mu(mask,merge,op1,0xAA,vl); +} + + +vuint16m4_t test___riscv_vwaddu_wx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m4_mu(mask,merge,op1,0xAA,vl); +} + + +vuint16m8_t test___riscv_vwaddu_wx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m8_mu(mask,merge,op1,0xAA,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_wx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32mf2_mu(mask,merge,op1,0xAA,vl); +} + + +vuint32m1_t test___riscv_vwaddu_wx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m1_mu(mask,merge,op1,0xAA,vl); +} + + +vuint32m2_t test___riscv_vwaddu_wx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m2_mu(mask,merge,op1,0xAA,vl); +} + + +vuint32m4_t test___riscv_vwaddu_wx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m4_mu(mask,merge,op1,0xAA,vl); +} + + +vuint32m8_t test___riscv_vwaddu_wx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m8_mu(mask,merge,op1,0xAA,vl); +} + + +vuint64m1_t test___riscv_vwaddu_wx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m1_mu(mask,merge,op1,0xAA,vl); +} + + +vuint64m2_t test___riscv_vwaddu_wx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m2_mu(mask,merge,op1,0xAA,vl); +} + + +vuint64m4_t test___riscv_vwaddu_wx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m4_mu(mask,merge,op1,0xAA,vl); +} + + +vuint64m8_t test___riscv_vwaddu_wx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m8_mu(mask,merge,op1,0xAA,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_mu-2.c new file mode 100644 index 00000000000..c50c3e177fe --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_mu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf4_mu(mask,merge,op1,0xAA,31); +} + + +vuint16mf2_t test___riscv_vwaddu_wx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf2_mu(mask,merge,op1,0xAA,31); +} + + +vuint16m1_t test___riscv_vwaddu_wx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m1_mu(mask,merge,op1,0xAA,31); +} + + +vuint16m2_t test___riscv_vwaddu_wx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m2_mu(mask,merge,op1,0xAA,31); +} + + +vuint16m4_t test___riscv_vwaddu_wx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m4_mu(mask,merge,op1,0xAA,31); +} + + +vuint16m8_t test___riscv_vwaddu_wx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m8_mu(mask,merge,op1,0xAA,31); +} + + +vuint32mf2_t test___riscv_vwaddu_wx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32mf2_mu(mask,merge,op1,0xAA,31); +} + + +vuint32m1_t test___riscv_vwaddu_wx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m1_mu(mask,merge,op1,0xAA,31); +} + + +vuint32m2_t test___riscv_vwaddu_wx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m2_mu(mask,merge,op1,0xAA,31); +} + + +vuint32m4_t test___riscv_vwaddu_wx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m4_mu(mask,merge,op1,0xAA,31); +} + + +vuint32m8_t test___riscv_vwaddu_wx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m8_mu(mask,merge,op1,0xAA,31); +} + + +vuint64m1_t test___riscv_vwaddu_wx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m1_mu(mask,merge,op1,0xAA,31); +} + + +vuint64m2_t test___riscv_vwaddu_wx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m2_mu(mask,merge,op1,0xAA,31); +} + + +vuint64m4_t test___riscv_vwaddu_wx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m4_mu(mask,merge,op1,0xAA,31); +} + + +vuint64m8_t test___riscv_vwaddu_wx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m8_mu(mask,merge,op1,0xAA,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_mu-3.c new file mode 100644 index 00000000000..fd01b9c33bb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_mu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf4_mu(mask,merge,op1,0xAA,32); +} + + +vuint16mf2_t test___riscv_vwaddu_wx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf2_mu(mask,merge,op1,0xAA,32); +} + + +vuint16m1_t test___riscv_vwaddu_wx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m1_mu(mask,merge,op1,0xAA,32); +} + + +vuint16m2_t test___riscv_vwaddu_wx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m2_mu(mask,merge,op1,0xAA,32); +} + + +vuint16m4_t test___riscv_vwaddu_wx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m4_mu(mask,merge,op1,0xAA,32); +} + + +vuint16m8_t test___riscv_vwaddu_wx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m8_mu(mask,merge,op1,0xAA,32); +} + + +vuint32mf2_t test___riscv_vwaddu_wx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32mf2_mu(mask,merge,op1,0xAA,32); +} + + +vuint32m1_t test___riscv_vwaddu_wx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m1_mu(mask,merge,op1,0xAA,32); +} + + +vuint32m2_t test___riscv_vwaddu_wx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m2_mu(mask,merge,op1,0xAA,32); +} + + +vuint32m4_t test___riscv_vwaddu_wx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m4_mu(mask,merge,op1,0xAA,32); +} + + +vuint32m8_t test___riscv_vwaddu_wx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m8_mu(mask,merge,op1,0xAA,32); +} + + +vuint64m1_t test___riscv_vwaddu_wx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m1_mu(mask,merge,op1,0xAA,32); +} + + +vuint64m2_t test___riscv_vwaddu_wx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m2_mu(mask,merge,op1,0xAA,32); +} + + +vuint64m4_t test___riscv_vwaddu_wx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m4_mu(mask,merge,op1,0xAA,32); +} + + +vuint64m8_t test___riscv_vwaddu_wx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m8_mu(mask,merge,op1,0xAA,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tu-1.c new file mode 100644 index 00000000000..4114409c1b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wx_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf4_tu(merge,op1,0xAA,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_wx_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf2_tu(merge,op1,0xAA,vl); +} + + +vuint16m1_t test___riscv_vwaddu_wx_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m1_tu(merge,op1,0xAA,vl); +} + + +vuint16m2_t test___riscv_vwaddu_wx_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m2_tu(merge,op1,0xAA,vl); +} + + +vuint16m4_t test___riscv_vwaddu_wx_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m4_tu(merge,op1,0xAA,vl); +} + + +vuint16m8_t test___riscv_vwaddu_wx_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m8_tu(merge,op1,0xAA,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_wx_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32mf2_tu(merge,op1,0xAA,vl); +} + + +vuint32m1_t test___riscv_vwaddu_wx_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m1_tu(merge,op1,0xAA,vl); +} + + +vuint32m2_t test___riscv_vwaddu_wx_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m2_tu(merge,op1,0xAA,vl); +} + + +vuint32m4_t test___riscv_vwaddu_wx_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m4_tu(merge,op1,0xAA,vl); +} + + +vuint32m8_t test___riscv_vwaddu_wx_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m8_tu(merge,op1,0xAA,vl); +} + + +vuint64m1_t test___riscv_vwaddu_wx_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m1_tu(merge,op1,0xAA,vl); +} + + +vuint64m2_t test___riscv_vwaddu_wx_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m2_tu(merge,op1,0xAA,vl); +} + + +vuint64m4_t test___riscv_vwaddu_wx_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m4_tu(merge,op1,0xAA,vl); +} + + +vuint64m8_t test___riscv_vwaddu_wx_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m8_tu(merge,op1,0xAA,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tu-2.c new file mode 100644 index 00000000000..03e9d2de6bf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wx_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf4_tu(merge,op1,0xAA,31); +} + + +vuint16mf2_t test___riscv_vwaddu_wx_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf2_tu(merge,op1,0xAA,31); +} + + +vuint16m1_t test___riscv_vwaddu_wx_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m1_tu(merge,op1,0xAA,31); +} + + +vuint16m2_t test___riscv_vwaddu_wx_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m2_tu(merge,op1,0xAA,31); +} + + +vuint16m4_t test___riscv_vwaddu_wx_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m4_tu(merge,op1,0xAA,31); +} + + +vuint16m8_t test___riscv_vwaddu_wx_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m8_tu(merge,op1,0xAA,31); +} + + +vuint32mf2_t test___riscv_vwaddu_wx_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32mf2_tu(merge,op1,0xAA,31); +} + + +vuint32m1_t test___riscv_vwaddu_wx_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m1_tu(merge,op1,0xAA,31); +} + + +vuint32m2_t test___riscv_vwaddu_wx_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m2_tu(merge,op1,0xAA,31); +} + + +vuint32m4_t test___riscv_vwaddu_wx_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m4_tu(merge,op1,0xAA,31); +} + + +vuint32m8_t test___riscv_vwaddu_wx_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m8_tu(merge,op1,0xAA,31); +} + + +vuint64m1_t test___riscv_vwaddu_wx_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m1_tu(merge,op1,0xAA,31); +} + + +vuint64m2_t test___riscv_vwaddu_wx_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m2_tu(merge,op1,0xAA,31); +} + + +vuint64m4_t test___riscv_vwaddu_wx_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m4_tu(merge,op1,0xAA,31); +} + + +vuint64m8_t test___riscv_vwaddu_wx_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m8_tu(merge,op1,0xAA,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tu-3.c new file mode 100644 index 00000000000..2c9301d0d77 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wx_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf4_tu(merge,op1,0xAA,32); +} + + +vuint16mf2_t test___riscv_vwaddu_wx_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf2_tu(merge,op1,0xAA,32); +} + + +vuint16m1_t test___riscv_vwaddu_wx_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m1_tu(merge,op1,0xAA,32); +} + + +vuint16m2_t test___riscv_vwaddu_wx_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m2_tu(merge,op1,0xAA,32); +} + + +vuint16m4_t test___riscv_vwaddu_wx_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m4_tu(merge,op1,0xAA,32); +} + + +vuint16m8_t test___riscv_vwaddu_wx_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m8_tu(merge,op1,0xAA,32); +} + + +vuint32mf2_t test___riscv_vwaddu_wx_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32mf2_tu(merge,op1,0xAA,32); +} + + +vuint32m1_t test___riscv_vwaddu_wx_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m1_tu(merge,op1,0xAA,32); +} + + +vuint32m2_t test___riscv_vwaddu_wx_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m2_tu(merge,op1,0xAA,32); +} + + +vuint32m4_t test___riscv_vwaddu_wx_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m4_tu(merge,op1,0xAA,32); +} + + +vuint32m8_t test___riscv_vwaddu_wx_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m8_tu(merge,op1,0xAA,32); +} + + +vuint64m1_t test___riscv_vwaddu_wx_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m1_tu(merge,op1,0xAA,32); +} + + +vuint64m2_t test___riscv_vwaddu_wx_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m2_tu(merge,op1,0xAA,32); +} + + +vuint64m4_t test___riscv_vwaddu_wx_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m4_tu(merge,op1,0xAA,32); +} + + +vuint64m8_t test___riscv_vwaddu_wx_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m8_tu(merge,op1,0xAA,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tum-1.c new file mode 100644 index 00000000000..e806519eb7f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tum-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf4_tum(mask,merge,op1,0xAA,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_wx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf2_tum(mask,merge,op1,0xAA,vl); +} + + +vuint16m1_t test___riscv_vwaddu_wx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m1_tum(mask,merge,op1,0xAA,vl); +} + + +vuint16m2_t test___riscv_vwaddu_wx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m2_tum(mask,merge,op1,0xAA,vl); +} + + +vuint16m4_t test___riscv_vwaddu_wx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m4_tum(mask,merge,op1,0xAA,vl); +} + + +vuint16m8_t test___riscv_vwaddu_wx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m8_tum(mask,merge,op1,0xAA,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_wx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32mf2_tum(mask,merge,op1,0xAA,vl); +} + + +vuint32m1_t test___riscv_vwaddu_wx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m1_tum(mask,merge,op1,0xAA,vl); +} + + +vuint32m2_t test___riscv_vwaddu_wx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m2_tum(mask,merge,op1,0xAA,vl); +} + + +vuint32m4_t test___riscv_vwaddu_wx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m4_tum(mask,merge,op1,0xAA,vl); +} + + +vuint32m8_t test___riscv_vwaddu_wx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m8_tum(mask,merge,op1,0xAA,vl); +} + + +vuint64m1_t test___riscv_vwaddu_wx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m1_tum(mask,merge,op1,0xAA,vl); +} + + +vuint64m2_t test___riscv_vwaddu_wx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m2_tum(mask,merge,op1,0xAA,vl); +} + + +vuint64m4_t test___riscv_vwaddu_wx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m4_tum(mask,merge,op1,0xAA,vl); +} + + +vuint64m8_t test___riscv_vwaddu_wx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m8_tum(mask,merge,op1,0xAA,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tum-2.c new file mode 100644 index 00000000000..1ff736f8b92 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tum-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf4_tum(mask,merge,op1,0xAA,31); +} + + +vuint16mf2_t test___riscv_vwaddu_wx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf2_tum(mask,merge,op1,0xAA,31); +} + + +vuint16m1_t test___riscv_vwaddu_wx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m1_tum(mask,merge,op1,0xAA,31); +} + + +vuint16m2_t test___riscv_vwaddu_wx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m2_tum(mask,merge,op1,0xAA,31); +} + + +vuint16m4_t test___riscv_vwaddu_wx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m4_tum(mask,merge,op1,0xAA,31); +} + + +vuint16m8_t test___riscv_vwaddu_wx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m8_tum(mask,merge,op1,0xAA,31); +} + + +vuint32mf2_t test___riscv_vwaddu_wx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32mf2_tum(mask,merge,op1,0xAA,31); +} + + +vuint32m1_t test___riscv_vwaddu_wx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m1_tum(mask,merge,op1,0xAA,31); +} + + +vuint32m2_t test___riscv_vwaddu_wx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m2_tum(mask,merge,op1,0xAA,31); +} + + +vuint32m4_t test___riscv_vwaddu_wx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m4_tum(mask,merge,op1,0xAA,31); +} + + +vuint32m8_t test___riscv_vwaddu_wx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m8_tum(mask,merge,op1,0xAA,31); +} + + +vuint64m1_t test___riscv_vwaddu_wx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m1_tum(mask,merge,op1,0xAA,31); +} + + +vuint64m2_t test___riscv_vwaddu_wx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m2_tum(mask,merge,op1,0xAA,31); +} + + +vuint64m4_t test___riscv_vwaddu_wx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m4_tum(mask,merge,op1,0xAA,31); +} + + +vuint64m8_t test___riscv_vwaddu_wx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m8_tum(mask,merge,op1,0xAA,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tum-3.c new file mode 100644 index 00000000000..5ac42c096c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tum-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf4_tum(mask,merge,op1,0xAA,32); +} + + +vuint16mf2_t test___riscv_vwaddu_wx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf2_tum(mask,merge,op1,0xAA,32); +} + + +vuint16m1_t test___riscv_vwaddu_wx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m1_tum(mask,merge,op1,0xAA,32); +} + + +vuint16m2_t test___riscv_vwaddu_wx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m2_tum(mask,merge,op1,0xAA,32); +} + + +vuint16m4_t test___riscv_vwaddu_wx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m4_tum(mask,merge,op1,0xAA,32); +} + + +vuint16m8_t test___riscv_vwaddu_wx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m8_tum(mask,merge,op1,0xAA,32); +} + + +vuint32mf2_t test___riscv_vwaddu_wx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32mf2_tum(mask,merge,op1,0xAA,32); +} + + +vuint32m1_t test___riscv_vwaddu_wx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m1_tum(mask,merge,op1,0xAA,32); +} + + +vuint32m2_t test___riscv_vwaddu_wx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m2_tum(mask,merge,op1,0xAA,32); +} + + +vuint32m4_t test___riscv_vwaddu_wx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m4_tum(mask,merge,op1,0xAA,32); +} + + +vuint32m8_t test___riscv_vwaddu_wx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m8_tum(mask,merge,op1,0xAA,32); +} + + +vuint64m1_t test___riscv_vwaddu_wx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m1_tum(mask,merge,op1,0xAA,32); +} + + +vuint64m2_t test___riscv_vwaddu_wx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m2_tum(mask,merge,op1,0xAA,32); +} + + +vuint64m4_t test___riscv_vwaddu_wx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m4_tum(mask,merge,op1,0xAA,32); +} + + +vuint64m8_t test___riscv_vwaddu_wx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m8_tum(mask,merge,op1,0xAA,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tumu-1.c new file mode 100644 index 00000000000..d991e90870e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tumu-1.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf4_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint16mf2_t test___riscv_vwaddu_wx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf2_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint16m1_t test___riscv_vwaddu_wx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m1_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint16m2_t test___riscv_vwaddu_wx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m2_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint16m4_t test___riscv_vwaddu_wx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m4_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint16m8_t test___riscv_vwaddu_wx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m8_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint32mf2_t test___riscv_vwaddu_wx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32mf2_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint32m1_t test___riscv_vwaddu_wx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m1_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint32m2_t test___riscv_vwaddu_wx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m2_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint32m4_t test___riscv_vwaddu_wx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m4_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint32m8_t test___riscv_vwaddu_wx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m8_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint64m1_t test___riscv_vwaddu_wx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m1_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint64m2_t test___riscv_vwaddu_wx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m2_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint64m4_t test___riscv_vwaddu_wx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m4_tumu(mask,merge,op1,0xAA,vl); +} + + +vuint64m8_t test___riscv_vwaddu_wx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m8_tumu(mask,merge,op1,0xAA,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tumu-2.c new file mode 100644 index 00000000000..0c6eb090644 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tumu-2.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf4_tumu(mask,merge,op1,0xAA,31); +} + + +vuint16mf2_t test___riscv_vwaddu_wx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf2_tumu(mask,merge,op1,0xAA,31); +} + + +vuint16m1_t test___riscv_vwaddu_wx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m1_tumu(mask,merge,op1,0xAA,31); +} + + +vuint16m2_t test___riscv_vwaddu_wx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m2_tumu(mask,merge,op1,0xAA,31); +} + + +vuint16m4_t test___riscv_vwaddu_wx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m4_tumu(mask,merge,op1,0xAA,31); +} + + +vuint16m8_t test___riscv_vwaddu_wx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m8_tumu(mask,merge,op1,0xAA,31); +} + + +vuint32mf2_t test___riscv_vwaddu_wx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32mf2_tumu(mask,merge,op1,0xAA,31); +} + + +vuint32m1_t test___riscv_vwaddu_wx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m1_tumu(mask,merge,op1,0xAA,31); +} + + +vuint32m2_t test___riscv_vwaddu_wx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m2_tumu(mask,merge,op1,0xAA,31); +} + + +vuint32m4_t test___riscv_vwaddu_wx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m4_tumu(mask,merge,op1,0xAA,31); +} + + +vuint32m8_t test___riscv_vwaddu_wx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m8_tumu(mask,merge,op1,0xAA,31); +} + + +vuint64m1_t test___riscv_vwaddu_wx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m1_tumu(mask,merge,op1,0xAA,31); +} + + +vuint64m2_t test___riscv_vwaddu_wx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m2_tumu(mask,merge,op1,0xAA,31); +} + + +vuint64m4_t test___riscv_vwaddu_wx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m4_tumu(mask,merge,op1,0xAA,31); +} + + +vuint64m8_t test___riscv_vwaddu_wx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m8_tumu(mask,merge,op1,0xAA,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tumu-3.c new file mode 100644 index 00000000000..6606869da8c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwaddu_wx_tumu-3.c @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwaddu_wx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf4_tumu(mask,merge,op1,0xAA,32); +} + + +vuint16mf2_t test___riscv_vwaddu_wx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16mf2_tumu(mask,merge,op1,0xAA,32); +} + + +vuint16m1_t test___riscv_vwaddu_wx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m1_tumu(mask,merge,op1,0xAA,32); +} + + +vuint16m2_t test___riscv_vwaddu_wx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m2_tumu(mask,merge,op1,0xAA,32); +} + + +vuint16m4_t test___riscv_vwaddu_wx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m4_tumu(mask,merge,op1,0xAA,32); +} + + +vuint16m8_t test___riscv_vwaddu_wx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u16m8_tumu(mask,merge,op1,0xAA,32); +} + + +vuint32mf2_t test___riscv_vwaddu_wx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32mf2_tumu(mask,merge,op1,0xAA,32); +} + + +vuint32m1_t test___riscv_vwaddu_wx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m1_tumu(mask,merge,op1,0xAA,32); +} + + +vuint32m2_t test___riscv_vwaddu_wx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m2_tumu(mask,merge,op1,0xAA,32); +} + + +vuint32m4_t test___riscv_vwaddu_wx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m4_tumu(mask,merge,op1,0xAA,32); +} + + +vuint32m8_t test___riscv_vwaddu_wx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u32m8_tumu(mask,merge,op1,0xAA,32); +} + + +vuint64m1_t test___riscv_vwaddu_wx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m1_tumu(mask,merge,op1,0xAA,32); +} + + +vuint64m2_t test___riscv_vwaddu_wx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m2_tumu(mask,merge,op1,0xAA,32); +} + + +vuint64m4_t test___riscv_vwaddu_wx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m4_tumu(mask,merge,op1,0xAA,32); +} + + +vuint64m8_t test___riscv_vwaddu_wx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwaddu_wx_u64m8_tumu(mask,merge,op1,0xAA,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwaddu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */