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[58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 06 Feb 2023 20:55:52 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: 4YCIXoSNyy6WjPhkjoVVatlRYnUfwG4fpU+4U8vJQYcRgs1WllXjQ5sjBdQO3 xre0Z1+nTTvx1ibLHRtdbvjQ+DgtqQ/HS5/feGmu3rlY5sL0xxyxztBhEtAIkEJtTTxj1Fm qHgO7qtDEn2lWbo2XhC6X8NZYYUi//KoQaC5Xw26sOELxZ0VL+Fi4M/1UZJf/lYeK19iVmA dcFIlxhPJrOwWGBvpYv/8xp7CUKcfE5DUhL9GxT4J/cX/FKPYP2p7bk0/I3n9Bj5iCGktRO +7NAgkSAVbvTYQV74o729j3hckGtm6jMRzPIvrLe+PUcD/6IArDqsfeFdVV0LFctay9GsT8 GC8qSI69KdSKtkaytYtHGe5rBuUYsgJ8QTAtgryO7sbvPF99gHtEgbkckDr3+7fu/r5vRSb X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vmulhsu.vx C++ API tests Date: Mon, 6 Feb 2023 20:55:51 +0800 Message-Id: <20230206125551.89879-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-3.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_rv32-1.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_rv32-2.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_rv32-3.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_rv64-1.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_rv64-2.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_rv64-3.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-3.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-1.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-2.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-3.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-1.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-2.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-3.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-3.C: New test. --- .../riscv/rvv/base/vmulhsu_vx_mu_rv32-1.C | 157 +++++++++ .../riscv/rvv/base/vmulhsu_vx_mu_rv32-2.C | 157 +++++++++ .../riscv/rvv/base/vmulhsu_vx_mu_rv32-3.C | 157 +++++++++ .../riscv/rvv/base/vmulhsu_vx_mu_rv64-1.C | 160 +++++++++ .../riscv/rvv/base/vmulhsu_vx_mu_rv64-2.C | 160 +++++++++ .../riscv/rvv/base/vmulhsu_vx_mu_rv64-3.C | 160 +++++++++ .../riscv/rvv/base/vmulhsu_vx_rv32-1.C | 308 +++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_rv32-2.C | 308 +++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_rv32-3.C | 308 +++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_rv64-1.C | 314 ++++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_rv64-2.C | 314 ++++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_rv64-3.C | 314 ++++++++++++++++++ .../riscv/rvv/base/vmulhsu_vx_tu_rv32-1.C | 157 +++++++++ .../riscv/rvv/base/vmulhsu_vx_tu_rv32-2.C | 157 +++++++++ .../riscv/rvv/base/vmulhsu_vx_tu_rv32-3.C | 157 +++++++++ .../riscv/rvv/base/vmulhsu_vx_tu_rv64-1.C | 160 +++++++++ .../riscv/rvv/base/vmulhsu_vx_tu_rv64-2.C | 160 +++++++++ .../riscv/rvv/base/vmulhsu_vx_tu_rv64-3.C | 160 +++++++++ .../riscv/rvv/base/vmulhsu_vx_tum_rv32-1.C | 157 +++++++++ .../riscv/rvv/base/vmulhsu_vx_tum_rv32-2.C | 157 +++++++++ .../riscv/rvv/base/vmulhsu_vx_tum_rv32-3.C | 157 +++++++++ .../riscv/rvv/base/vmulhsu_vx_tum_rv64-1.C | 160 +++++++++ .../riscv/rvv/base/vmulhsu_vx_tum_rv64-2.C | 160 +++++++++ .../riscv/rvv/base/vmulhsu_vx_tum_rv64-3.C | 160 +++++++++ .../riscv/rvv/base/vmulhsu_vx_tumu_rv32-1.C | 157 +++++++++ .../riscv/rvv/base/vmulhsu_vx_tumu_rv32-2.C | 157 +++++++++ .../riscv/rvv/base/vmulhsu_vx_tumu_rv32-3.C | 157 +++++++++ .../riscv/rvv/base/vmulhsu_vx_tumu_rv64-1.C | 160 +++++++++ .../riscv/rvv/base/vmulhsu_vx_tumu_rv64-2.C | 160 +++++++++ .../riscv/rvv/base/vmulhsu_vx_tumu_rv64-3.C | 160 +++++++++ 30 files changed, 5670 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-3.C diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-1.C new file mode 100644 index 00000000000..50fba59af46 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-1.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-2.C new file mode 100644 index 00000000000..bb26e7420d1 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-2.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-3.C new file mode 100644 index 00000000000..14fa0917de6 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv32-3.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-1.C new file mode 100644 index 00000000000..d882f34f19d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-2.C new file mode 100644 index 00000000000..1e27032ee5a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-3.C new file mode 100644 index 00000000000..a85e843e461 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_mu_rv64-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-1.C new file mode 100644 index 00000000000..8d875f983e8 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-1.C @@ -0,0 +1,308 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu(vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu(vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu(vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu(vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu(vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu(vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu(vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu(vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu(vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu(vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu(vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu(vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu(vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu(vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu(vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu(vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu(vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu(vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu(vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu(vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu(vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu(vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint8mf8_t test___riscv_vmulhsu(vbool64_t mask,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu(vbool32_t mask,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu(vbool16_t mask,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu(vbool8_t mask,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu(vbool4_t mask,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu(vbool2_t mask,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu(vbool1_t mask,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu(vbool64_t mask,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu(vbool32_t mask,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu(vbool16_t mask,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu(vbool8_t mask,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu(vbool4_t mask,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu(vbool2_t mask,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu(vbool64_t mask,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu(vbool32_t mask,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu(vbool16_t mask,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu(vbool8_t mask,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu(vbool4_t mask,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu(vbool64_t mask,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu(vbool32_t mask,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu(vbool16_t mask,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu(vbool8_t mask,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-2.C new file mode 100644 index 00000000000..03feada95a1 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-2.C @@ -0,0 +1,308 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu(vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu(vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu(vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu(vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu(vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu(vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu(vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu(vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu(vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu(vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu(vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu(vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu(vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu(vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu(vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu(vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu(vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu(vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu(vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu(vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu(vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu(vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint8mf8_t test___riscv_vmulhsu(vbool64_t mask,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu(vbool32_t mask,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu(vbool16_t mask,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu(vbool8_t mask,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu(vbool4_t mask,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu(vbool2_t mask,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu(vbool1_t mask,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu(vbool64_t mask,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu(vbool32_t mask,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu(vbool16_t mask,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu(vbool8_t mask,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu(vbool4_t mask,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu(vbool2_t mask,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu(vbool64_t mask,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu(vbool32_t mask,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu(vbool16_t mask,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu(vbool8_t mask,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu(vbool4_t mask,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu(vbool64_t mask,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu(vbool32_t mask,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu(vbool16_t mask,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu(vbool8_t mask,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-3.C new file mode 100644 index 00000000000..4b3c876016b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv32-3.C @@ -0,0 +1,308 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu(vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu(vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu(vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu(vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu(vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu(vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu(vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu(vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu(vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu(vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu(vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu(vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu(vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu(vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu(vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu(vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu(vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu(vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu(vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu(vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu(vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu(vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint8mf8_t test___riscv_vmulhsu(vbool64_t mask,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu(vbool32_t mask,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu(vbool16_t mask,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu(vbool8_t mask,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu(vbool4_t mask,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu(vbool2_t mask,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu(vbool1_t mask,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu(vbool64_t mask,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu(vbool32_t mask,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu(vbool16_t mask,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu(vbool8_t mask,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu(vbool4_t mask,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu(vbool2_t mask,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu(vbool64_t mask,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu(vbool32_t mask,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu(vbool16_t mask,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu(vbool8_t mask,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu(vbool4_t mask,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu(vbool64_t mask,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu(vbool32_t mask,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu(vbool16_t mask,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu(vbool8_t mask,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-1.C new file mode 100644 index 00000000000..81c3b26e34f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-1.C @@ -0,0 +1,314 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu(vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu(vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu(vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu(vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu(vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu(vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu(vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu(vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu(vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu(vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu(vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu(vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu(vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu(vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu(vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu(vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu(vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu(vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu(vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu(vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu(vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu(vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,vl); +} + + +vint8mf8_t test___riscv_vmulhsu(vbool64_t mask,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu(vbool32_t mask,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu(vbool16_t mask,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu(vbool8_t mask,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu(vbool4_t mask,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu(vbool2_t mask,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu(vbool1_t mask,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu(vbool64_t mask,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu(vbool32_t mask,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu(vbool16_t mask,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu(vbool8_t mask,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu(vbool4_t mask,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu(vbool2_t mask,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu(vbool64_t mask,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu(vbool32_t mask,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu(vbool16_t mask,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu(vbool8_t mask,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu(vbool4_t mask,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu(vbool64_t mask,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu(vbool32_t mask,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu(vbool16_t mask,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu(vbool8_t mask,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-2.C new file mode 100644 index 00000000000..833d463bac2 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-2.C @@ -0,0 +1,314 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu(vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu(vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu(vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu(vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu(vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu(vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu(vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu(vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu(vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu(vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu(vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu(vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu(vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu(vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu(vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu(vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu(vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu(vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu(vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu(vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu(vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu(vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,31); +} + + +vint8mf8_t test___riscv_vmulhsu(vbool64_t mask,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu(vbool32_t mask,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu(vbool16_t mask,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu(vbool8_t mask,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu(vbool4_t mask,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu(vbool2_t mask,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu(vbool1_t mask,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu(vbool64_t mask,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu(vbool32_t mask,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu(vbool16_t mask,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu(vbool8_t mask,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu(vbool4_t mask,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu(vbool2_t mask,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu(vbool64_t mask,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu(vbool32_t mask,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu(vbool16_t mask,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu(vbool8_t mask,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu(vbool4_t mask,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu(vbool64_t mask,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu(vbool32_t mask,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu(vbool16_t mask,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu(vbool8_t mask,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-3.C new file mode 100644 index 00000000000..bb575d319eb --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_rv64-3.C @@ -0,0 +1,314 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu(vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu(vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu(vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu(vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu(vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu(vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu(vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu(vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu(vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu(vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu(vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu(vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu(vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu(vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu(vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu(vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu(vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu(vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu(vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu(vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu(vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu(vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(op1,op2,32); +} + + +vint8mf8_t test___riscv_vmulhsu(vbool64_t mask,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu(vbool32_t mask,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu(vbool16_t mask,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu(vbool8_t mask,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu(vbool4_t mask,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu(vbool2_t mask,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu(vbool1_t mask,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu(vbool64_t mask,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu(vbool32_t mask,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu(vbool16_t mask,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu(vbool8_t mask,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu(vbool4_t mask,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu(vbool2_t mask,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu(vbool64_t mask,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu(vbool32_t mask,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu(vbool16_t mask,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu(vbool8_t mask,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu(vbool4_t mask,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu(vbool64_t mask,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu(vbool32_t mask,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu(vbool16_t mask,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu(vbool8_t mask,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-1.C new file mode 100644 index 00000000000..febe18d4f0d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-1.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tu(vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu_tu(vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu_tu(vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu_tu(vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu_tu(vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu_tu(vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu_tu(vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu_tu(vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu_tu(vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu_tu(vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu_tu(vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu_tu(vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu_tu(vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu_tu(vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu_tu(vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu_tu(vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu_tu(vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu_tu(vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu_tu(vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu_tu(vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu_tu(vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu_tu(vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-2.C new file mode 100644 index 00000000000..672533c682a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-2.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tu(vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu_tu(vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu_tu(vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu_tu(vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu_tu(vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu_tu(vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu_tu(vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu_tu(vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu_tu(vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu_tu(vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu_tu(vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu_tu(vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu_tu(vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu_tu(vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu_tu(vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu_tu(vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu_tu(vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu_tu(vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu_tu(vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu_tu(vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu_tu(vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu_tu(vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-3.C new file mode 100644 index 00000000000..cd46ef1f6aa --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv32-3.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tu(vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu_tu(vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu_tu(vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu_tu(vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu_tu(vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu_tu(vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu_tu(vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu_tu(vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu_tu(vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu_tu(vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu_tu(vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu_tu(vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu_tu(vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu_tu(vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu_tu(vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu_tu(vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu_tu(vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu_tu(vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu_tu(vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu_tu(vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu_tu(vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu_tu(vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-1.C new file mode 100644 index 00000000000..329a188285d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tu(vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu_tu(vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu_tu(vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu_tu(vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu_tu(vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu_tu(vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu_tu(vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu_tu(vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu_tu(vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu_tu(vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu_tu(vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu_tu(vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu_tu(vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu_tu(vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu_tu(vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu_tu(vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu_tu(vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu_tu(vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu_tu(vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu_tu(vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu_tu(vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu_tu(vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-2.C new file mode 100644 index 00000000000..43dfe69f897 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tu(vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu_tu(vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu_tu(vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu_tu(vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu_tu(vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu_tu(vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu_tu(vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu_tu(vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu_tu(vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu_tu(vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu_tu(vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu_tu(vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu_tu(vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu_tu(vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu_tu(vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu_tu(vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu_tu(vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu_tu(vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu_tu(vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu_tu(vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu_tu(vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu_tu(vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-3.C new file mode 100644 index 00000000000..66df249ce3d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tu_rv64-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tu(vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu_tu(vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu_tu(vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu_tu(vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu_tu(vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu_tu(vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu_tu(vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu_tu(vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu_tu(vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu_tu(vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu_tu(vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu_tu(vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu_tu(vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu_tu(vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu_tu(vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu_tu(vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu_tu(vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu_tu(vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu_tu(vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu_tu(vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu_tu(vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu_tu(vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-1.C new file mode 100644 index 00000000000..430b18b10c8 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-1.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-2.C new file mode 100644 index 00000000000..0ddf21a6e0a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-2.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-3.C new file mode 100644 index 00000000000..ab8a2ed74b9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv32-3.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-1.C new file mode 100644 index 00000000000..52942c45a68 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-2.C new file mode 100644 index 00000000000..5dbd3b35e07 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-3.C new file mode 100644 index 00000000000..80d6565ff64 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tum_rv64-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-1.C new file mode 100644 index 00000000000..2c6cf9ca1e6 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-1.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-2.C new file mode 100644 index 00000000000..f3fec8af9c6 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-2.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-3.C new file mode 100644 index 00000000000..edbcb78e19a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv32-3.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vmulhsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-1.C new file mode 100644 index 00000000000..d3ffc1f3e4a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vmulhsu_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-2.C new file mode 100644 index 00000000000..1aa19f2b51f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vmulhsu_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-3.C new file mode 100644 index 00000000000..8c73d15b76d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmulhsu_vx_tumu_rv64-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vmulhsu_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vmulhsu_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vmulhsu_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vmulhsu_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vmulhsu_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vmulhsu_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vmulhsu_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vmulhsu_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vmulhsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */