From patchwork Mon Feb 6 05:24:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?6ZKf5bGF5ZOy?= X-Patchwork-Id: 64341 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5D5343857007 for ; Mon, 6 Feb 2023 05:24:58 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg151.qq.com (smtpbg151.qq.com [18.169.211.239]) by sourceware.org (Postfix) with ESMTPS id BEFA83858D1E for ; Mon, 6 Feb 2023 05:24:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BEFA83858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp81t1675661071t61g1c6x Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 06 Feb 2023 13:24:30 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: udNu8hCIBuSGbB8v53VsAekVAPu4Mju4WQ8CjzfOUggJAYNTSTQQknnvPAyOD WkMtDpuaK0JhSVglTJJsr3ge0Pc7g0xeKKSvxNuJSIQFv6QFo40AU2kNAv7LIQsCgdb3cPs VVsfyIQQqrKPMVkVBz+IqtED8IfnJhsCOKDV2Qatyw8esIXi9oy98cdrnBTRU+AQxiD6tSY OSiEhkfP3PqWgwaFmWQdmTeKNdH0Z5PWbzkiHafyrwWrKbarI0kB8LqO1zQVyf0Bg9bZhVB vQxqlbR+1UvYnfjzBGcXk/fu7plYy/nCxOewKc9bbd/UciCUXDZWBtyUwrBBo+5xavs53Z6 N2ptMERaYODGIO9KKIvH0zuzVTf5WkYCh3dPxgfdI3FShyL1Jg2koxQcCOQGA== X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vzext.vf2 C++ API tests Date: Mon, 6 Feb 2023 13:24:29 +0800 Message-Id: <20230206052429.234436-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vzext_vf2-1.C: New test. * g++.target/riscv/rvv/base/vzext_vf2-2.C: New test. * g++.target/riscv/rvv/base/vzext_vf2-3.C: New test. * g++.target/riscv/rvv/base/vzext_vf2_mu-1.C: New test. * g++.target/riscv/rvv/base/vzext_vf2_mu-2.C: New test. * g++.target/riscv/rvv/base/vzext_vf2_mu-3.C: New test. * g++.target/riscv/rvv/base/vzext_vf2_tu-1.C: New test. * g++.target/riscv/rvv/base/vzext_vf2_tu-2.C: New test. * g++.target/riscv/rvv/base/vzext_vf2_tu-3.C: New test. * g++.target/riscv/rvv/base/vzext_vf2_tum-1.C: New test. * g++.target/riscv/rvv/base/vzext_vf2_tum-2.C: New test. * g++.target/riscv/rvv/base/vzext_vf2_tum-3.C: New test. * g++.target/riscv/rvv/base/vzext_vf2_tumu-1.C: New test. * g++.target/riscv/rvv/base/vzext_vf2_tumu-2.C: New test. * g++.target/riscv/rvv/base/vzext_vf2_tumu-3.C: New test. --- .../g++.target/riscv/rvv/base/vzext_vf2-1.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vzext_vf2-2.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vzext_vf2-3.C | 216 ++++++++++++++++++ .../riscv/rvv/base/vzext_vf2_mu-1.C | 111 +++++++++ .../riscv/rvv/base/vzext_vf2_mu-2.C | 111 +++++++++ .../riscv/rvv/base/vzext_vf2_mu-3.C | 111 +++++++++ .../riscv/rvv/base/vzext_vf2_tu-1.C | 111 +++++++++ .../riscv/rvv/base/vzext_vf2_tu-2.C | 111 +++++++++ .../riscv/rvv/base/vzext_vf2_tu-3.C | 111 +++++++++ .../riscv/rvv/base/vzext_vf2_tum-1.C | 111 +++++++++ .../riscv/rvv/base/vzext_vf2_tum-2.C | 111 +++++++++ .../riscv/rvv/base/vzext_vf2_tum-3.C | 111 +++++++++ .../riscv/rvv/base/vzext_vf2_tumu-1.C | 111 +++++++++ .../riscv/rvv/base/vzext_vf2_tumu-2.C | 111 +++++++++ .../riscv/rvv/base/vzext_vf2_tumu-3.C | 111 +++++++++ 15 files changed, 1980 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tumu-3.C diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-1.C new file mode 100644 index 00000000000..4e9c81cf87f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-1.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vzext_vf2(vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,vl); +} + + +vuint16mf2_t test___riscv_vzext_vf2(vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,vl); +} + + +vuint16m1_t test___riscv_vzext_vf2(vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,vl); +} + + +vuint16m2_t test___riscv_vzext_vf2(vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,vl); +} + + +vuint16m4_t test___riscv_vzext_vf2(vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,vl); +} + + +vuint16m8_t test___riscv_vzext_vf2(vuint8m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,vl); +} + + +vuint32mf2_t test___riscv_vzext_vf2(vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,vl); +} + + +vuint32m1_t test___riscv_vzext_vf2(vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,vl); +} + + +vuint32m2_t test___riscv_vzext_vf2(vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,vl); +} + + +vuint32m4_t test___riscv_vzext_vf2(vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,vl); +} + + +vuint32m8_t test___riscv_vzext_vf2(vuint16m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,vl); +} + + +vuint64m1_t test___riscv_vzext_vf2(vuint32mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf2(vuint32m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf2(vuint32m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf2(vuint32m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,vl); +} + + +vuint16mf4_t test___riscv_vzext_vf2(vbool64_t mask,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,vl); +} + + +vuint16mf2_t test___riscv_vzext_vf2(vbool32_t mask,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,vl); +} + + +vuint16m1_t test___riscv_vzext_vf2(vbool16_t mask,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,vl); +} + + +vuint16m2_t test___riscv_vzext_vf2(vbool8_t mask,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,vl); +} + + +vuint16m4_t test___riscv_vzext_vf2(vbool4_t mask,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,vl); +} + + +vuint16m8_t test___riscv_vzext_vf2(vbool2_t mask,vuint8m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,vl); +} + + +vuint32mf2_t test___riscv_vzext_vf2(vbool64_t mask,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,vl); +} + + +vuint32m1_t test___riscv_vzext_vf2(vbool32_t mask,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,vl); +} + + +vuint32m2_t test___riscv_vzext_vf2(vbool16_t mask,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,vl); +} + + +vuint32m4_t test___riscv_vzext_vf2(vbool8_t mask,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,vl); +} + + +vuint32m8_t test___riscv_vzext_vf2(vbool4_t mask,vuint16m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,vl); +} + + +vuint64m1_t test___riscv_vzext_vf2(vbool64_t mask,vuint32mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf2(vbool32_t mask,vuint32m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf2(vbool16_t mask,vuint32m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf2(vbool8_t mask,vuint32m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-2.C new file mode 100644 index 00000000000..13a0756d03e --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-2.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vzext_vf2(vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,31); +} + + +vuint16mf2_t test___riscv_vzext_vf2(vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,31); +} + + +vuint16m1_t test___riscv_vzext_vf2(vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,31); +} + + +vuint16m2_t test___riscv_vzext_vf2(vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,31); +} + + +vuint16m4_t test___riscv_vzext_vf2(vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,31); +} + + +vuint16m8_t test___riscv_vzext_vf2(vuint8m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,31); +} + + +vuint32mf2_t test___riscv_vzext_vf2(vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,31); +} + + +vuint32m1_t test___riscv_vzext_vf2(vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,31); +} + + +vuint32m2_t test___riscv_vzext_vf2(vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,31); +} + + +vuint32m4_t test___riscv_vzext_vf2(vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,31); +} + + +vuint32m8_t test___riscv_vzext_vf2(vuint16m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,31); +} + + +vuint64m1_t test___riscv_vzext_vf2(vuint32mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf2(vuint32m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf2(vuint32m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf2(vuint32m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,31); +} + + +vuint16mf4_t test___riscv_vzext_vf2(vbool64_t mask,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,31); +} + + +vuint16mf2_t test___riscv_vzext_vf2(vbool32_t mask,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,31); +} + + +vuint16m1_t test___riscv_vzext_vf2(vbool16_t mask,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,31); +} + + +vuint16m2_t test___riscv_vzext_vf2(vbool8_t mask,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,31); +} + + +vuint16m4_t test___riscv_vzext_vf2(vbool4_t mask,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,31); +} + + +vuint16m8_t test___riscv_vzext_vf2(vbool2_t mask,vuint8m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,31); +} + + +vuint32mf2_t test___riscv_vzext_vf2(vbool64_t mask,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,31); +} + + +vuint32m1_t test___riscv_vzext_vf2(vbool32_t mask,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,31); +} + + +vuint32m2_t test___riscv_vzext_vf2(vbool16_t mask,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,31); +} + + +vuint32m4_t test___riscv_vzext_vf2(vbool8_t mask,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,31); +} + + +vuint32m8_t test___riscv_vzext_vf2(vbool4_t mask,vuint16m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,31); +} + + +vuint64m1_t test___riscv_vzext_vf2(vbool64_t mask,vuint32mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf2(vbool32_t mask,vuint32m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf2(vbool16_t mask,vuint32m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf2(vbool8_t mask,vuint32m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-3.C new file mode 100644 index 00000000000..fdc37d18ee2 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2-3.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vzext_vf2(vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,32); +} + + +vuint16mf2_t test___riscv_vzext_vf2(vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,32); +} + + +vuint16m1_t test___riscv_vzext_vf2(vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,32); +} + + +vuint16m2_t test___riscv_vzext_vf2(vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,32); +} + + +vuint16m4_t test___riscv_vzext_vf2(vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,32); +} + + +vuint16m8_t test___riscv_vzext_vf2(vuint8m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,32); +} + + +vuint32mf2_t test___riscv_vzext_vf2(vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,32); +} + + +vuint32m1_t test___riscv_vzext_vf2(vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,32); +} + + +vuint32m2_t test___riscv_vzext_vf2(vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,32); +} + + +vuint32m4_t test___riscv_vzext_vf2(vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,32); +} + + +vuint32m8_t test___riscv_vzext_vf2(vuint16m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,32); +} + + +vuint64m1_t test___riscv_vzext_vf2(vuint32mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf2(vuint32m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf2(vuint32m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf2(vuint32m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2(op1,32); +} + + +vuint16mf4_t test___riscv_vzext_vf2(vbool64_t mask,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,32); +} + + +vuint16mf2_t test___riscv_vzext_vf2(vbool32_t mask,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,32); +} + + +vuint16m1_t test___riscv_vzext_vf2(vbool16_t mask,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,32); +} + + +vuint16m2_t test___riscv_vzext_vf2(vbool8_t mask,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,32); +} + + +vuint16m4_t test___riscv_vzext_vf2(vbool4_t mask,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,32); +} + + +vuint16m8_t test___riscv_vzext_vf2(vbool2_t mask,vuint8m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,32); +} + + +vuint32mf2_t test___riscv_vzext_vf2(vbool64_t mask,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,32); +} + + +vuint32m1_t test___riscv_vzext_vf2(vbool32_t mask,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,32); +} + + +vuint32m2_t test___riscv_vzext_vf2(vbool16_t mask,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,32); +} + + +vuint32m4_t test___riscv_vzext_vf2(vbool8_t mask,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,32); +} + + +vuint32m8_t test___riscv_vzext_vf2(vbool4_t mask,vuint16m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,32); +} + + +vuint64m1_t test___riscv_vzext_vf2(vbool64_t mask,vuint32mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf2(vbool32_t mask,vuint32m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf2(vbool16_t mask,vuint32m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf2(vbool8_t mask,vuint32m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2(mask,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_mu-1.C new file mode 100644 index 00000000000..fc136be7d95 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_mu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vzext_vf2_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,vl); +} + + +vuint16mf2_t test___riscv_vzext_vf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,vl); +} + + +vuint16m1_t test___riscv_vzext_vf2_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,vl); +} + + +vuint16m2_t test___riscv_vzext_vf2_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,vl); +} + + +vuint16m4_t test___riscv_vzext_vf2_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,vl); +} + + +vuint16m8_t test___riscv_vzext_vf2_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,vl); +} + + +vuint32mf2_t test___riscv_vzext_vf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,vl); +} + + +vuint32m1_t test___riscv_vzext_vf2_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,vl); +} + + +vuint32m2_t test___riscv_vzext_vf2_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,vl); +} + + +vuint32m4_t test___riscv_vzext_vf2_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,vl); +} + + +vuint32m8_t test___riscv_vzext_vf2_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,vl); +} + + +vuint64m1_t test___riscv_vzext_vf2_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf2_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf2_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf2_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_mu-2.C new file mode 100644 index 00000000000..08649144f7d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_mu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vzext_vf2_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,31); +} + + +vuint16mf2_t test___riscv_vzext_vf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,31); +} + + +vuint16m1_t test___riscv_vzext_vf2_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,31); +} + + +vuint16m2_t test___riscv_vzext_vf2_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,31); +} + + +vuint16m4_t test___riscv_vzext_vf2_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,31); +} + + +vuint16m8_t test___riscv_vzext_vf2_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,31); +} + + +vuint32mf2_t test___riscv_vzext_vf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,31); +} + + +vuint32m1_t test___riscv_vzext_vf2_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,31); +} + + +vuint32m2_t test___riscv_vzext_vf2_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,31); +} + + +vuint32m4_t test___riscv_vzext_vf2_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,31); +} + + +vuint32m8_t test___riscv_vzext_vf2_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,31); +} + + +vuint64m1_t test___riscv_vzext_vf2_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf2_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf2_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf2_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_mu-3.C new file mode 100644 index 00000000000..fceecc16742 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_mu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vzext_vf2_mu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,32); +} + + +vuint16mf2_t test___riscv_vzext_vf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,32); +} + + +vuint16m1_t test___riscv_vzext_vf2_mu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,32); +} + + +vuint16m2_t test___riscv_vzext_vf2_mu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,32); +} + + +vuint16m4_t test___riscv_vzext_vf2_mu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,32); +} + + +vuint16m8_t test___riscv_vzext_vf2_mu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,32); +} + + +vuint32mf2_t test___riscv_vzext_vf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,32); +} + + +vuint32m1_t test___riscv_vzext_vf2_mu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,32); +} + + +vuint32m2_t test___riscv_vzext_vf2_mu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,32); +} + + +vuint32m4_t test___riscv_vzext_vf2_mu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,32); +} + + +vuint32m8_t test___riscv_vzext_vf2_mu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,32); +} + + +vuint64m1_t test___riscv_vzext_vf2_mu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf2_mu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf2_mu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf2_mu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_mu(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tu-1.C new file mode 100644 index 00000000000..a01c708cf4d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vzext_vf2_tu(vuint16mf4_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,vl); +} + + +vuint16mf2_t test___riscv_vzext_vf2_tu(vuint16mf2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,vl); +} + + +vuint16m1_t test___riscv_vzext_vf2_tu(vuint16m1_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,vl); +} + + +vuint16m2_t test___riscv_vzext_vf2_tu(vuint16m2_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,vl); +} + + +vuint16m4_t test___riscv_vzext_vf2_tu(vuint16m4_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,vl); +} + + +vuint16m8_t test___riscv_vzext_vf2_tu(vuint16m8_t merge,vuint8m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,vl); +} + + +vuint32mf2_t test___riscv_vzext_vf2_tu(vuint32mf2_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,vl); +} + + +vuint32m1_t test___riscv_vzext_vf2_tu(vuint32m1_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,vl); +} + + +vuint32m2_t test___riscv_vzext_vf2_tu(vuint32m2_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,vl); +} + + +vuint32m4_t test___riscv_vzext_vf2_tu(vuint32m4_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,vl); +} + + +vuint32m8_t test___riscv_vzext_vf2_tu(vuint32m8_t merge,vuint16m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,vl); +} + + +vuint64m1_t test___riscv_vzext_vf2_tu(vuint64m1_t merge,vuint32mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf2_tu(vuint64m2_t merge,vuint32m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf2_tu(vuint64m4_t merge,vuint32m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf2_tu(vuint64m8_t merge,vuint32m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tu-2.C new file mode 100644 index 00000000000..cd76d77233f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vzext_vf2_tu(vuint16mf4_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,31); +} + + +vuint16mf2_t test___riscv_vzext_vf2_tu(vuint16mf2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,31); +} + + +vuint16m1_t test___riscv_vzext_vf2_tu(vuint16m1_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,31); +} + + +vuint16m2_t test___riscv_vzext_vf2_tu(vuint16m2_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,31); +} + + +vuint16m4_t test___riscv_vzext_vf2_tu(vuint16m4_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,31); +} + + +vuint16m8_t test___riscv_vzext_vf2_tu(vuint16m8_t merge,vuint8m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,31); +} + + +vuint32mf2_t test___riscv_vzext_vf2_tu(vuint32mf2_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,31); +} + + +vuint32m1_t test___riscv_vzext_vf2_tu(vuint32m1_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,31); +} + + +vuint32m2_t test___riscv_vzext_vf2_tu(vuint32m2_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,31); +} + + +vuint32m4_t test___riscv_vzext_vf2_tu(vuint32m4_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,31); +} + + +vuint32m8_t test___riscv_vzext_vf2_tu(vuint32m8_t merge,vuint16m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,31); +} + + +vuint64m1_t test___riscv_vzext_vf2_tu(vuint64m1_t merge,vuint32mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf2_tu(vuint64m2_t merge,vuint32m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf2_tu(vuint64m4_t merge,vuint32m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf2_tu(vuint64m8_t merge,vuint32m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tu-3.C new file mode 100644 index 00000000000..c33e78d47c2 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vzext_vf2_tu(vuint16mf4_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,32); +} + + +vuint16mf2_t test___riscv_vzext_vf2_tu(vuint16mf2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,32); +} + + +vuint16m1_t test___riscv_vzext_vf2_tu(vuint16m1_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,32); +} + + +vuint16m2_t test___riscv_vzext_vf2_tu(vuint16m2_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,32); +} + + +vuint16m4_t test___riscv_vzext_vf2_tu(vuint16m4_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,32); +} + + +vuint16m8_t test___riscv_vzext_vf2_tu(vuint16m8_t merge,vuint8m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,32); +} + + +vuint32mf2_t test___riscv_vzext_vf2_tu(vuint32mf2_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,32); +} + + +vuint32m1_t test___riscv_vzext_vf2_tu(vuint32m1_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,32); +} + + +vuint32m2_t test___riscv_vzext_vf2_tu(vuint32m2_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,32); +} + + +vuint32m4_t test___riscv_vzext_vf2_tu(vuint32m4_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,32); +} + + +vuint32m8_t test___riscv_vzext_vf2_tu(vuint32m8_t merge,vuint16m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,32); +} + + +vuint64m1_t test___riscv_vzext_vf2_tu(vuint64m1_t merge,vuint32mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf2_tu(vuint64m2_t merge,vuint32m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf2_tu(vuint64m4_t merge,vuint32m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf2_tu(vuint64m8_t merge,vuint32m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tu(merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tum-1.C new file mode 100644 index 00000000000..953e4a14eda --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tum-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vzext_vf2_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,vl); +} + + +vuint16mf2_t test___riscv_vzext_vf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,vl); +} + + +vuint16m1_t test___riscv_vzext_vf2_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,vl); +} + + +vuint16m2_t test___riscv_vzext_vf2_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,vl); +} + + +vuint16m4_t test___riscv_vzext_vf2_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,vl); +} + + +vuint16m8_t test___riscv_vzext_vf2_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,vl); +} + + +vuint32mf2_t test___riscv_vzext_vf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,vl); +} + + +vuint32m1_t test___riscv_vzext_vf2_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,vl); +} + + +vuint32m2_t test___riscv_vzext_vf2_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,vl); +} + + +vuint32m4_t test___riscv_vzext_vf2_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,vl); +} + + +vuint32m8_t test___riscv_vzext_vf2_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,vl); +} + + +vuint64m1_t test___riscv_vzext_vf2_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf2_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf2_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf2_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tum-2.C new file mode 100644 index 00000000000..4ef3abd0aca --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tum-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vzext_vf2_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,31); +} + + +vuint16mf2_t test___riscv_vzext_vf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,31); +} + + +vuint16m1_t test___riscv_vzext_vf2_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,31); +} + + +vuint16m2_t test___riscv_vzext_vf2_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,31); +} + + +vuint16m4_t test___riscv_vzext_vf2_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,31); +} + + +vuint16m8_t test___riscv_vzext_vf2_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,31); +} + + +vuint32mf2_t test___riscv_vzext_vf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,31); +} + + +vuint32m1_t test___riscv_vzext_vf2_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,31); +} + + +vuint32m2_t test___riscv_vzext_vf2_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,31); +} + + +vuint32m4_t test___riscv_vzext_vf2_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,31); +} + + +vuint32m8_t test___riscv_vzext_vf2_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,31); +} + + +vuint64m1_t test___riscv_vzext_vf2_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf2_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf2_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf2_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tum-3.C new file mode 100644 index 00000000000..8bc1c93bbac --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tum-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vzext_vf2_tum(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,32); +} + + +vuint16mf2_t test___riscv_vzext_vf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,32); +} + + +vuint16m1_t test___riscv_vzext_vf2_tum(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,32); +} + + +vuint16m2_t test___riscv_vzext_vf2_tum(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,32); +} + + +vuint16m4_t test___riscv_vzext_vf2_tum(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,32); +} + + +vuint16m8_t test___riscv_vzext_vf2_tum(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,32); +} + + +vuint32mf2_t test___riscv_vzext_vf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,32); +} + + +vuint32m1_t test___riscv_vzext_vf2_tum(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,32); +} + + +vuint32m2_t test___riscv_vzext_vf2_tum(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,32); +} + + +vuint32m4_t test___riscv_vzext_vf2_tum(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,32); +} + + +vuint32m8_t test___riscv_vzext_vf2_tum(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,32); +} + + +vuint64m1_t test___riscv_vzext_vf2_tum(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf2_tum(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf2_tum(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf2_tum(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tum(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tumu-1.C new file mode 100644 index 00000000000..febc64c5b3a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tumu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vzext_vf2_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,vl); +} + + +vuint16mf2_t test___riscv_vzext_vf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,vl); +} + + +vuint16m1_t test___riscv_vzext_vf2_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,vl); +} + + +vuint16m2_t test___riscv_vzext_vf2_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,vl); +} + + +vuint16m4_t test___riscv_vzext_vf2_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,vl); +} + + +vuint16m8_t test___riscv_vzext_vf2_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,vl); +} + + +vuint32mf2_t test___riscv_vzext_vf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,vl); +} + + +vuint32m1_t test___riscv_vzext_vf2_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,vl); +} + + +vuint32m2_t test___riscv_vzext_vf2_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,vl); +} + + +vuint32m4_t test___riscv_vzext_vf2_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,vl); +} + + +vuint32m8_t test___riscv_vzext_vf2_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,vl); +} + + +vuint64m1_t test___riscv_vzext_vf2_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf2_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf2_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf2_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tumu-2.C new file mode 100644 index 00000000000..ba33ba5b227 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tumu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vzext_vf2_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,31); +} + + +vuint16mf2_t test___riscv_vzext_vf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,31); +} + + +vuint16m1_t test___riscv_vzext_vf2_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,31); +} + + +vuint16m2_t test___riscv_vzext_vf2_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,31); +} + + +vuint16m4_t test___riscv_vzext_vf2_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,31); +} + + +vuint16m8_t test___riscv_vzext_vf2_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,31); +} + + +vuint32mf2_t test___riscv_vzext_vf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,31); +} + + +vuint32m1_t test___riscv_vzext_vf2_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,31); +} + + +vuint32m2_t test___riscv_vzext_vf2_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,31); +} + + +vuint32m4_t test___riscv_vzext_vf2_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,31); +} + + +vuint32m8_t test___riscv_vzext_vf2_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,31); +} + + +vuint64m1_t test___riscv_vzext_vf2_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf2_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf2_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf2_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tumu-3.C new file mode 100644 index 00000000000..d8b8b77f207 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf2_tumu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vzext_vf2_tumu(vbool64_t mask,vuint16mf4_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,32); +} + + +vuint16mf2_t test___riscv_vzext_vf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,32); +} + + +vuint16m1_t test___riscv_vzext_vf2_tumu(vbool16_t mask,vuint16m1_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,32); +} + + +vuint16m2_t test___riscv_vzext_vf2_tumu(vbool8_t mask,vuint16m2_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,32); +} + + +vuint16m4_t test___riscv_vzext_vf2_tumu(vbool4_t mask,vuint16m4_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,32); +} + + +vuint16m8_t test___riscv_vzext_vf2_tumu(vbool2_t mask,vuint16m8_t merge,vuint8m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,32); +} + + +vuint32mf2_t test___riscv_vzext_vf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,32); +} + + +vuint32m1_t test___riscv_vzext_vf2_tumu(vbool32_t mask,vuint32m1_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,32); +} + + +vuint32m2_t test___riscv_vzext_vf2_tumu(vbool16_t mask,vuint32m2_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,32); +} + + +vuint32m4_t test___riscv_vzext_vf2_tumu(vbool8_t mask,vuint32m4_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,32); +} + + +vuint32m8_t test___riscv_vzext_vf2_tumu(vbool4_t mask,vuint32m8_t merge,vuint16m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,32); +} + + +vuint64m1_t test___riscv_vzext_vf2_tumu(vbool64_t mask,vuint64m1_t merge,vuint32mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf2_tumu(vbool32_t mask,vuint64m2_t merge,vuint32m1_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf2_tumu(vbool16_t mask,vuint64m4_t merge,vuint32m2_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf2_tumu(vbool8_t mask,vuint64m8_t merge,vuint32m4_t op1,size_t vl) +{ + return __riscv_vzext_vf2_tumu(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vzext\.vf2\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */