From patchwork Mon Feb 6 05:23:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 64340 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 170043857365 for ; Mon, 6 Feb 2023 05:23:54 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast3.qq.com (smtpbguseast3.qq.com [54.243.244.52]) by sourceware.org (Postfix) with ESMTPS id D19DF3858D1E for ; Mon, 6 Feb 2023 05:23:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D19DF3858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp71t1675661008tf4plu9a Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 06 Feb 2023 13:23:28 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: rZJGTgY0+YOUXIZHx+70mhj9I0bbeRGiIUWlYkWk3tyS1fm7jjlrp0Zb2R+1z p/pcSdQszPe13HENNYxGTzIdpF2kYIwEp0d/0i4enYobRrjb+EXmRL9nH0J6ZUBZuDxX9uT hX19KTW3O7Y1uh77cupx/zKxxzRtzedY+maZrmQnq5rvmP4IVLHcTmbZC651aRcg1RIOQpm OoCVZyAc9L7DT9D8dyNytfHzPjTsq96WvBforqmY3AV/xkRv0FTu94/5vkN46rqc0fqBJxT WXls/byZIBLK9VTyIzIzHjRaQkMHMCR7IJgo4MD3PFv+Aoi+yiE+pfwnN/Yv8TATPof2ub3 PqPCvp1vd1SRRrTHdfQiWCuNI7ksO+WSVJNacKJ3iI7V29s718iTUkGmX3q210u2K28xy7b X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vzext.vf4 C++ API tests Date: Mon, 6 Feb 2023 13:23:27 +0800 Message-Id: <20230206052327.233617-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vzext_vf4-1.C: New test. * g++.target/riscv/rvv/base/vzext_vf4-2.C: New test. * g++.target/riscv/rvv/base/vzext_vf4-3.C: New test. * g++.target/riscv/rvv/base/vzext_vf4_mu-1.C: New test. * g++.target/riscv/rvv/base/vzext_vf4_mu-2.C: New test. * g++.target/riscv/rvv/base/vzext_vf4_mu-3.C: New test. * g++.target/riscv/rvv/base/vzext_vf4_tu-1.C: New test. * g++.target/riscv/rvv/base/vzext_vf4_tu-2.C: New test. * g++.target/riscv/rvv/base/vzext_vf4_tu-3.C: New test. * g++.target/riscv/rvv/base/vzext_vf4_tum-1.C: New test. * g++.target/riscv/rvv/base/vzext_vf4_tum-2.C: New test. * g++.target/riscv/rvv/base/vzext_vf4_tum-3.C: New test. * g++.target/riscv/rvv/base/vzext_vf4_tumu-1.C: New test. * g++.target/riscv/rvv/base/vzext_vf4_tumu-2.C: New test. * g++.target/riscv/rvv/base/vzext_vf4_tumu-3.C: New test. --- .../g++.target/riscv/rvv/base/vzext_vf4-1.C | 132 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vzext_vf4-2.C | 132 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vzext_vf4-3.C | 132 ++++++++++++++++++ .../riscv/rvv/base/vzext_vf4_mu-1.C | 69 +++++++++ .../riscv/rvv/base/vzext_vf4_mu-2.C | 69 +++++++++ .../riscv/rvv/base/vzext_vf4_mu-3.C | 69 +++++++++ .../riscv/rvv/base/vzext_vf4_tu-1.C | 69 +++++++++ .../riscv/rvv/base/vzext_vf4_tu-2.C | 69 +++++++++ .../riscv/rvv/base/vzext_vf4_tu-3.C | 69 +++++++++ .../riscv/rvv/base/vzext_vf4_tum-1.C | 69 +++++++++ .../riscv/rvv/base/vzext_vf4_tum-2.C | 69 +++++++++ .../riscv/rvv/base/vzext_vf4_tum-3.C | 69 +++++++++ .../riscv/rvv/base/vzext_vf4_tumu-1.C | 69 +++++++++ .../riscv/rvv/base/vzext_vf4_tumu-2.C | 69 +++++++++ .../riscv/rvv/base/vzext_vf4_tumu-3.C | 69 +++++++++ 15 files changed, 1224 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tumu-3.C diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4-1.C new file mode 100644 index 00000000000..5875271fa88 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4-1.C @@ -0,0 +1,132 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4(vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,vl); +} + + +vuint32m1_t test___riscv_vzext_vf4(vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,vl); +} + + +vuint32m2_t test___riscv_vzext_vf4(vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,vl); +} + + +vuint32m4_t test___riscv_vzext_vf4(vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,vl); +} + + +vuint32m8_t test___riscv_vzext_vf4(vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,vl); +} + + +vuint64m1_t test___riscv_vzext_vf4(vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf4(vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf4(vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf4(vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,vl); +} + + +vuint32mf2_t test___riscv_vzext_vf4(vbool64_t mask,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,vl); +} + + +vuint32m1_t test___riscv_vzext_vf4(vbool32_t mask,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,vl); +} + + +vuint32m2_t test___riscv_vzext_vf4(vbool16_t mask,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,vl); +} + + +vuint32m4_t test___riscv_vzext_vf4(vbool8_t mask,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,vl); +} + + +vuint32m8_t test___riscv_vzext_vf4(vbool4_t mask,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,vl); +} + + +vuint64m1_t test___riscv_vzext_vf4(vbool64_t mask,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf4(vbool32_t mask,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf4(vbool16_t mask,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf4(vbool8_t mask,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4-2.C new file mode 100644 index 00000000000..27022784040 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4-2.C @@ -0,0 +1,132 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4(vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,31); +} + + +vuint32m1_t test___riscv_vzext_vf4(vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,31); +} + + +vuint32m2_t test___riscv_vzext_vf4(vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,31); +} + + +vuint32m4_t test___riscv_vzext_vf4(vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,31); +} + + +vuint32m8_t test___riscv_vzext_vf4(vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,31); +} + + +vuint64m1_t test___riscv_vzext_vf4(vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf4(vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf4(vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf4(vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,31); +} + + +vuint32mf2_t test___riscv_vzext_vf4(vbool64_t mask,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,31); +} + + +vuint32m1_t test___riscv_vzext_vf4(vbool32_t mask,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,31); +} + + +vuint32m2_t test___riscv_vzext_vf4(vbool16_t mask,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,31); +} + + +vuint32m4_t test___riscv_vzext_vf4(vbool8_t mask,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,31); +} + + +vuint32m8_t test___riscv_vzext_vf4(vbool4_t mask,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,31); +} + + +vuint64m1_t test___riscv_vzext_vf4(vbool64_t mask,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf4(vbool32_t mask,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf4(vbool16_t mask,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf4(vbool8_t mask,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4-3.C new file mode 100644 index 00000000000..a7f36a35cfb --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4-3.C @@ -0,0 +1,132 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4(vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,32); +} + + +vuint32m1_t test___riscv_vzext_vf4(vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,32); +} + + +vuint32m2_t test___riscv_vzext_vf4(vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,32); +} + + +vuint32m4_t test___riscv_vzext_vf4(vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,32); +} + + +vuint32m8_t test___riscv_vzext_vf4(vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,32); +} + + +vuint64m1_t test___riscv_vzext_vf4(vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf4(vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf4(vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf4(vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(op1,32); +} + + +vuint32mf2_t test___riscv_vzext_vf4(vbool64_t mask,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,32); +} + + +vuint32m1_t test___riscv_vzext_vf4(vbool32_t mask,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,32); +} + + +vuint32m2_t test___riscv_vzext_vf4(vbool16_t mask,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,32); +} + + +vuint32m4_t test___riscv_vzext_vf4(vbool8_t mask,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,32); +} + + +vuint32m8_t test___riscv_vzext_vf4(vbool4_t mask,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,32); +} + + +vuint64m1_t test___riscv_vzext_vf4(vbool64_t mask,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf4(vbool32_t mask,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf4(vbool16_t mask,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf4(vbool8_t mask,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4(mask,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_mu-1.C new file mode 100644 index 00000000000..1692dfbdbee --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_mu-1.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_mu(vbool64_t mask,vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,vl); +} + + +vuint32m1_t test___riscv_vzext_vf4_mu(vbool32_t mask,vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,vl); +} + + +vuint32m2_t test___riscv_vzext_vf4_mu(vbool16_t mask,vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,vl); +} + + +vuint32m4_t test___riscv_vzext_vf4_mu(vbool8_t mask,vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,vl); +} + + +vuint32m8_t test___riscv_vzext_vf4_mu(vbool4_t mask,vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,vl); +} + + +vuint64m1_t test___riscv_vzext_vf4_mu(vbool64_t mask,vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf4_mu(vbool32_t mask,vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf4_mu(vbool16_t mask,vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf4_mu(vbool8_t mask,vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_mu-2.C new file mode 100644 index 00000000000..98dc58d13a3 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_mu-2.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_mu(vbool64_t mask,vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,31); +} + + +vuint32m1_t test___riscv_vzext_vf4_mu(vbool32_t mask,vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,31); +} + + +vuint32m2_t test___riscv_vzext_vf4_mu(vbool16_t mask,vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,31); +} + + +vuint32m4_t test___riscv_vzext_vf4_mu(vbool8_t mask,vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,31); +} + + +vuint32m8_t test___riscv_vzext_vf4_mu(vbool4_t mask,vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,31); +} + + +vuint64m1_t test___riscv_vzext_vf4_mu(vbool64_t mask,vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf4_mu(vbool32_t mask,vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf4_mu(vbool16_t mask,vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf4_mu(vbool8_t mask,vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_mu-3.C new file mode 100644 index 00000000000..2c205ef5c5e --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_mu-3.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_mu(vbool64_t mask,vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,32); +} + + +vuint32m1_t test___riscv_vzext_vf4_mu(vbool32_t mask,vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,32); +} + + +vuint32m2_t test___riscv_vzext_vf4_mu(vbool16_t mask,vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,32); +} + + +vuint32m4_t test___riscv_vzext_vf4_mu(vbool8_t mask,vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,32); +} + + +vuint32m8_t test___riscv_vzext_vf4_mu(vbool4_t mask,vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,32); +} + + +vuint64m1_t test___riscv_vzext_vf4_mu(vbool64_t mask,vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf4_mu(vbool32_t mask,vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf4_mu(vbool16_t mask,vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf4_mu(vbool8_t mask,vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_mu(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tu-1.C new file mode 100644 index 00000000000..e37164c9b00 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tu-1.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_tu(vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,vl); +} + + +vuint32m1_t test___riscv_vzext_vf4_tu(vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,vl); +} + + +vuint32m2_t test___riscv_vzext_vf4_tu(vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,vl); +} + + +vuint32m4_t test___riscv_vzext_vf4_tu(vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,vl); +} + + +vuint32m8_t test___riscv_vzext_vf4_tu(vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,vl); +} + + +vuint64m1_t test___riscv_vzext_vf4_tu(vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf4_tu(vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf4_tu(vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf4_tu(vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tu-2.C new file mode 100644 index 00000000000..c0ad6532478 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tu-2.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_tu(vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,31); +} + + +vuint32m1_t test___riscv_vzext_vf4_tu(vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,31); +} + + +vuint32m2_t test___riscv_vzext_vf4_tu(vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,31); +} + + +vuint32m4_t test___riscv_vzext_vf4_tu(vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,31); +} + + +vuint32m8_t test___riscv_vzext_vf4_tu(vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,31); +} + + +vuint64m1_t test___riscv_vzext_vf4_tu(vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf4_tu(vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf4_tu(vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf4_tu(vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tu-3.C new file mode 100644 index 00000000000..9534e557bea --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tu-3.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_tu(vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,32); +} + + +vuint32m1_t test___riscv_vzext_vf4_tu(vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,32); +} + + +vuint32m2_t test___riscv_vzext_vf4_tu(vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,32); +} + + +vuint32m4_t test___riscv_vzext_vf4_tu(vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,32); +} + + +vuint32m8_t test___riscv_vzext_vf4_tu(vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,32); +} + + +vuint64m1_t test___riscv_vzext_vf4_tu(vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf4_tu(vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf4_tu(vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf4_tu(vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tu(merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tum-1.C new file mode 100644 index 00000000000..e4cecb10784 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tum-1.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_tum(vbool64_t mask,vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,vl); +} + + +vuint32m1_t test___riscv_vzext_vf4_tum(vbool32_t mask,vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,vl); +} + + +vuint32m2_t test___riscv_vzext_vf4_tum(vbool16_t mask,vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,vl); +} + + +vuint32m4_t test___riscv_vzext_vf4_tum(vbool8_t mask,vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,vl); +} + + +vuint32m8_t test___riscv_vzext_vf4_tum(vbool4_t mask,vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,vl); +} + + +vuint64m1_t test___riscv_vzext_vf4_tum(vbool64_t mask,vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf4_tum(vbool32_t mask,vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf4_tum(vbool16_t mask,vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf4_tum(vbool8_t mask,vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tum-2.C new file mode 100644 index 00000000000..ce6152107ea --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tum-2.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_tum(vbool64_t mask,vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,31); +} + + +vuint32m1_t test___riscv_vzext_vf4_tum(vbool32_t mask,vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,31); +} + + +vuint32m2_t test___riscv_vzext_vf4_tum(vbool16_t mask,vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,31); +} + + +vuint32m4_t test___riscv_vzext_vf4_tum(vbool8_t mask,vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,31); +} + + +vuint32m8_t test___riscv_vzext_vf4_tum(vbool4_t mask,vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,31); +} + + +vuint64m1_t test___riscv_vzext_vf4_tum(vbool64_t mask,vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf4_tum(vbool32_t mask,vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf4_tum(vbool16_t mask,vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf4_tum(vbool8_t mask,vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tum-3.C new file mode 100644 index 00000000000..c688e2f0001 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tum-3.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_tum(vbool64_t mask,vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,32); +} + + +vuint32m1_t test___riscv_vzext_vf4_tum(vbool32_t mask,vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,32); +} + + +vuint32m2_t test___riscv_vzext_vf4_tum(vbool16_t mask,vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,32); +} + + +vuint32m4_t test___riscv_vzext_vf4_tum(vbool8_t mask,vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,32); +} + + +vuint32m8_t test___riscv_vzext_vf4_tum(vbool4_t mask,vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,32); +} + + +vuint64m1_t test___riscv_vzext_vf4_tum(vbool64_t mask,vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf4_tum(vbool32_t mask,vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf4_tum(vbool16_t mask,vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf4_tum(vbool8_t mask,vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tum(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tumu-1.C new file mode 100644 index 00000000000..6f462f555bb --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tumu-1.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_tumu(vbool64_t mask,vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,vl); +} + + +vuint32m1_t test___riscv_vzext_vf4_tumu(vbool32_t mask,vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,vl); +} + + +vuint32m2_t test___riscv_vzext_vf4_tumu(vbool16_t mask,vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,vl); +} + + +vuint32m4_t test___riscv_vzext_vf4_tumu(vbool8_t mask,vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,vl); +} + + +vuint32m8_t test___riscv_vzext_vf4_tumu(vbool4_t mask,vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,vl); +} + + +vuint64m1_t test___riscv_vzext_vf4_tumu(vbool64_t mask,vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,vl); +} + + +vuint64m2_t test___riscv_vzext_vf4_tumu(vbool32_t mask,vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,vl); +} + + +vuint64m4_t test___riscv_vzext_vf4_tumu(vbool16_t mask,vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,vl); +} + + +vuint64m8_t test___riscv_vzext_vf4_tumu(vbool8_t mask,vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tumu-2.C new file mode 100644 index 00000000000..87bf15b394f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tumu-2.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_tumu(vbool64_t mask,vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,31); +} + + +vuint32m1_t test___riscv_vzext_vf4_tumu(vbool32_t mask,vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,31); +} + + +vuint32m2_t test___riscv_vzext_vf4_tumu(vbool16_t mask,vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,31); +} + + +vuint32m4_t test___riscv_vzext_vf4_tumu(vbool8_t mask,vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,31); +} + + +vuint32m8_t test___riscv_vzext_vf4_tumu(vbool4_t mask,vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,31); +} + + +vuint64m1_t test___riscv_vzext_vf4_tumu(vbool64_t mask,vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,31); +} + + +vuint64m2_t test___riscv_vzext_vf4_tumu(vbool32_t mask,vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,31); +} + + +vuint64m4_t test___riscv_vzext_vf4_tumu(vbool16_t mask,vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,31); +} + + +vuint64m8_t test___riscv_vzext_vf4_tumu(vbool8_t mask,vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tumu-3.C new file mode 100644 index 00000000000..4c19699db2a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vzext_vf4_tumu-3.C @@ -0,0 +1,69 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint32mf2_t test___riscv_vzext_vf4_tumu(vbool64_t mask,vuint32mf2_t merge,vuint8mf8_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,32); +} + + +vuint32m1_t test___riscv_vzext_vf4_tumu(vbool32_t mask,vuint32m1_t merge,vuint8mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,32); +} + + +vuint32m2_t test___riscv_vzext_vf4_tumu(vbool16_t mask,vuint32m2_t merge,vuint8mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,32); +} + + +vuint32m4_t test___riscv_vzext_vf4_tumu(vbool8_t mask,vuint32m4_t merge,vuint8m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,32); +} + + +vuint32m8_t test___riscv_vzext_vf4_tumu(vbool4_t mask,vuint32m8_t merge,vuint8m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,32); +} + + +vuint64m1_t test___riscv_vzext_vf4_tumu(vbool64_t mask,vuint64m1_t merge,vuint16mf4_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,32); +} + + +vuint64m2_t test___riscv_vzext_vf4_tumu(vbool32_t mask,vuint64m2_t merge,vuint16mf2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,32); +} + + +vuint64m4_t test___riscv_vzext_vf4_tumu(vbool16_t mask,vuint64m4_t merge,vuint16m1_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,32); +} + + +vuint64m8_t test___riscv_vzext_vf4_tumu(vbool8_t mask,vuint64m8_t merge,vuint16m2_t op1,size_t vl) +{ + return __riscv_vzext_vf4_tumu(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vzext\.vf4\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */