From patchwork Sun Feb 5 01:50:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 64307 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 91AD13858D28 for ; Sun, 5 Feb 2023 01:51:45 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg151.qq.com (smtpbg151.qq.com [18.169.211.239]) by sourceware.org (Postfix) with ESMTPS id 5A1D83858D28 for ; Sun, 5 Feb 2023 01:50:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5A1D83858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp72t1675561833t4986vic Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Sun, 05 Feb 2023 09:50:32 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: qOAV9bwDT/mV0IVsmrbyUCMPRoXLaO4EjdPvQPmgXxuXJZmqfhCMG38vUYLA+ xRWKYU5tgERt8Hc2gsgyLrZTMgZ6bv5iBAbx5AWIQGEZ/ziayTfN5EqUXv1Ykv8RFewQesr FRzExwKqDQAouIuuorp4CZGPOZUhoyxAJ5UuQWT7Tir4zhnpoh42qMvRssA0iMpnHUZ6ncj E+up8rFP0i6Y6VcGNz2AFfluNtTb5/gAm08n/r0geTcqQggsbhHLQIKxd0PNxQHaPgVya5O h9k05SQw50MeA+zzo3skI+0KWRrjRZPqIa1DA5JR2G5JsavgucoGOIknZD+EhhBq6Fqz3BY oI1qIcBcoiqVhizb6wqHUJyf19GoiEP0t32wtFoL+irqHT8FJQ= X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add saturating Add && Sub vx constraint tests Date: Sun, 5 Feb 2023 09:50:31 +0800 Message-Id: <20230205015031.9176-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/binop_vx_constraint-100.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-101.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-102.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-103.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-104.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-105.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-106.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-107.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-108.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-109.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-110.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-111.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-112.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-113.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-114.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-115.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-116.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-117.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-118.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-119.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-97.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-98.c: New test. * gcc.target/riscv/rvv/base/binop_vx_constraint-99.c: New test. --- .../riscv/rvv/base/binop_vx_constraint-100.c | 16 +++ .../riscv/rvv/base/binop_vx_constraint-101.c | 16 +++ .../riscv/rvv/base/binop_vx_constraint-102.c | 18 +++ .../riscv/rvv/base/binop_vx_constraint-103.c | 123 ++++++++++++++++++ .../riscv/rvv/base/binop_vx_constraint-104.c | 72 ++++++++++ .../riscv/rvv/base/binop_vx_constraint-105.c | 16 +++ .../riscv/rvv/base/binop_vx_constraint-106.c | 16 +++ .../riscv/rvv/base/binop_vx_constraint-107.c | 16 +++ .../riscv/rvv/base/binop_vx_constraint-108.c | 18 +++ .../riscv/rvv/base/binop_vx_constraint-109.c | 123 ++++++++++++++++++ .../riscv/rvv/base/binop_vx_constraint-110.c | 72 ++++++++++ .../riscv/rvv/base/binop_vx_constraint-111.c | 16 +++ .../riscv/rvv/base/binop_vx_constraint-112.c | 16 +++ .../riscv/rvv/base/binop_vx_constraint-113.c | 16 +++ .../riscv/rvv/base/binop_vx_constraint-114.c | 18 +++ .../riscv/rvv/base/binop_vx_constraint-115.c | 72 ++++++++++ .../riscv/rvv/base/binop_vx_constraint-116.c | 16 +++ .../riscv/rvv/base/binop_vx_constraint-117.c | 16 +++ .../riscv/rvv/base/binop_vx_constraint-118.c | 16 +++ .../riscv/rvv/base/binop_vx_constraint-119.c | 18 +++ .../riscv/rvv/base/binop_vx_constraint-97.c | 123 ++++++++++++++++++ .../riscv/rvv/base/binop_vx_constraint-98.c | 72 ++++++++++ .../riscv/rvv/base/binop_vx_constraint-99.c | 16 +++ 23 files changed, 921 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-100.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-101.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-103.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-104.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-105.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-106.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-107.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-109.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-110.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-111.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-112.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-113.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-115.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-116.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-117.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-118.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-97.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-98.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-99.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-100.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-100.c new file mode 100644 index 00000000000..667a7656ce1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-100.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4); + vint64m1_t v4 = __riscv_vsadd_vx_i64m1_tu (v3, v2, 0xAAAAAAAAAAAAAAAA, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {vsadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-101.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-101.c new file mode 100644 index 00000000000..eefdf455bca --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-101.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, x, 4); + vint64m1_t v4 = __riscv_vsadd_vx_i64m1_tu (v3, v2, x, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {vsadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c new file mode 100644 index 00000000000..4b24b971cba --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-102.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, int32_t x, int n) +{ + for (int i = 0; i < n; i++) { + vint64m1_t v = __riscv_vle64_v_i64m1 (in + i + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + i + 2, 4); + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, x, 4); + vint64m1_t v4 = __riscv_vsadd_vx_i64m1_tu (v3, v2, x, 4); + __riscv_vse64_v_i64m1 (out + i + 2, v4, 4); + } +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero\s+\.L[0-9]+\:\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-103.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-103.c new file mode 100644 index 00000000000..7ffedd5ceb9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-103.c @@ -0,0 +1,123 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f0: +** ... +** vsaddu\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** vsaddu\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** ... +** ret +*/ +void f0 (void * in, void *out, int64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, -16, 4); + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, -16, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* +** f1: +** ... +** vsaddu\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** vsaddu\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** ... +** ret +*/ +void f1 (void * in, void *out, int64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 15, 4); + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, 15, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* +** f2: +** ... +** vsaddu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vsaddu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f2 (void * in, void *out, int64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 16, 4); + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, 16, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* +** f3: +** ... +** vsaddu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vsaddu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f3 (void * in, void *out, int64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 0xAAAAAAAA, 4); + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, 0xAAAAAAAA, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* +** f4: +** ... +** vsaddu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vsaddu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f4 (void * in, void *out, int64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4); + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, 0xAAAAAAAAAAAAAAAA, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* +** f5: +** ... +** vsaddu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vsaddu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f5 (void * in, void *out, int64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4); + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, 0xAAAAAAAAAAAAAAAA, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* +** f6: +** ... +** vsaddu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vsaddu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f6 (void * in, void *out, int64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, x, 4); + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, x, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-104.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-104.c new file mode 100644 index 00000000000..612213a6036 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-104.c @@ -0,0 +1,72 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f0: +** ... +** vsaddu\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** vsaddu\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** ... +** ret +*/ +void f0 (void * in, void *out, int64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, -16, 4); + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, -16, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* +** f1: +** ... +** vsaddu\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** vsaddu\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** ... +** ret +*/ +void f1 (void * in, void *out, int64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 15, 4); + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, 15, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* +** f2: +** ... +** vsaddu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vsaddu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f2 (void * in, void *out, int64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 16, 4); + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, 16, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* +** f3: +** ... +** vsaddu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vsaddu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f3 (void * in, void *out, int64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 0xAAAAAAA, 4); + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1 (v3, 0xAAAAAAA, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-105.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-105.c new file mode 100644 index 00000000000..86825c088b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-105.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, int64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 0xAAAAAAAA, 4); + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1_tu (v3, v2, 0xAAAAAAAA, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-106.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-106.c new file mode 100644 index 00000000000..94bff68ba5e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-106.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, int64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4); + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1_tu (v3, v2, 0xAAAAAAAAAAAAAAAA, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-107.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-107.c new file mode 100644 index 00000000000..a3d08de06c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-107.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, int64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, x, 4); + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1_tu (v3, v2, x, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c new file mode 100644 index 00000000000..99acc51b4ff --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-108.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, int32_t x, int n) +{ + for (int i = 0; i < n; i++) { + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + i + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + i + 2, 4); + vuint64m1_t v3 = __riscv_vsaddu_vx_u64m1 (v2, x, 4); + vuint64m1_t v4 = __riscv_vsaddu_vx_u64m1_tu (v3, v2, x, 4); + __riscv_vse64_v_u64m1 (out + i + 2, v4, 4); + } +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero\s+\.L[0-9]+\:\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsaddu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-109.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-109.c new file mode 100644 index 00000000000..9127b869f53 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-109.c @@ -0,0 +1,123 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f0: +** ... +** vsadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** vsadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** ... +** ret +*/ +void f0 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, -15, 4); + vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, -15, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f1: +** ... +** vsadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** vsadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** ... +** ret +*/ +void f1 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 16, 4); + vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, 16, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f2: +** ... +** vssub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vssub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f2 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 17, 4); + vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, 17, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f3: +** ... +** vssub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vssub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f3 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 0xAAAAAAAA, 4); + vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, 0xAAAAAAAA, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f4: +** ... +** vssub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vssub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f4 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4); + vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, 0xAAAAAAAAAAAAAAAA, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f5: +** ... +** vssub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vssub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f5 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4); + vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, 0xAAAAAAAAAAAAAAAA, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f6: +** ... +** vssub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vssub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f6 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, x, 4); + vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, x, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-110.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-110.c new file mode 100644 index 00000000000..d70789e1810 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-110.c @@ -0,0 +1,72 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f0: +** ... +** vsadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** vsadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** ... +** ret +*/ +void f0 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, -15, 4); + vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, -15, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f1: +** ... +** vsadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** vsadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** ... +** ret +*/ +void f1 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 16, 4); + vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, 16, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f2: +** ... +** vssub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vssub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f2 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 17, 4); + vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, 17, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f3: +** ... +** vssub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vssub\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f3 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 0xAAAAAAA, 4); + vint64m1_t v4 = __riscv_vssub_vx_i64m1 (v3, 0xAAAAAAA, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-111.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-111.c new file mode 100644 index 00000000000..e02b21554a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-111.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 0xAAAAAAAA, 4); + vint64m1_t v4 = __riscv_vssub_vx_i64m1_tu (v3, v2, 0xAAAAAAAA, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-112.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-112.c new file mode 100644 index 00000000000..8cd9c4d09ba --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-112.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4); + vint64m1_t v4 = __riscv_vssub_vx_i64m1_tu (v3, v2, 0xAAAAAAAAAAAAAAAA, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-113.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-113.c new file mode 100644 index 00000000000..6090a1da69d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-113.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, x, 4); + vint64m1_t v4 = __riscv_vssub_vx_i64m1_tu (v3, v2, x, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c new file mode 100644 index 00000000000..d595c446503 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-114.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, int32_t x, int n) +{ + for (int i = 0; i < n; i++) { + vint64m1_t v = __riscv_vle64_v_i64m1 (in + i + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + i + 2, 4); + vint64m1_t v3 = __riscv_vssub_vx_i64m1 (v2, x, 4); + vint64m1_t v4 = __riscv_vssub_vx_i64m1_tu (v3, v2, x, 4); + __riscv_vse64_v_i64m1 (out + i + 2, v4, 4); + } +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero\s+\.L[0-9]+\:\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vssub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-115.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-115.c new file mode 100644 index 00000000000..9722f5e6118 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-115.c @@ -0,0 +1,72 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f0: +** ... +** vssubu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vssubu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f0 (void * in, void *out, uint64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, -16, 4); + vuint64m1_t v4 = __riscv_vssubu_vx_u64m1 (v3, -16, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* +** f1: +** ... +** vssubu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vssubu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f1 (void * in, void *out, uint64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, 15, 4); + vuint64m1_t v4 = __riscv_vssubu_vx_u64m1 (v3, 15, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* +** f2: +** ... +** vssubu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vssubu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f2 (void * in, void *out, uint64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, 16, 4); + vuint64m1_t v4 = __riscv_vssubu_vx_u64m1 (v3, 16, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* +** f3: +** ... +** vssubu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vssubu\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f3 (void * in, void *out, uint64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, 0xAAAAAAA, 4); + vuint64m1_t v4 = __riscv_vssubu_vx_u64m1 (v3, 0xAAAAAAA, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-116.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-116.c new file mode 100644 index 00000000000..066365dc744 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-116.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, uint64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, 0xAAAAAAAA, 4); + vuint64m1_t v4 = __riscv_vssubu_vx_u64m1_tu (v3, v2, 0xAAAAAAAA, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-117.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-117.c new file mode 100644 index 00000000000..bfc6773f198 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-117.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, uint64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4); + vuint64m1_t v4 = __riscv_vssubu_vx_u64m1_tu (v3, v2, 0xAAAAAAAAAAAAAAAA, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-118.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-118.c new file mode 100644 index 00000000000..05a7a1d9e65 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-118.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, uint64_t x, int n) +{ + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + 2, 4); + vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, x, 4); + vuint64m1_t v4 = __riscv_vssubu_vx_u64m1_tu (v3, v2, x, 4); + __riscv_vse64_v_u64m1 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c new file mode 100644 index 00000000000..0b51175f66c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-119.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, uint64_t x, int n) +{ + for (int i = 0; i < n; i++) { + vuint64m1_t v = __riscv_vle64_v_u64m1 (in + i + 1, 4); + vuint64m1_t v2 = __riscv_vle64_v_u64m1_tu (v, in + i + 2, 4); + vuint64m1_t v3 = __riscv_vssubu_vx_u64m1 (v2, x, 4); + vuint64m1_t v4 = __riscv_vssubu_vx_u64m1_tu (v3, v2, x, 4); + __riscv_vse64_v_u64m1 (out + i + 2, v4, 4); + } +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero\s+\.L[0-9]+\:\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vssubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-97.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-97.c new file mode 100644 index 00000000000..d1283d89a93 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-97.c @@ -0,0 +1,123 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f0: +** ... +** vsadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** vsadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** ... +** ret +*/ +void f0 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, -16, 4); + vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, -16, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f1: +** ... +** vsadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** vsadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** ... +** ret +*/ +void f1 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 15, 4); + vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, 15, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f2: +** ... +** vsadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vsadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f2 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 16, 4); + vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, 16, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f3: +** ... +** vsadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vsadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f3 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 0xAAAAAAAA, 4); + vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, 0xAAAAAAAA, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f4: +** ... +** vsadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vsadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f4 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4); + vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, 0xAAAAAAAAAAAAAAAA, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f5: +** ... +** vsadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vsadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f5 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 0xAAAAAAAAAAAAAAAA, 4); + vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, 0xAAAAAAAAAAAAAAAA, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f6: +** ... +** vsadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vsadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f6 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, x, 4); + vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, x, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-98.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-98.c new file mode 100644 index 00000000000..ed7477b3ca8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-98.c @@ -0,0 +1,72 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f0: +** ... +** vsadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** vsadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16 +** ... +** ret +*/ +void f0 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, -16, 4); + vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, -16, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f1: +** ... +** vsadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** vsadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*15 +** ... +** ret +*/ +void f1 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 15, 4); + vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, 15, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f2: +** ... +** vsadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vsadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f2 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 16, 4); + vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, 16, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* +** f3: +** ... +** vsadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** vsadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+ +** ... +** ret +*/ +void f3 (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vsadd_vx_i64m1 (v2, 0xAAAAAAA, 4); + vint64m1_t v4 = __riscv_vsadd_vx_i64m1 (v3, 0xAAAAAAA, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-99.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-99.c new file mode 100644 index 00000000000..5a4f58bfc1a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-99.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */ +#include "riscv_vector.h" + +void f (void * in, void *out, int64_t x, int n) +{ + vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4); + vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4); + vint64m1_t v3 = __riscv_vadd_vx_i64m1 (v2, 0xAAAAAAAA, 4); + vint64m1_t v4 = __riscv_vadd_vx_i64m1_tu (v3, v2, 0xAAAAAAAA, 4); + __riscv_vse64_v_i64m1 (out + 2, v4, 4); +} + +/* { dg-final { scan-assembler-times {vlse64\.v\s+v[0-9]+,\s*0\([a-x0-9]+\),\s*zero} 1 } } */ +/* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-not {vmv} } } */