From patchwork Fri Feb 3 23:26:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 64291 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9B7403838025 for ; Fri, 3 Feb 2023 23:27:15 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast3.qq.com (smtpbguseast3.qq.com [54.243.244.52]) by sourceware.org (Postfix) with ESMTPS id C4B393864812 for ; Fri, 3 Feb 2023 23:26:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C4B393864812 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp87t1675466804tis7cvlc Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Sat, 04 Feb 2023 07:26:43 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: Zre9CpKCW9PVNjSw0PtCPNPmeglE7yHdfLw6PZvoj/RLTVq9A09WsOMb35ppq jgfRzHtSmlbtNOBhb7BwIECzPPSBv7vOtPRyFnJPSjwK8G6Gz3J4eJsuy02lIMibdveBBRG mZAmQQ8LVRYkslS3n/eZB1a3h85KxUpYz6BMGBQIgRxx6zqWHC+FrPgLEm8LDsItki+klZb I6Gydle/3+5Au8m+SS6IBkjsQIRBtFme3OsVFECletSLOY8L+DaHaDT6PTF8cORcbxMvp6S 3AXMCNApXShdhHt8K6zYsFd2QHG+u5vV/kIbIlOH9fX9K/3ir0N9gCFyuLNWMaJ9gOwoyUo m368iCzBtRGby8QpW74fPE8kiq3EdwKfaMM4PIGj17cgn2H4hI= X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vnot.v C++ API tests Date: Sat, 4 Feb 2023 07:26:41 +0800 Message-Id: <20230203232641.224761-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vnot_v-1.C: New test. * g++.target/riscv/rvv/base/vnot_v-2.C: New test. * g++.target/riscv/rvv/base/vnot_v-3.C: New test. * g++.target/riscv/rvv/base/vnot_v_mu-1.C: New test. * g++.target/riscv/rvv/base/vnot_v_mu-2.C: New test. * g++.target/riscv/rvv/base/vnot_v_mu-3.C: New test. * g++.target/riscv/rvv/base/vnot_v_tu-1.C: New test. * g++.target/riscv/rvv/base/vnot_v_tu-2.C: New test. * g++.target/riscv/rvv/base/vnot_v_tu-3.C: New test. * g++.target/riscv/rvv/base/vnot_v_tum-1.C: New test. * g++.target/riscv/rvv/base/vnot_v_tum-2.C: New test. * g++.target/riscv/rvv/base/vnot_v_tum-3.C: New test. * g++.target/riscv/rvv/base/vnot_v_tumu-1.C: New test. * g++.target/riscv/rvv/base/vnot_v_tumu-2.C: New test. * g++.target/riscv/rvv/base/vnot_v_tumu-3.C: New test. --- .../g++.target/riscv/rvv/base/vnot_v-1.C | 314 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vnot_v-2.C | 314 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vnot_v-3.C | 314 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vnot_v_mu-1.C | 160 +++++++++ .../g++.target/riscv/rvv/base/vnot_v_mu-2.C | 160 +++++++++ .../g++.target/riscv/rvv/base/vnot_v_mu-3.C | 160 +++++++++ .../g++.target/riscv/rvv/base/vnot_v_tu-1.C | 160 +++++++++ .../g++.target/riscv/rvv/base/vnot_v_tu-2.C | 160 +++++++++ .../g++.target/riscv/rvv/base/vnot_v_tu-3.C | 160 +++++++++ .../g++.target/riscv/rvv/base/vnot_v_tum-1.C | 160 +++++++++ .../g++.target/riscv/rvv/base/vnot_v_tum-2.C | 160 +++++++++ .../g++.target/riscv/rvv/base/vnot_v_tum-3.C | 160 +++++++++ .../g++.target/riscv/rvv/base/vnot_v_tumu-1.C | 160 +++++++++ .../g++.target/riscv/rvv/base/vnot_v_tumu-2.C | 160 +++++++++ .../g++.target/riscv/rvv/base/vnot_v_tumu-3.C | 160 +++++++++ 15 files changed, 2862 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-3.C diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-1.C new file mode 100644 index 00000000000..23e6f92c8c9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-1.C @@ -0,0 +1,314 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnot(vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint8mf4_t test___riscv_vnot(vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint8mf2_t test___riscv_vnot(vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint8m1_t test___riscv_vnot(vint8m1_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint8m2_t test___riscv_vnot(vint8m2_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint8m4_t test___riscv_vnot(vint8m4_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint8m8_t test___riscv_vnot(vint8m8_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint16mf4_t test___riscv_vnot(vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint16mf2_t test___riscv_vnot(vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint16m1_t test___riscv_vnot(vint16m1_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint16m2_t test___riscv_vnot(vint16m2_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint16m4_t test___riscv_vnot(vint16m4_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint16m8_t test___riscv_vnot(vint16m8_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint32mf2_t test___riscv_vnot(vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint32m1_t test___riscv_vnot(vint32m1_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint32m2_t test___riscv_vnot(vint32m2_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint32m4_t test___riscv_vnot(vint32m4_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint32m8_t test___riscv_vnot(vint32m8_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint64m1_t test___riscv_vnot(vint64m1_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint64m2_t test___riscv_vnot(vint64m2_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint64m4_t test___riscv_vnot(vint64m4_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint64m8_t test___riscv_vnot(vint64m8_t op1,size_t vl) +{ + return __riscv_vnot(op1,vl); +} + + +vint8mf8_t test___riscv_vnot(vbool64_t mask,vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint8mf4_t test___riscv_vnot(vbool32_t mask,vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint8mf2_t test___riscv_vnot(vbool16_t mask,vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint8m1_t test___riscv_vnot(vbool8_t mask,vint8m1_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint8m2_t test___riscv_vnot(vbool4_t mask,vint8m2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint8m4_t test___riscv_vnot(vbool2_t mask,vint8m4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint8m8_t test___riscv_vnot(vbool1_t mask,vint8m8_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint16mf4_t test___riscv_vnot(vbool64_t mask,vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint16mf2_t test___riscv_vnot(vbool32_t mask,vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint16m1_t test___riscv_vnot(vbool16_t mask,vint16m1_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint16m2_t test___riscv_vnot(vbool8_t mask,vint16m2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint16m4_t test___riscv_vnot(vbool4_t mask,vint16m4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint16m8_t test___riscv_vnot(vbool2_t mask,vint16m8_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint32mf2_t test___riscv_vnot(vbool64_t mask,vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint32m1_t test___riscv_vnot(vbool32_t mask,vint32m1_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint32m2_t test___riscv_vnot(vbool16_t mask,vint32m2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint32m4_t test___riscv_vnot(vbool8_t mask,vint32m4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint32m8_t test___riscv_vnot(vbool4_t mask,vint32m8_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint64m1_t test___riscv_vnot(vbool64_t mask,vint64m1_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint64m2_t test___riscv_vnot(vbool32_t mask,vint64m2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint64m4_t test___riscv_vnot(vbool16_t mask,vint64m4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + +vint64m8_t test___riscv_vnot(vbool8_t mask,vint64m8_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-2.C new file mode 100644 index 00000000000..35426a06531 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-2.C @@ -0,0 +1,314 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnot(vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint8mf4_t test___riscv_vnot(vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint8mf2_t test___riscv_vnot(vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint8m1_t test___riscv_vnot(vint8m1_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint8m2_t test___riscv_vnot(vint8m2_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint8m4_t test___riscv_vnot(vint8m4_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint8m8_t test___riscv_vnot(vint8m8_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint16mf4_t test___riscv_vnot(vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint16mf2_t test___riscv_vnot(vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint16m1_t test___riscv_vnot(vint16m1_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint16m2_t test___riscv_vnot(vint16m2_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint16m4_t test___riscv_vnot(vint16m4_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint16m8_t test___riscv_vnot(vint16m8_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint32mf2_t test___riscv_vnot(vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint32m1_t test___riscv_vnot(vint32m1_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint32m2_t test___riscv_vnot(vint32m2_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint32m4_t test___riscv_vnot(vint32m4_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint32m8_t test___riscv_vnot(vint32m8_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint64m1_t test___riscv_vnot(vint64m1_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint64m2_t test___riscv_vnot(vint64m2_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint64m4_t test___riscv_vnot(vint64m4_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint64m8_t test___riscv_vnot(vint64m8_t op1,size_t vl) +{ + return __riscv_vnot(op1,31); +} + + +vint8mf8_t test___riscv_vnot(vbool64_t mask,vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint8mf4_t test___riscv_vnot(vbool32_t mask,vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint8mf2_t test___riscv_vnot(vbool16_t mask,vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint8m1_t test___riscv_vnot(vbool8_t mask,vint8m1_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint8m2_t test___riscv_vnot(vbool4_t mask,vint8m2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint8m4_t test___riscv_vnot(vbool2_t mask,vint8m4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint8m8_t test___riscv_vnot(vbool1_t mask,vint8m8_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint16mf4_t test___riscv_vnot(vbool64_t mask,vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint16mf2_t test___riscv_vnot(vbool32_t mask,vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint16m1_t test___riscv_vnot(vbool16_t mask,vint16m1_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint16m2_t test___riscv_vnot(vbool8_t mask,vint16m2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint16m4_t test___riscv_vnot(vbool4_t mask,vint16m4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint16m8_t test___riscv_vnot(vbool2_t mask,vint16m8_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint32mf2_t test___riscv_vnot(vbool64_t mask,vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint32m1_t test___riscv_vnot(vbool32_t mask,vint32m1_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint32m2_t test___riscv_vnot(vbool16_t mask,vint32m2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint32m4_t test___riscv_vnot(vbool8_t mask,vint32m4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint32m8_t test___riscv_vnot(vbool4_t mask,vint32m8_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint64m1_t test___riscv_vnot(vbool64_t mask,vint64m1_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint64m2_t test___riscv_vnot(vbool32_t mask,vint64m2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint64m4_t test___riscv_vnot(vbool16_t mask,vint64m4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + +vint64m8_t test___riscv_vnot(vbool8_t mask,vint64m8_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-3.C new file mode 100644 index 00000000000..42fd5054ea0 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-3.C @@ -0,0 +1,314 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnot(vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint8mf4_t test___riscv_vnot(vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint8mf2_t test___riscv_vnot(vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint8m1_t test___riscv_vnot(vint8m1_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint8m2_t test___riscv_vnot(vint8m2_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint8m4_t test___riscv_vnot(vint8m4_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint8m8_t test___riscv_vnot(vint8m8_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint16mf4_t test___riscv_vnot(vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint16mf2_t test___riscv_vnot(vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint16m1_t test___riscv_vnot(vint16m1_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint16m2_t test___riscv_vnot(vint16m2_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint16m4_t test___riscv_vnot(vint16m4_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint16m8_t test___riscv_vnot(vint16m8_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint32mf2_t test___riscv_vnot(vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint32m1_t test___riscv_vnot(vint32m1_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint32m2_t test___riscv_vnot(vint32m2_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint32m4_t test___riscv_vnot(vint32m4_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint32m8_t test___riscv_vnot(vint32m8_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint64m1_t test___riscv_vnot(vint64m1_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint64m2_t test___riscv_vnot(vint64m2_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint64m4_t test___riscv_vnot(vint64m4_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint64m8_t test___riscv_vnot(vint64m8_t op1,size_t vl) +{ + return __riscv_vnot(op1,32); +} + + +vint8mf8_t test___riscv_vnot(vbool64_t mask,vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint8mf4_t test___riscv_vnot(vbool32_t mask,vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint8mf2_t test___riscv_vnot(vbool16_t mask,vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint8m1_t test___riscv_vnot(vbool8_t mask,vint8m1_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint8m2_t test___riscv_vnot(vbool4_t mask,vint8m2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint8m4_t test___riscv_vnot(vbool2_t mask,vint8m4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint8m8_t test___riscv_vnot(vbool1_t mask,vint8m8_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint16mf4_t test___riscv_vnot(vbool64_t mask,vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint16mf2_t test___riscv_vnot(vbool32_t mask,vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint16m1_t test___riscv_vnot(vbool16_t mask,vint16m1_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint16m2_t test___riscv_vnot(vbool8_t mask,vint16m2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint16m4_t test___riscv_vnot(vbool4_t mask,vint16m4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint16m8_t test___riscv_vnot(vbool2_t mask,vint16m8_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint32mf2_t test___riscv_vnot(vbool64_t mask,vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint32m1_t test___riscv_vnot(vbool32_t mask,vint32m1_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint32m2_t test___riscv_vnot(vbool16_t mask,vint32m2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint32m4_t test___riscv_vnot(vbool8_t mask,vint32m4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint32m8_t test___riscv_vnot(vbool4_t mask,vint32m8_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint64m1_t test___riscv_vnot(vbool64_t mask,vint64m1_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint64m2_t test___riscv_vnot(vbool32_t mask,vint64m2_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint64m4_t test___riscv_vnot(vbool16_t mask,vint64m4_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + +vint64m8_t test___riscv_vnot(vbool8_t mask,vint64m8_t op1,size_t vl) +{ + return __riscv_vnot(mask,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-1.C new file mode 100644 index 00000000000..3fcbf02aed5 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnot_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint8mf4_t test___riscv_vnot_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint8mf2_t test___riscv_vnot_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint8m1_t test___riscv_vnot_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint8m2_t test___riscv_vnot_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint8m4_t test___riscv_vnot_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint8m8_t test___riscv_vnot_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint16mf4_t test___riscv_vnot_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint16mf2_t test___riscv_vnot_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint16m1_t test___riscv_vnot_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint16m2_t test___riscv_vnot_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint16m4_t test___riscv_vnot_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint16m8_t test___riscv_vnot_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint32mf2_t test___riscv_vnot_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint32m1_t test___riscv_vnot_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint32m2_t test___riscv_vnot_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint32m4_t test___riscv_vnot_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint32m8_t test___riscv_vnot_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint64m1_t test___riscv_vnot_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint64m2_t test___riscv_vnot_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint64m4_t test___riscv_vnot_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + +vint64m8_t test___riscv_vnot_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-2.C new file mode 100644 index 00000000000..5dde6117a43 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnot_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint8mf4_t test___riscv_vnot_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint8mf2_t test___riscv_vnot_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint8m1_t test___riscv_vnot_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint8m2_t test___riscv_vnot_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint8m4_t test___riscv_vnot_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint8m8_t test___riscv_vnot_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint16mf4_t test___riscv_vnot_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint16mf2_t test___riscv_vnot_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint16m1_t test___riscv_vnot_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint16m2_t test___riscv_vnot_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint16m4_t test___riscv_vnot_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint16m8_t test___riscv_vnot_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint32mf2_t test___riscv_vnot_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint32m1_t test___riscv_vnot_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint32m2_t test___riscv_vnot_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint32m4_t test___riscv_vnot_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint32m8_t test___riscv_vnot_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint64m1_t test___riscv_vnot_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint64m2_t test___riscv_vnot_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint64m4_t test___riscv_vnot_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + +vint64m8_t test___riscv_vnot_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-3.C new file mode 100644 index 00000000000..c3637b98b66 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnot_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint8mf4_t test___riscv_vnot_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint8mf2_t test___riscv_vnot_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint8m1_t test___riscv_vnot_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint8m2_t test___riscv_vnot_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint8m4_t test___riscv_vnot_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint8m8_t test___riscv_vnot_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint16mf4_t test___riscv_vnot_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint16mf2_t test___riscv_vnot_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint16m1_t test___riscv_vnot_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint16m2_t test___riscv_vnot_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint16m4_t test___riscv_vnot_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint16m8_t test___riscv_vnot_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint32mf2_t test___riscv_vnot_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint32m1_t test___riscv_vnot_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint32m2_t test___riscv_vnot_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint32m4_t test___riscv_vnot_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint32m8_t test___riscv_vnot_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint64m1_t test___riscv_vnot_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint64m2_t test___riscv_vnot_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint64m4_t test___riscv_vnot_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + +vint64m8_t test___riscv_vnot_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vnot_mu(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-1.C new file mode 100644 index 00000000000..25fb8e93c91 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnot_tu(vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint8mf4_t test___riscv_vnot_tu(vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint8mf2_t test___riscv_vnot_tu(vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint8m1_t test___riscv_vnot_tu(vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint8m2_t test___riscv_vnot_tu(vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint8m4_t test___riscv_vnot_tu(vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint8m8_t test___riscv_vnot_tu(vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint16mf4_t test___riscv_vnot_tu(vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint16mf2_t test___riscv_vnot_tu(vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint16m1_t test___riscv_vnot_tu(vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint16m2_t test___riscv_vnot_tu(vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint16m4_t test___riscv_vnot_tu(vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint16m8_t test___riscv_vnot_tu(vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint32mf2_t test___riscv_vnot_tu(vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint32m1_t test___riscv_vnot_tu(vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint32m2_t test___riscv_vnot_tu(vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint32m4_t test___riscv_vnot_tu(vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint32m8_t test___riscv_vnot_tu(vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint64m1_t test___riscv_vnot_tu(vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint64m2_t test___riscv_vnot_tu(vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint64m4_t test___riscv_vnot_tu(vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + +vint64m8_t test___riscv_vnot_tu(vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-2.C new file mode 100644 index 00000000000..b05b86fce83 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnot_tu(vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint8mf4_t test___riscv_vnot_tu(vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint8mf2_t test___riscv_vnot_tu(vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint8m1_t test___riscv_vnot_tu(vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint8m2_t test___riscv_vnot_tu(vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint8m4_t test___riscv_vnot_tu(vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint8m8_t test___riscv_vnot_tu(vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint16mf4_t test___riscv_vnot_tu(vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint16mf2_t test___riscv_vnot_tu(vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint16m1_t test___riscv_vnot_tu(vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint16m2_t test___riscv_vnot_tu(vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint16m4_t test___riscv_vnot_tu(vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint16m8_t test___riscv_vnot_tu(vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint32mf2_t test___riscv_vnot_tu(vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint32m1_t test___riscv_vnot_tu(vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint32m2_t test___riscv_vnot_tu(vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint32m4_t test___riscv_vnot_tu(vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint32m8_t test___riscv_vnot_tu(vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint64m1_t test___riscv_vnot_tu(vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint64m2_t test___riscv_vnot_tu(vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint64m4_t test___riscv_vnot_tu(vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + +vint64m8_t test___riscv_vnot_tu(vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-3.C new file mode 100644 index 00000000000..7048f9ecc99 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnot_tu(vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint8mf4_t test___riscv_vnot_tu(vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint8mf2_t test___riscv_vnot_tu(vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint8m1_t test___riscv_vnot_tu(vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint8m2_t test___riscv_vnot_tu(vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint8m4_t test___riscv_vnot_tu(vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint8m8_t test___riscv_vnot_tu(vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint16mf4_t test___riscv_vnot_tu(vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint16mf2_t test___riscv_vnot_tu(vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint16m1_t test___riscv_vnot_tu(vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint16m2_t test___riscv_vnot_tu(vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint16m4_t test___riscv_vnot_tu(vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint16m8_t test___riscv_vnot_tu(vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint32mf2_t test___riscv_vnot_tu(vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint32m1_t test___riscv_vnot_tu(vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint32m2_t test___riscv_vnot_tu(vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint32m4_t test___riscv_vnot_tu(vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint32m8_t test___riscv_vnot_tu(vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint64m1_t test___riscv_vnot_tu(vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint64m2_t test___riscv_vnot_tu(vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint64m4_t test___riscv_vnot_tu(vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + +vint64m8_t test___riscv_vnot_tu(vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vnot_tu(merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-1.C new file mode 100644 index 00000000000..151f6559f9f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnot_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint8mf4_t test___riscv_vnot_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint8mf2_t test___riscv_vnot_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint8m1_t test___riscv_vnot_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint8m2_t test___riscv_vnot_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint8m4_t test___riscv_vnot_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint8m8_t test___riscv_vnot_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint16mf4_t test___riscv_vnot_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint16mf2_t test___riscv_vnot_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint16m1_t test___riscv_vnot_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint16m2_t test___riscv_vnot_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint16m4_t test___riscv_vnot_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint16m8_t test___riscv_vnot_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint32mf2_t test___riscv_vnot_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint32m1_t test___riscv_vnot_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint32m2_t test___riscv_vnot_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint32m4_t test___riscv_vnot_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint32m8_t test___riscv_vnot_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint64m1_t test___riscv_vnot_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint64m2_t test___riscv_vnot_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint64m4_t test___riscv_vnot_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + +vint64m8_t test___riscv_vnot_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-2.C new file mode 100644 index 00000000000..a9d767d88f4 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnot_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint8mf4_t test___riscv_vnot_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint8mf2_t test___riscv_vnot_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint8m1_t test___riscv_vnot_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint8m2_t test___riscv_vnot_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint8m4_t test___riscv_vnot_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint8m8_t test___riscv_vnot_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint16mf4_t test___riscv_vnot_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint16mf2_t test___riscv_vnot_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint16m1_t test___riscv_vnot_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint16m2_t test___riscv_vnot_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint16m4_t test___riscv_vnot_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint16m8_t test___riscv_vnot_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint32mf2_t test___riscv_vnot_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint32m1_t test___riscv_vnot_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint32m2_t test___riscv_vnot_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint32m4_t test___riscv_vnot_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint32m8_t test___riscv_vnot_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint64m1_t test___riscv_vnot_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint64m2_t test___riscv_vnot_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint64m4_t test___riscv_vnot_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + +vint64m8_t test___riscv_vnot_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-3.C new file mode 100644 index 00000000000..1d39bcc7349 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnot_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint8mf4_t test___riscv_vnot_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint8mf2_t test___riscv_vnot_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint8m1_t test___riscv_vnot_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint8m2_t test___riscv_vnot_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint8m4_t test___riscv_vnot_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint8m8_t test___riscv_vnot_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint16mf4_t test___riscv_vnot_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint16mf2_t test___riscv_vnot_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint16m1_t test___riscv_vnot_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint16m2_t test___riscv_vnot_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint16m4_t test___riscv_vnot_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint16m8_t test___riscv_vnot_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint32mf2_t test___riscv_vnot_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint32m1_t test___riscv_vnot_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint32m2_t test___riscv_vnot_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint32m4_t test___riscv_vnot_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint32m8_t test___riscv_vnot_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint64m1_t test___riscv_vnot_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint64m2_t test___riscv_vnot_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint64m4_t test___riscv_vnot_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + +vint64m8_t test___riscv_vnot_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vnot_tum(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-1.C new file mode 100644 index 00000000000..9dfe96a8474 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnot_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint8mf4_t test___riscv_vnot_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint8mf2_t test___riscv_vnot_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint8m1_t test___riscv_vnot_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint8m2_t test___riscv_vnot_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint8m4_t test___riscv_vnot_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint8m8_t test___riscv_vnot_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint16mf4_t test___riscv_vnot_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint16mf2_t test___riscv_vnot_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint16m1_t test___riscv_vnot_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint16m2_t test___riscv_vnot_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint16m4_t test___riscv_vnot_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint16m8_t test___riscv_vnot_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint32mf2_t test___riscv_vnot_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint32m1_t test___riscv_vnot_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint32m2_t test___riscv_vnot_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint32m4_t test___riscv_vnot_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint32m8_t test___riscv_vnot_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint64m1_t test___riscv_vnot_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint64m2_t test___riscv_vnot_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint64m4_t test___riscv_vnot_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + +vint64m8_t test___riscv_vnot_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-2.C new file mode 100644 index 00000000000..223b7ce3865 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnot_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint8mf4_t test___riscv_vnot_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint8mf2_t test___riscv_vnot_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint8m1_t test___riscv_vnot_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint8m2_t test___riscv_vnot_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint8m4_t test___riscv_vnot_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint8m8_t test___riscv_vnot_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint16mf4_t test___riscv_vnot_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint16mf2_t test___riscv_vnot_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint16m1_t test___riscv_vnot_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint16m2_t test___riscv_vnot_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint16m4_t test___riscv_vnot_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint16m8_t test___riscv_vnot_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint32mf2_t test___riscv_vnot_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint32m1_t test___riscv_vnot_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint32m2_t test___riscv_vnot_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint32m4_t test___riscv_vnot_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint32m8_t test___riscv_vnot_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint64m1_t test___riscv_vnot_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint64m2_t test___riscv_vnot_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint64m4_t test___riscv_vnot_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + +vint64m8_t test___riscv_vnot_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-3.C new file mode 100644 index 00000000000..492595d74b1 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vnot_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint8mf4_t test___riscv_vnot_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint8mf2_t test___riscv_vnot_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint8m1_t test___riscv_vnot_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint8m2_t test___riscv_vnot_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint8m4_t test___riscv_vnot_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint8m8_t test___riscv_vnot_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint16mf4_t test___riscv_vnot_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint16mf2_t test___riscv_vnot_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint16m1_t test___riscv_vnot_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint16m2_t test___riscv_vnot_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint16m4_t test___riscv_vnot_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint16m8_t test___riscv_vnot_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint32mf2_t test___riscv_vnot_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint32m1_t test___riscv_vnot_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint32m2_t test___riscv_vnot_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint32m4_t test___riscv_vnot_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint32m8_t test___riscv_vnot_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint64m1_t test___riscv_vnot_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint64m2_t test___riscv_vnot_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint64m4_t test___riscv_vnot_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + +vint64m8_t test___riscv_vnot_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vnot_tumu(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */