From patchwork Fri Feb 3 23:25:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?6ZKf5bGF5ZOy?= X-Patchwork-Id: 64290 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 656293881D2E for ; Fri, 3 Feb 2023 23:25:46 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbg150.qq.com (smtpbg150.qq.com [18.132.163.193]) by sourceware.org (Postfix) with ESMTPS id 2801038555A0 for ; Fri, 3 Feb 2023 23:25:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2801038555A0 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp62t1675466724tr3hr1en Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Sat, 04 Feb 2023 07:25:23 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: jUz4x+AhIZkCK7lUR4oaRZv4kIjUXbh262EDj2KJlflR5vn6ZHMVj1/aJvtzd nZq8YgLoYu16rcguCwExzoH7kThUVnKsxKOtkmUw64zyGaVG1T59kBNLnA8EFDor+uhvKjN 1qF/1TyZTV2IAJ+YpG0PAFaewcjYlF4/JfQz7T/XhLhY9lh/7rn1Ara3XfiYSPmlYlCjZtR q0j9HvYwMKThZi1izOE0d8Zf290JC/ZMgI5YNEQ/2N7GR/sJP7BOFfOTJ7wm6XBNGLL1A/P bP/PN58W284l7IV5SFctmTmFt1m3jPWxS3EYEznk4mzD5Frtyd9cg4mPbsmhwCirys4GeXs jwRoMm7YgVTY/5/xBAPDRHDh3k+MyfqBxYAKWUe6SPzfn84sPJTkCx8c7nrXNOkOHD2CbTN X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add unary constraint tests. Date: Sat, 4 Feb 2023 07:25:22 +0800 Message-Id: <20230203232522.224551-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/unop_v_constraint-1.c: New test. --- .../riscv/rvv/base/unop_v_constraint-1.c | 132 ++++++++++++++++++ 1 file changed, 132 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-1.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-1.c new file mode 100644 index 00000000000..1266784fd8f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-1.c @@ -0,0 +1,132 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f1: +** vsetivli\tzero,4,e32,m1,tu,ma +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vneg\.v\tv[0-9]+,\s*v[0-9]+ +** vneg\.v\tv[0-9]+,\s*v[0-9]+ +** vse32\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vneg_v_i32m1 (v2, 4); + vint32m1_t v4 = __riscv_vneg_v_i32m1_tu (v3, v2, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e32,m1,ta,ma +** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vneg\.v\tv[0-9]+,\s*v[0-9]+ +** vneg\.v\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t +** vse32.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vneg_v_i32m1 (v2, 4); + vint32m1_t v4 = __riscv_vneg_v_i32m1_m (mask, v3, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e32,m1,tu,mu +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vneg\.v\tv[0-9]+,\s*v[0-9]+ +** vneg\.v\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t +** vse32.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vneg_v_i32m1 (v2, 4); + vint32m1_t v4 = __riscv_vneg_v_i32m1_tumu (mask, v3, v2, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f4: +** vsetivli\tzero,4,e8,mf8,tu,ma +** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** vneg\.v\tv[0-9]+,\s*v[0-9]+ +** vneg\.v\tv[0-9]+,\s*v[0-9]+ +** vse8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f4 (void * in, void *out) +{ + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4); + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in, 4); + vint8mf8_t v3 = __riscv_vneg_v_i8mf8 (v2, 4); + vint8mf8_t v4 = __riscv_vneg_v_i8mf8_tu (v3, v2, 4); + __riscv_vse8_v_i8mf8 (out, v4, 4); +} + +/* +** f5: +** vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e8,mf8,ta,ma +** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vneg\.v\tv[0-9]+,\s*v[0-9]+ +** vneg\.v\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t +** vse8.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f5 (void * in, void *out) +{ + vbool64_t mask = *(vbool64_t*)in; + asm volatile ("":::"memory"); + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4); + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_m (mask, in, 4); + vint8mf8_t v3 = __riscv_vneg_v_i8mf8 (v2, 4); + vint8mf8_t v4 = __riscv_vneg_v_i8mf8_m (mask, v3, 4); + __riscv_vse8_v_i8mf8 (out, v4, 4); +} + +/* +** f6: +** vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e8,mf8,tu,mu +** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vneg\.v\tv[0-9]+,\s*v[0-9]+ +** vneg\.v\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t +** vse8.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f6 (void * in, void *out) +{ + vbool64_t mask = *(vbool64_t*)in; + asm volatile ("":::"memory"); + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4); + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tumu (mask, v, in, 4); + vint8mf8_t v3 = __riscv_vneg_v_i8mf8 (v2, 4); + vint8mf8_t v4 = __riscv_vneg_v_i8mf8_tumu (mask, v3, v2, 4); + __riscv_vse8_v_i8mf8 (out, v4, 4); +}