From patchwork Fri Feb 3 09:42:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jin Ma X-Patchwork-Id: 64238 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1ED2C385828E for ; Fri, 3 Feb 2023 09:45:07 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 1ED2C385828E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1675417507; bh=nJEZkzZGno4V7XwAr1oUIS+shW+70bzqF91+zTPiFHY=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=kllHPL72zv0//JWWkF7HxUBxVstxD4CrTTwEaZPFKNJvGl2YlJXysNFjwoYcwIUle TBw07dEB0anTktnQPDMZzNoQhLwhklSgirKoZHkuZRHMQ3prAdHX9sLutvKXQCh/wy oo88WkSTx2KeCPVY7eUIqaJEvkt06gtcWoEKyEoo= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from out30-98.freemail.mail.aliyun.com (out30-98.freemail.mail.aliyun.com [115.124.30.98]) by sourceware.org (Postfix) with ESMTPS id C7A733858C52 for ; Fri, 3 Feb 2023 09:44:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C7A733858C52 X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R111e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018046049; MF=jinma@linux.alibaba.com; NM=1; PH=DS; RN=5; SR=0; TI=SMTPD_---0VaoJKkw_1675417467; Received: from localhost.localdomain(mailfrom:jinma@linux.alibaba.com fp:SMTPD_---0VaoJKkw_1675417467) by smtp.aliyun-inc.com; Fri, 03 Feb 2023 17:44:29 +0800 To: gcc-patches@gcc.gnu.org Cc: kito.cheng@sifive.com, kito.cheng@gmail.com, palmer@dabbelt.com, Jin Ma Subject: [PATCH v1] RISC-V: Change the generation mode of ADJUST_SP_RTX from gen_insn to gen_SET. Date: Fri, 3 Feb 2023 17:42:59 +0800 Message-Id: <20230203094259.673-1-jinma@linux.alibaba.com> X-Mailer: git-send-email 2.38.1.windows.1 MIME-Version: 1.0 X-Spam-Status: No, score=-20.9 required=5.0 tests=BAYES_00, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP, UNPARSEABLE_RELAY, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jin Ma via Gcc-patches From: Jin Ma Reply-To: Jin Ma Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" The gen_insn method is used to generate ADJUST_SP_RTX here, which has certain potential risks: When the architecture adds pre-processing to `define_insn "adddi3"`, such as `define_expend "adddi3"`, the gen_expand will be automatically called here, causing the patern to emit directly, which will cause insn to enter REG_NOTE for `DWARF` instead of patern. The following error REG_NOTE occurred: error: invalid rtl sharing found in the insn: (insn 19 3 20 2 (parallel [ ... ]) (expr_list:REG_CFA_ADJUST_CFA (insn 18 0 0 (set (reg/f:DI 2 sp) (plus:DI (reg/f:DI 2 sp) (const_int -16 [0xfffffffffffffff0]))) -1 (nil)))) In fact, the correct one should be the following: (insn 19 3 20 2 (parallel [ ... ]) (expr_list:REG_CFA_ADJUST_CFA (set (reg/f:DI 2 sp) (plus:DI (reg/f:DI 2 sp) (const_int -16 [0xfffffffffffffff0]))))) Following the treatment of arm or other architectures, it is more reasonable to use gen_SET here. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_adjust_libcall_cfi_prologue): Change gen_add3_insn to gen_rtx_SET. (riscv_adjust_libcall_cfi_epilogue): Likewise. --- gcc/config/riscv/riscv.cc | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 3b7804b7501..c9c6e53c6d0 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -5054,8 +5054,9 @@ riscv_adjust_libcall_cfi_prologue () } /* Debug info for adjust sp. */ - adjust_sp_rtx = gen_add3_insn (stack_pointer_rtx, - stack_pointer_rtx, GEN_INT (-saved_size)); + adjust_sp_rtx = + gen_rtx_SET (stack_pointer_rtx, + gen_rtx_PLUS (GET_MODE(stack_pointer_rtx), stack_pointer_rtx, GEN_INT (-saved_size))); dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, adjust_sp_rtx, dwarf); return dwarf; @@ -5176,8 +5177,9 @@ riscv_adjust_libcall_cfi_epilogue () int saved_size = cfun->machine->frame.save_libcall_adjustment; /* Debug info for adjust sp. */ - adjust_sp_rtx = gen_add3_insn (stack_pointer_rtx, - stack_pointer_rtx, GEN_INT (saved_size)); + adjust_sp_rtx = + gen_rtx_SET (stack_pointer_rtx, + gen_rtx_PLUS (GET_MODE(stack_pointer_rtx), stack_pointer_rtx, GEN_INT (saved_size))); dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, adjust_sp_rtx, dwarf);