From patchwork Fri Feb 3 08:14:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?6ZKf5bGF5ZOy?= X-Patchwork-Id: 64234 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E7A203858C33 for ; Fri, 3 Feb 2023 08:15:16 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgsg1.qq.com (smtpbgsg1.qq.com [54.254.200.92]) by sourceware.org (Postfix) with ESMTPS id 7B60D3858409 for ; Fri, 3 Feb 2023 08:14:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7B60D3858409 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp72t1675412047t0mcb0xy Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 03 Feb 2023 16:14:06 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: +stq0SUjyHwLiyWZtrgTS3CKUdUfVzUkK/6R3OgxutMiHibCAPNLEWaVfZpSI +uB/xbld3rPEuPibXux8bB4zAT6aJ5Uq0hmKRpS1/ewgF918kF55VfldISORp7HwMAB21nT 5vKxJwgfGS3VfcKDNYqism1lxVHFmbanTr/Zk0cpY4ivTretdk6I0+yZecTfK5+hwaTq4+Y CiHgW7oo/iRfGr/NyK2muLirNOUq2ksWOfaNWy3SQyhyCamD1y0ejoh5P7Jzg0e4IUSPcJ7 9LCChARNRL8zA9Vs6TiF6omRbOVjIhq2DKUQ2Rq9tYFf9ae1BVeIFIxFSri5LUYAVdVEraa T6qwaXyFvpPHuxXK5eMJ4BYDU2o9KAlpUcJSRlFoK+AHZ9R7wVdAmoFIarAqmzDeY3z73RG X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vand.vx C++ API test. Date: Fri, 3 Feb 2023 16:14:05 +0800 Message-Id: <20230203081405.232059-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vand_vx_mu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vand_vx_mu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vand_vx_mu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vand_vx_mu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vand_vx_mu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vand_vx_mu_rv64-3.C: New test. * g++.target/riscv/rvv/base/vand_vx_rv32-1.C: New test. * g++.target/riscv/rvv/base/vand_vx_rv32-2.C: New test. * g++.target/riscv/rvv/base/vand_vx_rv32-3.C: New test. * g++.target/riscv/rvv/base/vand_vx_rv64-1.C: New test. * g++.target/riscv/rvv/base/vand_vx_rv64-2.C: New test. * g++.target/riscv/rvv/base/vand_vx_rv64-3.C: New test. * g++.target/riscv/rvv/base/vand_vx_tu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vand_vx_tu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vand_vx_tu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vand_vx_tu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vand_vx_tu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vand_vx_tu_rv64-3.C: New test. * g++.target/riscv/rvv/base/vand_vx_tum_rv32-1.C: New test. * g++.target/riscv/rvv/base/vand_vx_tum_rv32-2.C: New test. * g++.target/riscv/rvv/base/vand_vx_tum_rv32-3.C: New test. * g++.target/riscv/rvv/base/vand_vx_tum_rv64-1.C: New test. * g++.target/riscv/rvv/base/vand_vx_tum_rv64-2.C: New test. * g++.target/riscv/rvv/base/vand_vx_tum_rv64-3.C: New test. * g++.target/riscv/rvv/base/vand_vx_tumu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vand_vx_tumu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vand_vx_tumu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vand_vx_tumu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vand_vx_tumu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vand_vx_tumu_rv64-3.C: New test. --- .../riscv/rvv/base/vand_vx_mu_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vand_vx_mu_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vand_vx_mu_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vand_vx_mu_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vand_vx_mu_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vand_vx_mu_rv64-3.C | 292 +++++++++ .../riscv/rvv/base/vand_vx_rv32-1.C | 572 +++++++++++++++++ .../riscv/rvv/base/vand_vx_rv32-2.C | 572 +++++++++++++++++ .../riscv/rvv/base/vand_vx_rv32-3.C | 572 +++++++++++++++++ .../riscv/rvv/base/vand_vx_rv64-1.C | 578 ++++++++++++++++++ .../riscv/rvv/base/vand_vx_rv64-2.C | 578 ++++++++++++++++++ .../riscv/rvv/base/vand_vx_rv64-3.C | 578 ++++++++++++++++++ .../riscv/rvv/base/vand_vx_tu_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vand_vx_tu_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vand_vx_tu_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vand_vx_tu_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vand_vx_tu_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vand_vx_tu_rv64-3.C | 292 +++++++++ .../riscv/rvv/base/vand_vx_tum_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vand_vx_tum_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vand_vx_tum_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vand_vx_tum_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vand_vx_tum_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vand_vx_tum_rv64-3.C | 292 +++++++++ .../riscv/rvv/base/vand_vx_tumu_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vand_vx_tumu_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vand_vx_tumu_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vand_vx_tumu_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vand_vx_tumu_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vand_vx_tumu_rv64-3.C | 292 +++++++++ 30 files changed, 10422 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv64-3.C diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv32-1.C new file mode 100644 index 00000000000..678e4f4a14a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv32-1.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vand_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vand_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vand_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vand_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vand_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vand_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vand_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vand_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vand_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vand_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vand_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vand_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vand_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vand_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vand_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vand_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vand_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vand_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vand_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vand_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vand_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vand_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vand_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vand_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vand_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vand_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vand_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vand_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vand_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vand_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vand_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vand_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vand_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vand_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vand_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vand_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vand_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vand_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vand_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vand_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vand_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vand_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vand_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv32-2.C new file mode 100644 index 00000000000..51642687f92 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv32-2.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vand_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vand_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vand_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vand_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vand_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vand_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vand_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vand_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vand_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vand_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vand_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vand_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vand_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vand_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vand_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vand_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vand_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vand_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vand_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vand_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vand_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vand_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vand_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vand_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vand_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vand_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vand_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vand_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vand_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vand_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vand_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vand_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vand_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vand_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vand_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vand_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vand_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vand_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vand_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vand_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vand_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vand_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vand_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv32-3.C new file mode 100644 index 00000000000..d7646399496 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv32-3.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vand_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vand_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vand_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vand_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vand_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vand_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vand_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vand_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vand_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vand_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vand_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vand_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vand_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vand_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vand_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vand_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vand_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vand_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vand_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vand_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vand_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vand_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vand_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vand_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vand_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vand_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vand_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vand_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vand_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vand_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vand_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vand_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vand_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vand_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vand_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vand_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vand_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vand_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vand_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vand_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vand_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vand_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vand_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv64-1.C new file mode 100644 index 00000000000..f0935c0570b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv64-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vand_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vand_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vand_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vand_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vand_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vand_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vand_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vand_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vand_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vand_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vand_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vand_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vand_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vand_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vand_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vand_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vand_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vand_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vand_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vand_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vand_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vand_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vand_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vand_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vand_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vand_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vand_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vand_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vand_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vand_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vand_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vand_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vand_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vand_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vand_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vand_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vand_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vand_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vand_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vand_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vand_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vand_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vand_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv64-2.C new file mode 100644 index 00000000000..b5b3b45558d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv64-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vand_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vand_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vand_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vand_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vand_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vand_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vand_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vand_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vand_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vand_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vand_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vand_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vand_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vand_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vand_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vand_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vand_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vand_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vand_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vand_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vand_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vand_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vand_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vand_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vand_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vand_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vand_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vand_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vand_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vand_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vand_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vand_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vand_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vand_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vand_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vand_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vand_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vand_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vand_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vand_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vand_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vand_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vand_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv64-3.C new file mode 100644 index 00000000000..90eb92c2872 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_mu_rv64-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vand_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vand_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vand_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vand_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vand_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vand_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vand_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vand_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vand_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vand_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vand_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vand_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vand_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vand_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vand_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vand_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vand_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vand_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vand_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vand_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vand_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vand_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vand_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vand_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vand_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vand_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vand_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vand_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vand_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vand_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vand_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vand_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vand_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vand_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vand_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vand_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vand_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vand_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vand_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vand_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vand_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vand_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vand_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv32-1.C new file mode 100644 index 00000000000..0539eb128d6 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv32-1.C @@ -0,0 +1,572 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint8mf4_t test___riscv_vand(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint8mf2_t test___riscv_vand(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint8m1_t test___riscv_vand(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint8m2_t test___riscv_vand(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint8m4_t test___riscv_vand(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint8m8_t test___riscv_vand(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vand(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vand(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint16m1_t test___riscv_vand(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint16m2_t test___riscv_vand(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint16m4_t test___riscv_vand(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint16m8_t test___riscv_vand(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vand(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint32m1_t test___riscv_vand(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint32m2_t test___riscv_vand(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint32m4_t test___riscv_vand(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint32m8_t test___riscv_vand(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint64m1_t test___riscv_vand(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint64m2_t test___riscv_vand(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint64m4_t test___riscv_vand(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint64m8_t test___riscv_vand(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vand(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vand(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vand(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint8m1_t test___riscv_vand(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint8m2_t test___riscv_vand(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint8m4_t test___riscv_vand(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint8m8_t test___riscv_vand(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vand(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vand(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint16m1_t test___riscv_vand(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint16m2_t test___riscv_vand(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint16m4_t test___riscv_vand(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint16m8_t test___riscv_vand(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vand(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint32m1_t test___riscv_vand(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint32m2_t test___riscv_vand(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint32m4_t test___riscv_vand(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint32m8_t test___riscv_vand(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint64m1_t test___riscv_vand(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint64m2_t test___riscv_vand(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint64m4_t test___riscv_vand(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint64m8_t test___riscv_vand(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint8mf8_t test___riscv_vand(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vand(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vand(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint8m1_t test___riscv_vand(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint8m2_t test___riscv_vand(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint8m4_t test___riscv_vand(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint8m8_t test___riscv_vand(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vand(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vand(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vand(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vand(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vand(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vand(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vand(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vand(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vand(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vand(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vand(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vand(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vand(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vand(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vand(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vand(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vand(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vand(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vand(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vand(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vand(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vand(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vand(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vand(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vand(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vand(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vand(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vand(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vand(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vand(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vand(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vand(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vand(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vand(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vand(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vand(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vand(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv32-2.C new file mode 100644 index 00000000000..77f0e6c65ba --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv32-2.C @@ -0,0 +1,572 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint8mf4_t test___riscv_vand(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint8mf2_t test___riscv_vand(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint8m1_t test___riscv_vand(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint8m2_t test___riscv_vand(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint8m4_t test___riscv_vand(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint8m8_t test___riscv_vand(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint16mf4_t test___riscv_vand(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint16mf2_t test___riscv_vand(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint16m1_t test___riscv_vand(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint16m2_t test___riscv_vand(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint16m4_t test___riscv_vand(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint16m8_t test___riscv_vand(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint32mf2_t test___riscv_vand(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint32m1_t test___riscv_vand(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint32m2_t test___riscv_vand(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint32m4_t test___riscv_vand(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint32m8_t test___riscv_vand(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint64m1_t test___riscv_vand(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint64m2_t test___riscv_vand(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint64m4_t test___riscv_vand(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint64m8_t test___riscv_vand(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint8mf8_t test___riscv_vand(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint8mf4_t test___riscv_vand(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint8mf2_t test___riscv_vand(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint8m1_t test___riscv_vand(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint8m2_t test___riscv_vand(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint8m4_t test___riscv_vand(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint8m8_t test___riscv_vand(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint16mf4_t test___riscv_vand(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint16mf2_t test___riscv_vand(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint16m1_t test___riscv_vand(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint16m2_t test___riscv_vand(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint16m4_t test___riscv_vand(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint16m8_t test___riscv_vand(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint32mf2_t test___riscv_vand(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint32m1_t test___riscv_vand(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint32m2_t test___riscv_vand(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint32m4_t test___riscv_vand(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint32m8_t test___riscv_vand(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint64m1_t test___riscv_vand(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint64m2_t test___riscv_vand(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint64m4_t test___riscv_vand(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint64m8_t test___riscv_vand(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint8mf8_t test___riscv_vand(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint8mf4_t test___riscv_vand(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint8mf2_t test___riscv_vand(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint8m1_t test___riscv_vand(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint8m2_t test___riscv_vand(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint8m4_t test___riscv_vand(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint8m8_t test___riscv_vand(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint16mf4_t test___riscv_vand(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vand(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vand(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vand(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vand(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vand(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vand(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vand(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vand(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vand(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vand(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vand(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vand(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vand(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vand(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vand(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vand(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vand(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint8m1_t test___riscv_vand(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint8m2_t test___riscv_vand(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint8m4_t test___riscv_vand(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint8m8_t test___riscv_vand(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vand(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vand(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint16m1_t test___riscv_vand(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint16m2_t test___riscv_vand(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint16m4_t test___riscv_vand(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint16m8_t test___riscv_vand(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vand(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint32m1_t test___riscv_vand(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint32m2_t test___riscv_vand(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint32m4_t test___riscv_vand(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint32m8_t test___riscv_vand(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint64m1_t test___riscv_vand(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint64m2_t test___riscv_vand(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint64m4_t test___riscv_vand(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint64m8_t test___riscv_vand(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv32-3.C new file mode 100644 index 00000000000..fdc0e459685 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv32-3.C @@ -0,0 +1,572 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint8mf4_t test___riscv_vand(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint8mf2_t test___riscv_vand(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint8m1_t test___riscv_vand(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint8m2_t test___riscv_vand(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint8m4_t test___riscv_vand(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint8m8_t test___riscv_vand(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint16mf4_t test___riscv_vand(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint16mf2_t test___riscv_vand(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint16m1_t test___riscv_vand(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint16m2_t test___riscv_vand(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint16m4_t test___riscv_vand(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint16m8_t test___riscv_vand(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint32mf2_t test___riscv_vand(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint32m1_t test___riscv_vand(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint32m2_t test___riscv_vand(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint32m4_t test___riscv_vand(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint32m8_t test___riscv_vand(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint64m1_t test___riscv_vand(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint64m2_t test___riscv_vand(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint64m4_t test___riscv_vand(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint64m8_t test___riscv_vand(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint8mf8_t test___riscv_vand(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint8mf4_t test___riscv_vand(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint8mf2_t test___riscv_vand(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint8m1_t test___riscv_vand(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint8m2_t test___riscv_vand(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint8m4_t test___riscv_vand(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint8m8_t test___riscv_vand(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint16mf4_t test___riscv_vand(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint16mf2_t test___riscv_vand(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint16m1_t test___riscv_vand(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint16m2_t test___riscv_vand(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint16m4_t test___riscv_vand(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint16m8_t test___riscv_vand(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint32mf2_t test___riscv_vand(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint32m1_t test___riscv_vand(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint32m2_t test___riscv_vand(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint32m4_t test___riscv_vand(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint32m8_t test___riscv_vand(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint64m1_t test___riscv_vand(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint64m2_t test___riscv_vand(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint64m4_t test___riscv_vand(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint64m8_t test___riscv_vand(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint8mf8_t test___riscv_vand(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint8mf4_t test___riscv_vand(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint8mf2_t test___riscv_vand(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint8m1_t test___riscv_vand(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint8m2_t test___riscv_vand(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint8m4_t test___riscv_vand(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint8m8_t test___riscv_vand(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint16mf4_t test___riscv_vand(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vand(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vand(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vand(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vand(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vand(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vand(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vand(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vand(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vand(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vand(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vand(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vand(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vand(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vand(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vand(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vand(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vand(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint8m1_t test___riscv_vand(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint8m2_t test___riscv_vand(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint8m4_t test___riscv_vand(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint8m8_t test___riscv_vand(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vand(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vand(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint16m1_t test___riscv_vand(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint16m2_t test___riscv_vand(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint16m4_t test___riscv_vand(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint16m8_t test___riscv_vand(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vand(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint32m1_t test___riscv_vand(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint32m2_t test___riscv_vand(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint32m4_t test___riscv_vand(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint32m8_t test___riscv_vand(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint64m1_t test___riscv_vand(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint64m2_t test___riscv_vand(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint64m4_t test___riscv_vand(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint64m8_t test___riscv_vand(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv64-1.C new file mode 100644 index 00000000000..7bfaf00cd32 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv64-1.C @@ -0,0 +1,578 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint8mf4_t test___riscv_vand(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint8mf2_t test___riscv_vand(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint8m1_t test___riscv_vand(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint8m2_t test___riscv_vand(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint8m4_t test___riscv_vand(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint8m8_t test___riscv_vand(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vand(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vand(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint16m1_t test___riscv_vand(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint16m2_t test___riscv_vand(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint16m4_t test___riscv_vand(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint16m8_t test___riscv_vand(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vand(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint32m1_t test___riscv_vand(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint32m2_t test___riscv_vand(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint32m4_t test___riscv_vand(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint32m8_t test___riscv_vand(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint64m1_t test___riscv_vand(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint64m2_t test___riscv_vand(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint64m4_t test___riscv_vand(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint64m8_t test___riscv_vand(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vand(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vand(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vand(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint8m1_t test___riscv_vand(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint8m2_t test___riscv_vand(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint8m4_t test___riscv_vand(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint8m8_t test___riscv_vand(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vand(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vand(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint16m1_t test___riscv_vand(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint16m2_t test___riscv_vand(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint16m4_t test___riscv_vand(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint16m8_t test___riscv_vand(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vand(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint32m1_t test___riscv_vand(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint32m2_t test___riscv_vand(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint32m4_t test___riscv_vand(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint32m8_t test___riscv_vand(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint64m1_t test___riscv_vand(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint64m2_t test___riscv_vand(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint64m4_t test___riscv_vand(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vuint64m8_t test___riscv_vand(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,vl); +} + + +vint8mf8_t test___riscv_vand(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vand(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vand(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint8m1_t test___riscv_vand(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint8m2_t test___riscv_vand(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint8m4_t test___riscv_vand(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint8m8_t test___riscv_vand(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vand(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vand(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vand(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vand(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vand(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vand(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vand(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vand(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vand(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vand(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vand(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vand(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vand(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vand(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vand(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vand(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vand(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vand(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vand(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vand(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vand(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vand(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vand(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vand(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vand(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vand(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vand(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vand(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vand(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vand(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vand(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vand(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vand(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vand(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vand(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vand(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vand(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv64-2.C new file mode 100644 index 00000000000..6ad13c699b6 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv64-2.C @@ -0,0 +1,578 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint8mf4_t test___riscv_vand(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint8mf2_t test___riscv_vand(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint8m1_t test___riscv_vand(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint8m2_t test___riscv_vand(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint8m4_t test___riscv_vand(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint8m8_t test___riscv_vand(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint16mf4_t test___riscv_vand(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint16mf2_t test___riscv_vand(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint16m1_t test___riscv_vand(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint16m2_t test___riscv_vand(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint16m4_t test___riscv_vand(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint16m8_t test___riscv_vand(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint32mf2_t test___riscv_vand(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint32m1_t test___riscv_vand(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint32m2_t test___riscv_vand(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint32m4_t test___riscv_vand(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint32m8_t test___riscv_vand(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint64m1_t test___riscv_vand(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint64m2_t test___riscv_vand(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint64m4_t test___riscv_vand(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint64m8_t test___riscv_vand(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint8mf8_t test___riscv_vand(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint8mf4_t test___riscv_vand(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint8mf2_t test___riscv_vand(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint8m1_t test___riscv_vand(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint8m2_t test___riscv_vand(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint8m4_t test___riscv_vand(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint8m8_t test___riscv_vand(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint16mf4_t test___riscv_vand(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint16mf2_t test___riscv_vand(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint16m1_t test___riscv_vand(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint16m2_t test___riscv_vand(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint16m4_t test___riscv_vand(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint16m8_t test___riscv_vand(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint32mf2_t test___riscv_vand(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint32m1_t test___riscv_vand(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint32m2_t test___riscv_vand(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint32m4_t test___riscv_vand(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint32m8_t test___riscv_vand(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint64m1_t test___riscv_vand(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint64m2_t test___riscv_vand(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint64m4_t test___riscv_vand(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vuint64m8_t test___riscv_vand(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,31); +} + + +vint8mf8_t test___riscv_vand(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint8mf4_t test___riscv_vand(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint8mf2_t test___riscv_vand(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint8m1_t test___riscv_vand(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint8m2_t test___riscv_vand(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint8m4_t test___riscv_vand(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint8m8_t test___riscv_vand(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint16mf4_t test___riscv_vand(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vand(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vand(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vand(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vand(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vand(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vand(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vand(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vand(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vand(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vand(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vand(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vand(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vand(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vand(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vand(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vand(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vand(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint8m1_t test___riscv_vand(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint8m2_t test___riscv_vand(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint8m4_t test___riscv_vand(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint8m8_t test___riscv_vand(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vand(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vand(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint16m1_t test___riscv_vand(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint16m2_t test___riscv_vand(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint16m4_t test___riscv_vand(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint16m8_t test___riscv_vand(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vand(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint32m1_t test___riscv_vand(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint32m2_t test___riscv_vand(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint32m4_t test___riscv_vand(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint32m8_t test___riscv_vand(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint64m1_t test___riscv_vand(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint64m2_t test___riscv_vand(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint64m4_t test___riscv_vand(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + +vuint64m8_t test___riscv_vand(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv64-3.C new file mode 100644 index 00000000000..ecc45a78f87 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv64-3.C @@ -0,0 +1,578 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint8mf4_t test___riscv_vand(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint8mf2_t test___riscv_vand(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint8m1_t test___riscv_vand(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint8m2_t test___riscv_vand(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint8m4_t test___riscv_vand(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint8m8_t test___riscv_vand(vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint16mf4_t test___riscv_vand(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint16mf2_t test___riscv_vand(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint16m1_t test___riscv_vand(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint16m2_t test___riscv_vand(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint16m4_t test___riscv_vand(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint16m8_t test___riscv_vand(vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint32mf2_t test___riscv_vand(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint32m1_t test___riscv_vand(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint32m2_t test___riscv_vand(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint32m4_t test___riscv_vand(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint32m8_t test___riscv_vand(vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint64m1_t test___riscv_vand(vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint64m2_t test___riscv_vand(vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint64m4_t test___riscv_vand(vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint64m8_t test___riscv_vand(vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint8mf8_t test___riscv_vand(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint8mf4_t test___riscv_vand(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint8mf2_t test___riscv_vand(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint8m1_t test___riscv_vand(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint8m2_t test___riscv_vand(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint8m4_t test___riscv_vand(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint8m8_t test___riscv_vand(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint16mf4_t test___riscv_vand(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint16mf2_t test___riscv_vand(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint16m1_t test___riscv_vand(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint16m2_t test___riscv_vand(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint16m4_t test___riscv_vand(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint16m8_t test___riscv_vand(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint32mf2_t test___riscv_vand(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint32m1_t test___riscv_vand(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint32m2_t test___riscv_vand(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint32m4_t test___riscv_vand(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint32m8_t test___riscv_vand(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint64m1_t test___riscv_vand(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint64m2_t test___riscv_vand(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint64m4_t test___riscv_vand(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vuint64m8_t test___riscv_vand(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(op1,op2,32); +} + + +vint8mf8_t test___riscv_vand(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint8mf4_t test___riscv_vand(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint8mf2_t test___riscv_vand(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint8m1_t test___riscv_vand(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint8m2_t test___riscv_vand(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint8m4_t test___riscv_vand(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint8m8_t test___riscv_vand(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint16mf4_t test___riscv_vand(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vand(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vand(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vand(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vand(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vand(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vand(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vand(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vand(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vand(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vand(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vand(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vand(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vand(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vand(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vand(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vand(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vand(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint8m1_t test___riscv_vand(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint8m2_t test___riscv_vand(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint8m4_t test___riscv_vand(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint8m8_t test___riscv_vand(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vand(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vand(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint16m1_t test___riscv_vand(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint16m2_t test___riscv_vand(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint16m4_t test___riscv_vand(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint16m8_t test___riscv_vand(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vand(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint32m1_t test___riscv_vand(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint32m2_t test___riscv_vand(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint32m4_t test___riscv_vand(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint32m8_t test___riscv_vand(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint64m1_t test___riscv_vand(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint64m2_t test___riscv_vand(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint64m4_t test___riscv_vand(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + +vuint64m8_t test___riscv_vand(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv32-1.C new file mode 100644 index 00000000000..f100e0db77b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv32-1.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vand_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vand_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vand_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vand_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vand_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vand_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vand_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vand_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vand_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vand_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vand_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vand_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vand_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vand_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vand_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vand_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vand_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vand_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vand_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vand_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vand_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vand_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vand_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vand_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vand_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vand_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vand_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vand_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vand_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vand_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vand_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vand_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vand_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vand_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vand_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vand_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vand_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vand_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vand_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vand_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vand_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vand_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vand_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv32-2.C new file mode 100644 index 00000000000..47b4591d41f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv32-2.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vand_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vand_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vand_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vand_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vand_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vand_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vand_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vand_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vand_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vand_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vand_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vand_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vand_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vand_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vand_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vand_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vand_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vand_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vand_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vand_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vand_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vand_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vand_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vand_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vand_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vand_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vand_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vand_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vand_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vand_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vand_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vand_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vand_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vand_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vand_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vand_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vand_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vand_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vand_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vand_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vand_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vand_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vand_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv32-3.C new file mode 100644 index 00000000000..eea61848961 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv32-3.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vand_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vand_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vand_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vand_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vand_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vand_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vand_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vand_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vand_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vand_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vand_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vand_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vand_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vand_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vand_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vand_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vand_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vand_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vand_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vand_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vand_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vand_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vand_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vand_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vand_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vand_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vand_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vand_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vand_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vand_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vand_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vand_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vand_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vand_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vand_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vand_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vand_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vand_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vand_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vand_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vand_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vand_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vand_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv64-1.C new file mode 100644 index 00000000000..92cf8ffd9af --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv64-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vand_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vand_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vand_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vand_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vand_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vand_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vand_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vand_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vand_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vand_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vand_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vand_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vand_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vand_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vand_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vand_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vand_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vand_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vand_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vand_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vand_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vand_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vand_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vand_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vand_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vand_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vand_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vand_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vand_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vand_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vand_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vand_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vand_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vand_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vand_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vand_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vand_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vand_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vand_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vand_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vand_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vand_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vand_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv64-2.C new file mode 100644 index 00000000000..626570f6248 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv64-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vand_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vand_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vand_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vand_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vand_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vand_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vand_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vand_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vand_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vand_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vand_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vand_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vand_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vand_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vand_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vand_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vand_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vand_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vand_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vand_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vand_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vand_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vand_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vand_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vand_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vand_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vand_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vand_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vand_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vand_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vand_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vand_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vand_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vand_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vand_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vand_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vand_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vand_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vand_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vand_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vand_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vand_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vand_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv64-3.C new file mode 100644 index 00000000000..435dae26b54 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tu_rv64-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vand_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vand_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vand_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vand_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vand_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vand_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vand_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vand_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vand_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vand_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vand_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vand_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vand_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vand_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vand_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vand_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vand_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vand_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vand_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vand_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vand_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vand_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vand_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vand_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vand_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vand_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vand_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vand_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vand_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vand_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vand_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vand_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vand_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vand_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vand_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vand_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vand_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vand_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vand_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vand_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vand_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vand_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vand_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv32-1.C new file mode 100644 index 00000000000..c4b680d90af --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv32-1.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vand_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vand_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vand_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vand_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vand_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vand_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vand_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vand_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vand_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vand_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vand_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vand_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vand_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vand_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vand_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vand_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vand_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vand_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vand_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vand_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vand_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vand_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vand_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vand_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vand_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vand_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vand_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vand_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vand_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vand_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vand_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vand_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vand_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vand_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vand_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vand_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vand_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vand_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vand_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vand_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vand_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vand_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vand_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv32-2.C new file mode 100644 index 00000000000..8efac1c7efb --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv32-2.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vand_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vand_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vand_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vand_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vand_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vand_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vand_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vand_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vand_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vand_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vand_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vand_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vand_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vand_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vand_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vand_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vand_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vand_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vand_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vand_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vand_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vand_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vand_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vand_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vand_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vand_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vand_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vand_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vand_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vand_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vand_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vand_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vand_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vand_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vand_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vand_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vand_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vand_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vand_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vand_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vand_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vand_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vand_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv32-3.C new file mode 100644 index 00000000000..31a443becca --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv32-3.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vand_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vand_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vand_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vand_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vand_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vand_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vand_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vand_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vand_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vand_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vand_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vand_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vand_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vand_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vand_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vand_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vand_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vand_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vand_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vand_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vand_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vand_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vand_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vand_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vand_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vand_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vand_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vand_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vand_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vand_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vand_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vand_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vand_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vand_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vand_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vand_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vand_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vand_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vand_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vand_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vand_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vand_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vand_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv64-1.C new file mode 100644 index 00000000000..e8ccf7251a1 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv64-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vand_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vand_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vand_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vand_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vand_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vand_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vand_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vand_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vand_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vand_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vand_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vand_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vand_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vand_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vand_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vand_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vand_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vand_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vand_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vand_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vand_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vand_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vand_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vand_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vand_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vand_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vand_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vand_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vand_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vand_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vand_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vand_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vand_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vand_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vand_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vand_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vand_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vand_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vand_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vand_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vand_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vand_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vand_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv64-2.C new file mode 100644 index 00000000000..4d3661dd8b6 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv64-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vand_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vand_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vand_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vand_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vand_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vand_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vand_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vand_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vand_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vand_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vand_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vand_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vand_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vand_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vand_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vand_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vand_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vand_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vand_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vand_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vand_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vand_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vand_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vand_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vand_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vand_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vand_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vand_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vand_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vand_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vand_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vand_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vand_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vand_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vand_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vand_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vand_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vand_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vand_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vand_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vand_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vand_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vand_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv64-3.C new file mode 100644 index 00000000000..916cc3e7fea --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tum_rv64-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vand_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vand_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vand_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vand_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vand_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vand_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vand_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vand_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vand_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vand_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vand_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vand_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vand_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vand_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vand_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vand_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vand_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vand_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vand_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vand_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vand_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vand_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vand_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vand_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vand_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vand_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vand_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vand_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vand_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vand_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vand_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vand_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vand_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vand_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vand_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vand_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vand_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vand_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vand_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vand_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vand_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vand_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vand_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv32-1.C new file mode 100644 index 00000000000..c4eddda9c23 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv32-1.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vand_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vand_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vand_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vand_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vand_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vand_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vand_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vand_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vand_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vand_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vand_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vand_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vand_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vand_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vand_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vand_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vand_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vand_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vand_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vand_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vand_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vand_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vand_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vand_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vand_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vand_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vand_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vand_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vand_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vand_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vand_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vand_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vand_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vand_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vand_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vand_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vand_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vand_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vand_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vand_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vand_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vand_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vand_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv32-2.C new file mode 100644 index 00000000000..1e4a7e7f780 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv32-2.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vand_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vand_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vand_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vand_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vand_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vand_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vand_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vand_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vand_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vand_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vand_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vand_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vand_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vand_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vand_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vand_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vand_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vand_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vand_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vand_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vand_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vand_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vand_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vand_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vand_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vand_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vand_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vand_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vand_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vand_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vand_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vand_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vand_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vand_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vand_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vand_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vand_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vand_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vand_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vand_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vand_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vand_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vand_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv32-3.C new file mode 100644 index 00000000000..603394d4ef4 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv32-3.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vand_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vand_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vand_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vand_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vand_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vand_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vand_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vand_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vand_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vand_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vand_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vand_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vand_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vand_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vand_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vand_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vand_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vand_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vand_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vand_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vand_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vand_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vand_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vand_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vand_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vand_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vand_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vand_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vand_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vand_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vand_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vand_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vand_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vand_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vand_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vand_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vand_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vand_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vand_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vand_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vand_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vand_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vand_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vand\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv64-1.C new file mode 100644 index 00000000000..02cc9708842 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv64-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vand_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vand_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vand_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vand_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vand_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vand_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vand_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vand_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vand_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vand_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vand_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vand_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vand_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vand_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vand_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vand_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vand_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vand_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vand_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vand_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vand_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vand_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vand_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vand_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vand_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vand_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vand_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vand_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vand_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vand_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vand_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vand_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vand_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vand_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vand_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vand_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vand_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vand_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vand_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vand_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vand_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vand_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vand_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv64-2.C new file mode 100644 index 00000000000..4c0131a7a3d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv64-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vand_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vand_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vand_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vand_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vand_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vand_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vand_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vand_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vand_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vand_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vand_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vand_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vand_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vand_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vand_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vand_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vand_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vand_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vand_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vand_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vand_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vand_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vand_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vand_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vand_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vand_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vand_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vand_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vand_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vand_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vand_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vand_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vand_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vand_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vand_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vand_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vand_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vand_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vand_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vand_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vand_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vand_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vand_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv64-3.C new file mode 100644 index 00000000000..a6e2143454b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_tumu_rv64-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vand_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vand_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vand_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vand_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vand_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vand_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vand_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vand_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vand_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vand_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vand_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vand_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vand_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vand_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vand_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vand_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vand_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vand_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vand_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vand_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vand_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vand_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vand_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vand_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vand_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vand_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vand_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vand_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vand_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vand_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vand_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vand_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vand_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vand_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vand_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vand_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vand_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vand_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vand_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vand_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vand_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vand_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vand_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vand_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vand_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vand\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */