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[69.181.90.243]) by smtp.gmail.com with ESMTPSA id z15sm9156171pjz.41.2021.02.12.12.58.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Feb 2021 12:58:50 -0800 (PST) Received: from gnu-tgl-2.localdomain (gnu-tgl-2 [192.168.1.34]) by gnu-cfl-2.localdomain (Postfix) with ESMTPS id 6E5C01A06AD for ; Fri, 12 Feb 2021 12:58:49 -0800 (PST) Received: from gnu-tgl-2.localdomain (localhost [IPv6:::1]) by gnu-tgl-2.localdomain (Postfix) with ESMTP id 555693001D9 for ; Fri, 12 Feb 2021 12:58:48 -0800 (PST) To: libc-alpha@sourceware.org Subject: [PATCH] x86: Use x86/nptl/pthreaddef.h Date: Fri, 12 Feb 2021 12:58:46 -0800 Message-Id: <20210212205846.2197814-1-hjl.tools@gmail.com> X-Mailer: git-send-email 2.29.2 MIME-Version: 1.0 X-Spam-Status: No, score=-3038.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: "H.J. Lu via Libc-alpha" From: "H.J. Lu" Reply-To: "H.J. Lu" Errors-To: libc-alpha-bounces@sourceware.org Sender: "Libc-alpha" 1. Move sysdeps/i386/nptl/pthreaddef.h to sysdeps/x86/nptl/pthreaddef.h. 2. Remove sysdeps/x86_64/nptl/pthreaddef.h. --- sysdeps/{i386 => x86}/nptl/pthreaddef.h | 8 ++++- sysdeps/x86_64/nptl/pthreaddef.h | 47 ------------------------- 2 files changed, 7 insertions(+), 48 deletions(-) rename sysdeps/{i386 => x86}/nptl/pthreaddef.h (88%) delete mode 100644 sysdeps/x86_64/nptl/pthreaddef.h diff --git a/sysdeps/i386/nptl/pthreaddef.h b/sysdeps/x86/nptl/pthreaddef.h similarity index 88% rename from sysdeps/i386/nptl/pthreaddef.h rename to sysdeps/x86/nptl/pthreaddef.h index a488cac603..6ff7d601eb 100644 --- a/sysdeps/i386/nptl/pthreaddef.h +++ b/sysdeps/x86/nptl/pthreaddef.h @@ -40,4 +40,10 @@ /* Location of current stack frame. */ -#define CURRENT_STACK_FRAME __builtin_frame_address (0) +#ifdef __x86_64__ +/* The frame pointer is not usable. */ +# define CURRENT_STACK_FRAME \ + ({ register char *frame __asm__("rsp"); frame; }) +#else +# define CURRENT_STACK_FRAME __builtin_frame_address (0) +#endif diff --git a/sysdeps/x86_64/nptl/pthreaddef.h b/sysdeps/x86_64/nptl/pthreaddef.h deleted file mode 100644 index a8b5fa4c45..0000000000 --- a/sysdeps/x86_64/nptl/pthreaddef.h +++ /dev/null @@ -1,47 +0,0 @@ -/* Copyright (C) 2002-2021 Free Software Foundation, Inc. - This file is part of the GNU C Library. - Contributed by Ulrich Drepper , 2002. - - The GNU C Library is free software; you can redistribute it and/or - modify it under the terms of the GNU Lesser General Public - License as published by the Free Software Foundation; either - version 2.1 of the License, or (at your option) any later version. - - The GNU C Library is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - Lesser General Public License for more details. - - You should have received a copy of the GNU Lesser General Public - License along with the GNU C Library; if not, see - . */ - -/* Default stack size. */ -#define ARCH_STACK_DEFAULT_SIZE (2 * 1024 * 1024) - -/* Minimum guard size. */ -#define ARCH_MIN_GUARD_SIZE 0 - -/* Required stack pointer alignment at beginning. SSE requires 16 - bytes. */ -#define STACK_ALIGN 16 - -/* Minimal stack size after allocating thread descriptor and guard size. */ -#define MINIMAL_REST_STACK 2048 - -/* Alignment requirement for TCB. - - We need to store post-AVX vector registers in the TCB and we want the - storage to be aligned to at least 32 bytes. - - Some processors such as Intel Atom pay a big penalty on every - access using a segment override if that segment's base is not - aligned to the size of a cache line. (See Intel 64 and IA-32 - Architectures Optimization Reference Manual, section 13.3.3.3, - "Segment Base".) On such machines, a cache line is 64 bytes. */ -#define TCB_ALIGNMENT 64 - - -/* Location of current stack frame. The frame pointer is not usable. */ -#define CURRENT_STACK_FRAME \ - ({ register char *frame __asm__("rsp"); frame; })