From patchwork Wed Nov 30 18:50:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John David Anglin X-Patchwork-Id: 61276 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 318EC385516F for ; Wed, 30 Nov 2022 18:50:30 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from dellerweb.de (unknown [IPv6:2a02:c207:3003:236::1]) by sourceware.org (Postfix) with ESMTPS id 5FC8C385842E for ; Wed, 30 Nov 2022 18:50:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 5FC8C385842E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=bell.net Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=bell.net Received: from mx3210.localdomain (bras-base-otwaon0925w-grc-05-174-95-50-166.dsl.bell.ca [174.95.50.166]) by dellerweb.de (Postfix) with ESMTPSA id A3AFE16001A4; Wed, 30 Nov 2022 19:50:13 +0100 (CET) Received: by mx3210.localdomain (Postfix, from userid 1000) id 6815D22011B; Wed, 30 Nov 2022 18:50:11 +0000 (UTC) Date: Wed, 30 Nov 2022 18:50:11 +0000 From: John David Anglin To: GCC Patches Subject: [committed] hppa: Fix addvdi3 and subvdi3 patterns Message-ID: MIME-Version: 1.0 Content-Disposition: inline X-Spam-Status: No, score=-10.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KHOP_HELO_FCRDNS, SPF_HELO_NONE, SPF_SOFTFAIL, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This was found building 64-bit openssh package. Committed to active branches. Dave --- Fix addvdi3 and subvdi3 patterns While most PA 2.0 instructions support both 32 and 64-bit traps and conditions, the addi and subi instructions only support 32-bit traps and conditions. Thus, we need to force immediate operands to register operands on the 64-bit target and use the add/sub instructions which can trap on 64-bit signed overflow. 2022-11-30 John David Anglin gcc/ChangeLog: * config/pa/pa.md (addvdi3): Force operand 2 to a register. Remove "addi,tsv,*" instruction from unamed pattern. (subvdi3): Force operand 1 to a register. Remove "subi,tsv" instruction from from unamed pattern. diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index 76ae35d4cfa..41382271e54 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -5071,23 +5071,25 @@ (match_dup 2)))) (const_int 0))])] "" - "") + " +{ + if (TARGET_64BIT) + operands[2] = force_reg (DImode, operands[2]); +}") (define_insn "" - [(set (match_operand:DI 0 "register_operand" "=r,r") - (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rM,rM") - (match_operand:DI 2 "arith11_operand" "r,I"))) + [(set (match_operand:DI 0 "register_operand" "=r") + (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rM") + (match_operand:DI 2 "register_operand" "r"))) (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1)) (sign_extend:TI (match_dup 2))) (sign_extend:TI (plus:DI (match_dup 1) (match_dup 2)))) (const_int 0))] "TARGET_64BIT" - "@ - add,tsv,* %2,%1,%0 - addi,tsv,* %2,%1,%0" - [(set_attr "type" "binary,binary") - (set_attr "length" "4,4")]) + "add,tsv,* %2,%1,%0" + [(set_attr "type" "binary") + (set_attr "length" "4")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") @@ -5262,23 +5264,25 @@ (match_dup 2)))) (const_int 0))])] "" - "") + " +{ + if (TARGET_64BIT) + operands[1] = force_reg (DImode, operands[1]); +}") (define_insn "" - [(set (match_operand:DI 0 "register_operand" "=r,r") - (minus:DI (match_operand:DI 1 "arith11_operand" "r,I") - (match_operand:DI 2 "reg_or_0_operand" "rM,rM"))) + [(set (match_operand:DI 0 "register_operand" "=r") + (minus:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "reg_or_0_operand" "rM"))) (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1)) (sign_extend:TI (match_dup 2))) (sign_extend:TI (minus:DI (match_dup 1) (match_dup 2)))) (const_int 0))] "TARGET_64BIT" - "@ - {subo|sub,tsv} %1,%2,%0 - {subio|subi,tsv} %1,%2,%0" - [(set_attr "type" "binary,binary") - (set_attr "length" "4,4")]) + "sub,tsv,* %1,%2,%0" + [(set_attr "type" "binary") + (set_attr "length" "4")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r,&r")