From patchwork Fri Nov 18 06:37:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Noah Goldstein X-Patchwork-Id: 60814 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id AE41D3853D56 for ; Fri, 18 Nov 2022 06:38:22 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org AE41D3853D56 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1668753502; bh=uaeJfMKbGTdRvirH+6vnMHHgWbK65BJz+XnT4iO99Mk=; h=To:Cc:Subject:Date:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=QDdry9JisqGggWYyJvRsgduOctgt+H2dlM78p11bbm/tmUafwDfn/+wTxo70Lc96i 4GYDWK5UsnDPW1IDyD5adHXRQ+I0ODXM3/96juoHpcCD/DWVa3hi8ezyJGGwVOgE+A A9cgIBCLxBD/Zpiwt/NOj/oFQIMB8UKaaXlO0FMU= X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-pf1-x434.google.com (mail-pf1-x434.google.com [IPv6:2607:f8b0:4864:20::434]) by sourceware.org (Postfix) with ESMTPS id 31B77385455C for ; Fri, 18 Nov 2022 06:37:31 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 31B77385455C Received: by mail-pf1-x434.google.com with SMTP id 130so4008337pfu.8 for ; Thu, 17 Nov 2022 22:37:31 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=uaeJfMKbGTdRvirH+6vnMHHgWbK65BJz+XnT4iO99Mk=; b=ldpzqtUBb1tJxiWlfAPqpcGWwKFxJVvYAflOEtNBd6xMTEtWpvdCoy4FlNjFc5YUoj S7x01TDeABgbwQvxSBWqKZi86qSa0ULjCawlH/ctnCIr+3Z1TspMW1o0ZWhmEYr1KuIx euHF2Zu6McZHJQSFh45xNA1enZwnGm1fObqU7WIpIWKuDr4xfgiTuBIzQvEPby/gn7za eFOEwkTJdf24kaH+95mleCKkH3XeDCwZXnJ4uDgmW5yufJrKrsKSS3A+Q8CImW3YPtcd 2xj1g7g7a+Ju+DVoKU2zhrcmQK7KRio3+LV2fff2nNHQUK2d8JC54C9q68Z5lPZxaO78 R5YA== X-Gm-Message-State: ANoB5pnQJ44aqawYzQke2T/Qpa2tk1V06/J5s7bOhmqFBIVIG0/zJD6k CR7SnTQGOnJXxaFN2yCiDkrswrW1AvA= X-Google-Smtp-Source: AA0mqf4GyfaUdI7TJfbI2jiG37h9jM5gE1uXzkhiBGl9TKtvI+29Fr3m+YnvJNXycdiY51K7sK6Rxw== X-Received: by 2002:a63:3189:0:b0:473:efcb:3950 with SMTP id x131-20020a633189000000b00473efcb3950mr5575638pgx.232.1668753447858; Thu, 17 Nov 2022 22:37:27 -0800 (PST) Received: from noahgold-desk.. ([192.55.60.47]) by smtp.gmail.com with ESMTPSA id j7-20020a170902da8700b00176a6ba5969sm2670692plx.98.2022.11.17.22.37.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Nov 2022 22:37:27 -0800 (PST) To: libc-alpha@sourceware.org Cc: goldstein.w.n@gmail.com, hjl.tools@gmail.com, carlos@systemhalted.org Subject: [PATCH v1 1/3] x86/fpu: Move svml_{s|d}_wrapper_impl.h -> svml_{s|d}_wrapper_impl.h.S Date: Thu, 17 Nov 2022 22:37:21 -0800 Message-Id: <20221118063723.858936-1-goldstein.w.n@gmail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Noah Goldstein via Libc-alpha From: Noah Goldstein Reply-To: Noah Goldstein Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org Sender: "Libc-alpha" The files are assembler so having the proper file extension is convenient. This doesn't change libm.so or libmvec.so. --- sysdeps/x86_64/fpu/multiarch/svml_d_cos8_core_avx512.S | 2 +- sysdeps/x86_64/fpu/multiarch/svml_d_exp8_core_avx512.S | 2 +- sysdeps/x86_64/fpu/multiarch/svml_d_log8_core_avx512.S | 2 +- sysdeps/x86_64/fpu/multiarch/svml_d_pow8_core_avx512.S | 2 +- sysdeps/x86_64/fpu/multiarch/svml_d_sin8_core_avx512.S | 2 +- sysdeps/x86_64/fpu/multiarch/svml_d_sincos8_core_avx512.S | 2 +- sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core_avx512.S | 2 +- sysdeps/x86_64/fpu/multiarch/svml_s_expf16_core_avx512.S | 2 +- sysdeps/x86_64/fpu/multiarch/svml_s_logf16_core_avx512.S | 2 +- sysdeps/x86_64/fpu/multiarch/svml_s_powf16_core_avx512.S | 2 +- sysdeps/x86_64/fpu/multiarch/svml_s_sincosf16_core_avx512.S | 2 +- sysdeps/x86_64/fpu/multiarch/svml_s_sinf16_core_avx512.S | 2 +- sysdeps/x86_64/fpu/svml_d_acos2_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_acos4_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_acos4_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_d_acos8_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_acosh2_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_acosh4_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_acosh4_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_d_acosh8_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_asin2_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_asin4_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_asin4_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_d_asin8_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_asinh2_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_asinh4_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_asinh4_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_d_asinh8_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_atan22_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_atan24_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_atan24_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_d_atan28_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_atan2_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_atan4_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_atan4_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_d_atan8_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_atanh2_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_atanh4_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_atanh4_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_d_atanh8_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_cbrt2_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_cbrt4_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_cbrt4_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_d_cbrt8_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_cos2_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_cos4_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_cos4_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_d_cos8_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_cosh2_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_cosh4_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_cosh4_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_d_cosh8_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_erf2_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_erf4_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_erf4_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_d_erf8_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_erfc2_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_erfc4_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_erfc4_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_d_erfc8_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_exp102_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_exp104_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_exp104_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_d_exp108_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_exp22_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_exp24_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_exp24_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_d_exp28_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_exp2_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_exp4_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_exp4_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_d_exp8_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_expm12_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_expm14_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_expm14_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_d_expm18_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_hypot2_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_hypot4_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_hypot4_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_d_hypot8_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_log102_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_log104_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_log104_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_d_log108_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_log1p2_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_log1p4_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_log1p4_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_d_log1p8_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_log22_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_log24_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_log24_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_d_log28_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_log2_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_log4_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_log4_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_d_log8_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_pow2_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_pow4_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_pow4_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_d_pow8_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_sin2_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_sin4_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_sin4_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_d_sin8_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_sincos2_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_sincos4_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_sincos4_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_d_sincos8_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_sinh2_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_sinh4_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_sinh4_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_d_sinh8_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_tan2_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_tan4_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_tan4_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_d_tan8_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_tanh2_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_tanh4_core.S | 2 +- sysdeps/x86_64/fpu/svml_d_tanh4_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_d_tanh8_core.S | 2 +- .../fpu/{svml_d_wrapper_impl.h => svml_d_wrapper_impl.h.S} | 0 sysdeps/x86_64/fpu/svml_s_acosf16_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_acosf4_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_acosf8_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_acosf8_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_s_acoshf16_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_acoshf4_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_acoshf8_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_acoshf8_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_s_asinf16_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_asinf4_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_asinf8_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_asinf8_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_s_asinhf16_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_asinhf4_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_asinhf8_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_asinhf8_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_s_atan2f16_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_atan2f4_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_atan2f8_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_atan2f8_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_s_atanf16_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_atanf4_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_atanf8_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_atanf8_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_s_atanhf16_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_atanhf4_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_atanhf8_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_atanhf8_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_s_cbrtf16_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_cbrtf4_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_cbrtf8_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_cbrtf8_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_s_cosf16_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_cosf4_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_cosf8_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_cosf8_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_s_coshf16_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_coshf4_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_coshf8_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_coshf8_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_s_erfcf16_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_erfcf4_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_erfcf8_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_erfcf8_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_s_erff16_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_erff4_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_erff8_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_erff8_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_s_exp10f16_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_exp10f4_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_exp10f8_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_exp10f8_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_s_exp2f16_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_exp2f4_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_exp2f8_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_exp2f8_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_s_expf16_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_expf4_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_expf8_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_expf8_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_s_expm1f16_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_expm1f4_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_expm1f8_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_expm1f8_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_s_hypotf16_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_hypotf4_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_hypotf8_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_hypotf8_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_s_log10f16_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_log10f4_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_log10f8_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_log10f8_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_s_log1pf16_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_log1pf4_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_log1pf8_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_log1pf8_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_s_log2f16_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_log2f4_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_log2f8_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_log2f8_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_s_logf16_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_logf4_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_logf8_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_logf8_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_s_powf16_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_powf4_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_powf8_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_powf8_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_s_sincosf16_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_sincosf4_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_sincosf8_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_sincosf8_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_s_sinf16_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_sinf4_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_sinf8_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_sinf8_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_s_sinhf16_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_sinhf4_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_sinhf8_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_sinhf8_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_s_tanf16_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_tanf4_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_tanf8_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_tanf8_core_avx.S | 2 +- sysdeps/x86_64/fpu/svml_s_tanhf16_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_tanhf4_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_tanhf8_core.S | 2 +- sysdeps/x86_64/fpu/svml_s_tanhf8_core_avx.S | 2 +- .../fpu/{svml_s_wrapper_impl.h => svml_s_wrapper_impl.h.S} | 0 230 files changed, 228 insertions(+), 228 deletions(-) rename sysdeps/x86_64/fpu/{svml_d_wrapper_impl.h => svml_d_wrapper_impl.h.S} (100%) rename sysdeps/x86_64/fpu/{svml_s_wrapper_impl.h => svml_s_wrapper_impl.h.S} (100%) diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_cos8_core_avx512.S b/sysdeps/x86_64/fpu/multiarch/svml_d_cos8_core_avx512.S index 86543d50d3..b2675d9647 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_d_cos8_core_avx512.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_d_cos8_core_avx512.S @@ -18,7 +18,7 @@ #include #include "svml_d_trig_data.h" -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVeN8v_cos_knl) diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_exp8_core_avx512.S b/sysdeps/x86_64/fpu/multiarch/svml_d_exp8_core_avx512.S index bccc56858d..98f2bc2e41 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_d_exp8_core_avx512.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_d_exp8_core_avx512.S @@ -18,7 +18,7 @@ #include #include "svml_d_exp_data.h" -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVeN8v_exp_knl) diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_log8_core_avx512.S b/sysdeps/x86_64/fpu/multiarch/svml_d_log8_core_avx512.S index 230ebe8ceb..20d4d967e0 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_d_log8_core_avx512.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_d_log8_core_avx512.S @@ -18,7 +18,7 @@ #include #include "svml_d_log_data.h" -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVeN8v_log_knl) diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_pow8_core_avx512.S b/sysdeps/x86_64/fpu/multiarch/svml_d_pow8_core_avx512.S index 963fbe3662..a4c6c27147 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_d_pow8_core_avx512.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_d_pow8_core_avx512.S @@ -18,7 +18,7 @@ #include #include "svml_d_pow_data.h" -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" /* ALGORITHM DESCRIPTION: diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_sin8_core_avx512.S b/sysdeps/x86_64/fpu/multiarch/svml_d_sin8_core_avx512.S index 54bd8679d1..f3de17b413 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_d_sin8_core_avx512.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_d_sin8_core_avx512.S @@ -18,7 +18,7 @@ #include #include "svml_d_trig_data.h" -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVeN8v_sin_knl) diff --git a/sysdeps/x86_64/fpu/multiarch/svml_d_sincos8_core_avx512.S b/sysdeps/x86_64/fpu/multiarch/svml_d_sincos8_core_avx512.S index f6297e0024..a05a900ede 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_d_sincos8_core_avx512.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_d_sincos8_core_avx512.S @@ -18,7 +18,7 @@ #include #include "svml_d_trig_data.h" -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" /* ALGORITHM DESCRIPTION: diff --git a/sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core_avx512.S b/sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core_avx512.S index b0612c9357..5929fc0203 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core_avx512.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_s_cosf16_core_avx512.S @@ -18,7 +18,7 @@ #include #include "svml_s_trig_data.h" -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVeN16v_cosf_knl) diff --git a/sysdeps/x86_64/fpu/multiarch/svml_s_expf16_core_avx512.S b/sysdeps/x86_64/fpu/multiarch/svml_s_expf16_core_avx512.S index 599b67f83b..71ed573a6e 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_s_expf16_core_avx512.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_s_expf16_core_avx512.S @@ -18,7 +18,7 @@ #include #include "svml_s_expf_data.h" -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVeN16v_expf_knl) diff --git a/sysdeps/x86_64/fpu/multiarch/svml_s_logf16_core_avx512.S b/sysdeps/x86_64/fpu/multiarch/svml_s_logf16_core_avx512.S index 0070b0c419..b0062a1eb5 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_s_logf16_core_avx512.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_s_logf16_core_avx512.S @@ -18,7 +18,7 @@ #include #include "svml_s_logf_data.h" -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVeN16v_logf_knl) diff --git a/sysdeps/x86_64/fpu/multiarch/svml_s_powf16_core_avx512.S b/sysdeps/x86_64/fpu/multiarch/svml_s_powf16_core_avx512.S index 306895838b..c05960bc31 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_s_powf16_core_avx512.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_s_powf16_core_avx512.S @@ -18,7 +18,7 @@ #include #include "svml_s_powf_data.h" -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" /* ALGORITHM DESCRIPTION: diff --git a/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf16_core_avx512.S b/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf16_core_avx512.S index 9a2aebb023..9ab6af69be 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf16_core_avx512.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_s_sincosf16_core_avx512.S @@ -18,7 +18,7 @@ #include #include "svml_s_trig_data.h" -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" /* ALGORITHM DESCRIPTION: diff --git a/sysdeps/x86_64/fpu/multiarch/svml_s_sinf16_core_avx512.S b/sysdeps/x86_64/fpu/multiarch/svml_s_sinf16_core_avx512.S index 33b210fac0..0c037fd663 100644 --- a/sysdeps/x86_64/fpu/multiarch/svml_s_sinf16_core_avx512.S +++ b/sysdeps/x86_64/fpu/multiarch/svml_s_sinf16_core_avx512.S @@ -18,7 +18,7 @@ #include #include "svml_s_trig_data.h" -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY(_ZGVeN16v_sinf_knl) diff --git a/sysdeps/x86_64/fpu/svml_d_acos2_core.S b/sysdeps/x86_64/fpu/svml_d_acos2_core.S index 8c573fcff1..1022d7e4e7 100644 --- a/sysdeps/x86_64/fpu/svml_d_acos2_core.S +++ b/sysdeps/x86_64/fpu/svml_d_acos2_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVbN2v_acos) diff --git a/sysdeps/x86_64/fpu/svml_d_acos4_core.S b/sysdeps/x86_64/fpu/svml_d_acos4_core.S index ef2253f3dd..b4a8990f5a 100644 --- a/sysdeps/x86_64/fpu/svml_d_acos4_core.S +++ b/sysdeps/x86_64/fpu/svml_d_acos4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVdN4v_acos) diff --git a/sysdeps/x86_64/fpu/svml_d_acos4_core_avx.S b/sysdeps/x86_64/fpu/svml_d_acos4_core_avx.S index cc5377850c..48e610f4ef 100644 --- a/sysdeps/x86_64/fpu/svml_d_acos4_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_d_acos4_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVcN4v_acos) diff --git a/sysdeps/x86_64/fpu/svml_d_acos8_core.S b/sysdeps/x86_64/fpu/svml_d_acos8_core.S index 3bf8d8dcdf..8f8017a72d 100644 --- a/sysdeps/x86_64/fpu/svml_d_acos8_core.S +++ b/sysdeps/x86_64/fpu/svml_d_acos8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVeN8v_acos) diff --git a/sysdeps/x86_64/fpu/svml_d_acosh2_core.S b/sysdeps/x86_64/fpu/svml_d_acosh2_core.S index ab92795d13..23d22de0fe 100644 --- a/sysdeps/x86_64/fpu/svml_d_acosh2_core.S +++ b/sysdeps/x86_64/fpu/svml_d_acosh2_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVbN2v_acosh) diff --git a/sysdeps/x86_64/fpu/svml_d_acosh4_core.S b/sysdeps/x86_64/fpu/svml_d_acosh4_core.S index 91ff3018c1..5bef8065f7 100644 --- a/sysdeps/x86_64/fpu/svml_d_acosh4_core.S +++ b/sysdeps/x86_64/fpu/svml_d_acosh4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVdN4v_acosh) diff --git a/sysdeps/x86_64/fpu/svml_d_acosh4_core_avx.S b/sysdeps/x86_64/fpu/svml_d_acosh4_core_avx.S index 84cbe5871c..95dd9ed670 100644 --- a/sysdeps/x86_64/fpu/svml_d_acosh4_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_d_acosh4_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVcN4v_acosh) diff --git a/sysdeps/x86_64/fpu/svml_d_acosh8_core.S b/sysdeps/x86_64/fpu/svml_d_acosh8_core.S index 0b4521ce64..6277eebc1e 100644 --- a/sysdeps/x86_64/fpu/svml_d_acosh8_core.S +++ b/sysdeps/x86_64/fpu/svml_d_acosh8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVeN8v_acosh) diff --git a/sysdeps/x86_64/fpu/svml_d_asin2_core.S b/sysdeps/x86_64/fpu/svml_d_asin2_core.S index 911625030f..13c186ac08 100644 --- a/sysdeps/x86_64/fpu/svml_d_asin2_core.S +++ b/sysdeps/x86_64/fpu/svml_d_asin2_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVbN2v_asin) diff --git a/sysdeps/x86_64/fpu/svml_d_asin4_core.S b/sysdeps/x86_64/fpu/svml_d_asin4_core.S index 222a0b8f73..50ea5a4207 100644 --- a/sysdeps/x86_64/fpu/svml_d_asin4_core.S +++ b/sysdeps/x86_64/fpu/svml_d_asin4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVdN4v_asin) diff --git a/sysdeps/x86_64/fpu/svml_d_asin4_core_avx.S b/sysdeps/x86_64/fpu/svml_d_asin4_core_avx.S index 04ff322ea6..6de73c97cf 100644 --- a/sysdeps/x86_64/fpu/svml_d_asin4_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_d_asin4_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVcN4v_asin) diff --git a/sysdeps/x86_64/fpu/svml_d_asin8_core.S b/sysdeps/x86_64/fpu/svml_d_asin8_core.S index bea94b954c..aaf93dc8e9 100644 --- a/sysdeps/x86_64/fpu/svml_d_asin8_core.S +++ b/sysdeps/x86_64/fpu/svml_d_asin8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVeN8v_asin) diff --git a/sysdeps/x86_64/fpu/svml_d_asinh2_core.S b/sysdeps/x86_64/fpu/svml_d_asinh2_core.S index a621fae3fb..00723458e4 100644 --- a/sysdeps/x86_64/fpu/svml_d_asinh2_core.S +++ b/sysdeps/x86_64/fpu/svml_d_asinh2_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVbN2v_asinh) diff --git a/sysdeps/x86_64/fpu/svml_d_asinh4_core.S b/sysdeps/x86_64/fpu/svml_d_asinh4_core.S index a0332eca57..f2e13c3a0a 100644 --- a/sysdeps/x86_64/fpu/svml_d_asinh4_core.S +++ b/sysdeps/x86_64/fpu/svml_d_asinh4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVdN4v_asinh) diff --git a/sysdeps/x86_64/fpu/svml_d_asinh4_core_avx.S b/sysdeps/x86_64/fpu/svml_d_asinh4_core_avx.S index bc365d7dd7..51324b697f 100644 --- a/sysdeps/x86_64/fpu/svml_d_asinh4_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_d_asinh4_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVcN4v_asinh) diff --git a/sysdeps/x86_64/fpu/svml_d_asinh8_core.S b/sysdeps/x86_64/fpu/svml_d_asinh8_core.S index 2271466d99..3c32741b39 100644 --- a/sysdeps/x86_64/fpu/svml_d_asinh8_core.S +++ b/sysdeps/x86_64/fpu/svml_d_asinh8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVeN8v_asinh) diff --git a/sysdeps/x86_64/fpu/svml_d_atan22_core.S b/sysdeps/x86_64/fpu/svml_d_atan22_core.S index 7f40f1be6f..6b3cef4269 100644 --- a/sysdeps/x86_64/fpu/svml_d_atan22_core.S +++ b/sysdeps/x86_64/fpu/svml_d_atan22_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVbN2vv_atan2) diff --git a/sysdeps/x86_64/fpu/svml_d_atan24_core.S b/sysdeps/x86_64/fpu/svml_d_atan24_core.S index afb8296d80..7f76bf166c 100644 --- a/sysdeps/x86_64/fpu/svml_d_atan24_core.S +++ b/sysdeps/x86_64/fpu/svml_d_atan24_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVdN4vv_atan2) diff --git a/sysdeps/x86_64/fpu/svml_d_atan24_core_avx.S b/sysdeps/x86_64/fpu/svml_d_atan24_core_avx.S index 81db9cd297..7e8fead6e0 100644 --- a/sysdeps/x86_64/fpu/svml_d_atan24_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_d_atan24_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVcN4vv_atan2) diff --git a/sysdeps/x86_64/fpu/svml_d_atan28_core.S b/sysdeps/x86_64/fpu/svml_d_atan28_core.S index 9c25de34b6..2c710eadac 100644 --- a/sysdeps/x86_64/fpu/svml_d_atan28_core.S +++ b/sysdeps/x86_64/fpu/svml_d_atan28_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVeN8vv_atan2) diff --git a/sysdeps/x86_64/fpu/svml_d_atan2_core.S b/sysdeps/x86_64/fpu/svml_d_atan2_core.S index bd4020ab69..7ea434fec5 100644 --- a/sysdeps/x86_64/fpu/svml_d_atan2_core.S +++ b/sysdeps/x86_64/fpu/svml_d_atan2_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVbN2v_atan) diff --git a/sysdeps/x86_64/fpu/svml_d_atan4_core.S b/sysdeps/x86_64/fpu/svml_d_atan4_core.S index 89737790f4..06e3e2a870 100644 --- a/sysdeps/x86_64/fpu/svml_d_atan4_core.S +++ b/sysdeps/x86_64/fpu/svml_d_atan4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVdN4v_atan) diff --git a/sysdeps/x86_64/fpu/svml_d_atan4_core_avx.S b/sysdeps/x86_64/fpu/svml_d_atan4_core_avx.S index 8abe407abe..73a8ab8ebb 100644 --- a/sysdeps/x86_64/fpu/svml_d_atan4_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_d_atan4_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVcN4v_atan) diff --git a/sysdeps/x86_64/fpu/svml_d_atan8_core.S b/sysdeps/x86_64/fpu/svml_d_atan8_core.S index cea8caf797..dfb6f788bc 100644 --- a/sysdeps/x86_64/fpu/svml_d_atan8_core.S +++ b/sysdeps/x86_64/fpu/svml_d_atan8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVeN8v_atan) diff --git a/sysdeps/x86_64/fpu/svml_d_atanh2_core.S b/sysdeps/x86_64/fpu/svml_d_atanh2_core.S index 8c300fbc09..f112f43793 100644 --- a/sysdeps/x86_64/fpu/svml_d_atanh2_core.S +++ b/sysdeps/x86_64/fpu/svml_d_atanh2_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVbN2v_atanh) diff --git a/sysdeps/x86_64/fpu/svml_d_atanh4_core.S b/sysdeps/x86_64/fpu/svml_d_atanh4_core.S index df63d2d655..ba74bcfeb5 100644 --- a/sysdeps/x86_64/fpu/svml_d_atanh4_core.S +++ b/sysdeps/x86_64/fpu/svml_d_atanh4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVdN4v_atanh) diff --git a/sysdeps/x86_64/fpu/svml_d_atanh4_core_avx.S b/sysdeps/x86_64/fpu/svml_d_atanh4_core_avx.S index 0bb51b2d60..9d1fa7f8c7 100644 --- a/sysdeps/x86_64/fpu/svml_d_atanh4_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_d_atanh4_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVcN4v_atanh) diff --git a/sysdeps/x86_64/fpu/svml_d_atanh8_core.S b/sysdeps/x86_64/fpu/svml_d_atanh8_core.S index 956230e978..24011dad24 100644 --- a/sysdeps/x86_64/fpu/svml_d_atanh8_core.S +++ b/sysdeps/x86_64/fpu/svml_d_atanh8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVeN8v_atanh) diff --git a/sysdeps/x86_64/fpu/svml_d_cbrt2_core.S b/sysdeps/x86_64/fpu/svml_d_cbrt2_core.S index 5ca1129c7f..3a3152000b 100644 --- a/sysdeps/x86_64/fpu/svml_d_cbrt2_core.S +++ b/sysdeps/x86_64/fpu/svml_d_cbrt2_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVbN2v_cbrt) diff --git a/sysdeps/x86_64/fpu/svml_d_cbrt4_core.S b/sysdeps/x86_64/fpu/svml_d_cbrt4_core.S index c3948ec480..31e0bc46db 100644 --- a/sysdeps/x86_64/fpu/svml_d_cbrt4_core.S +++ b/sysdeps/x86_64/fpu/svml_d_cbrt4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVdN4v_cbrt) diff --git a/sysdeps/x86_64/fpu/svml_d_cbrt4_core_avx.S b/sysdeps/x86_64/fpu/svml_d_cbrt4_core_avx.S index b64825e876..8b4122c7ad 100644 --- a/sysdeps/x86_64/fpu/svml_d_cbrt4_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_d_cbrt4_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVcN4v_cbrt) diff --git a/sysdeps/x86_64/fpu/svml_d_cbrt8_core.S b/sysdeps/x86_64/fpu/svml_d_cbrt8_core.S index 312f015706..0aac584981 100644 --- a/sysdeps/x86_64/fpu/svml_d_cbrt8_core.S +++ b/sysdeps/x86_64/fpu/svml_d_cbrt8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVeN8v_cbrt) diff --git a/sysdeps/x86_64/fpu/svml_d_cos2_core.S b/sysdeps/x86_64/fpu/svml_d_cos2_core.S index 02a6583776..d2ea460b50 100644 --- a/sysdeps/x86_64/fpu/svml_d_cos2_core.S +++ b/sysdeps/x86_64/fpu/svml_d_cos2_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVbN2v_cos) diff --git a/sysdeps/x86_64/fpu/svml_d_cos4_core.S b/sysdeps/x86_64/fpu/svml_d_cos4_core.S index f066ceaf4c..1f09e366c2 100644 --- a/sysdeps/x86_64/fpu/svml_d_cos4_core.S +++ b/sysdeps/x86_64/fpu/svml_d_cos4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVdN4v_cos) diff --git a/sysdeps/x86_64/fpu/svml_d_cos4_core_avx.S b/sysdeps/x86_64/fpu/svml_d_cos4_core_avx.S index 5212078c9c..e96205ec00 100644 --- a/sysdeps/x86_64/fpu/svml_d_cos4_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_d_cos4_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVcN4v_cos) diff --git a/sysdeps/x86_64/fpu/svml_d_cos8_core.S b/sysdeps/x86_64/fpu/svml_d_cos8_core.S index 2ac8e4687a..ef3c7a0a71 100644 --- a/sysdeps/x86_64/fpu/svml_d_cos8_core.S +++ b/sysdeps/x86_64/fpu/svml_d_cos8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVeN8v_cos) diff --git a/sysdeps/x86_64/fpu/svml_d_cosh2_core.S b/sysdeps/x86_64/fpu/svml_d_cosh2_core.S index 6aa76d40ed..55b4ae267b 100644 --- a/sysdeps/x86_64/fpu/svml_d_cosh2_core.S +++ b/sysdeps/x86_64/fpu/svml_d_cosh2_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVbN2v_cosh) diff --git a/sysdeps/x86_64/fpu/svml_d_cosh4_core.S b/sysdeps/x86_64/fpu/svml_d_cosh4_core.S index d3a7bec3f4..9a99bd3fab 100644 --- a/sysdeps/x86_64/fpu/svml_d_cosh4_core.S +++ b/sysdeps/x86_64/fpu/svml_d_cosh4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVdN4v_cosh) diff --git a/sysdeps/x86_64/fpu/svml_d_cosh4_core_avx.S b/sysdeps/x86_64/fpu/svml_d_cosh4_core_avx.S index 73612e33bc..8a514c8790 100644 --- a/sysdeps/x86_64/fpu/svml_d_cosh4_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_d_cosh4_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVcN4v_cosh) diff --git a/sysdeps/x86_64/fpu/svml_d_cosh8_core.S b/sysdeps/x86_64/fpu/svml_d_cosh8_core.S index e89d2c23fb..35ab7f6ee9 100644 --- a/sysdeps/x86_64/fpu/svml_d_cosh8_core.S +++ b/sysdeps/x86_64/fpu/svml_d_cosh8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVeN8v_cosh) diff --git a/sysdeps/x86_64/fpu/svml_d_erf2_core.S b/sysdeps/x86_64/fpu/svml_d_erf2_core.S index 828dd59cb3..0622c3caac 100644 --- a/sysdeps/x86_64/fpu/svml_d_erf2_core.S +++ b/sysdeps/x86_64/fpu/svml_d_erf2_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVbN2v_erf) diff --git a/sysdeps/x86_64/fpu/svml_d_erf4_core.S b/sysdeps/x86_64/fpu/svml_d_erf4_core.S index 9432824d8a..6f95c5feef 100644 --- a/sysdeps/x86_64/fpu/svml_d_erf4_core.S +++ b/sysdeps/x86_64/fpu/svml_d_erf4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVdN4v_erf) diff --git a/sysdeps/x86_64/fpu/svml_d_erf4_core_avx.S b/sysdeps/x86_64/fpu/svml_d_erf4_core_avx.S index e3f73f9044..4815f8468a 100644 --- a/sysdeps/x86_64/fpu/svml_d_erf4_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_d_erf4_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVcN4v_erf) diff --git a/sysdeps/x86_64/fpu/svml_d_erf8_core.S b/sysdeps/x86_64/fpu/svml_d_erf8_core.S index fde688f5dd..079f423284 100644 --- a/sysdeps/x86_64/fpu/svml_d_erf8_core.S +++ b/sysdeps/x86_64/fpu/svml_d_erf8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVeN8v_erf) diff --git a/sysdeps/x86_64/fpu/svml_d_erfc2_core.S b/sysdeps/x86_64/fpu/svml_d_erfc2_core.S index 530d358b8b..cb239f82e8 100644 --- a/sysdeps/x86_64/fpu/svml_d_erfc2_core.S +++ b/sysdeps/x86_64/fpu/svml_d_erfc2_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVbN2v_erfc) diff --git a/sysdeps/x86_64/fpu/svml_d_erfc4_core.S b/sysdeps/x86_64/fpu/svml_d_erfc4_core.S index c6b3e2c367..2b42b3af83 100644 --- a/sysdeps/x86_64/fpu/svml_d_erfc4_core.S +++ b/sysdeps/x86_64/fpu/svml_d_erfc4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVdN4v_erfc) diff --git a/sysdeps/x86_64/fpu/svml_d_erfc4_core_avx.S b/sysdeps/x86_64/fpu/svml_d_erfc4_core_avx.S index e81ca48897..9e16bf2ec5 100644 --- a/sysdeps/x86_64/fpu/svml_d_erfc4_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_d_erfc4_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVcN4v_erfc) diff --git a/sysdeps/x86_64/fpu/svml_d_erfc8_core.S b/sysdeps/x86_64/fpu/svml_d_erfc8_core.S index b3d31fec27..f781a7af9a 100644 --- a/sysdeps/x86_64/fpu/svml_d_erfc8_core.S +++ b/sysdeps/x86_64/fpu/svml_d_erfc8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVeN8v_erfc) diff --git a/sysdeps/x86_64/fpu/svml_d_exp102_core.S b/sysdeps/x86_64/fpu/svml_d_exp102_core.S index 8e6131d717..d6d7da6fec 100644 --- a/sysdeps/x86_64/fpu/svml_d_exp102_core.S +++ b/sysdeps/x86_64/fpu/svml_d_exp102_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVbN2v_exp10) diff --git a/sysdeps/x86_64/fpu/svml_d_exp104_core.S b/sysdeps/x86_64/fpu/svml_d_exp104_core.S index e226bb88bb..e0c651f904 100644 --- a/sysdeps/x86_64/fpu/svml_d_exp104_core.S +++ b/sysdeps/x86_64/fpu/svml_d_exp104_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVdN4v_exp10) diff --git a/sysdeps/x86_64/fpu/svml_d_exp104_core_avx.S b/sysdeps/x86_64/fpu/svml_d_exp104_core_avx.S index 8758d35449..ca3931eb8b 100644 --- a/sysdeps/x86_64/fpu/svml_d_exp104_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_d_exp104_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVcN4v_exp10) diff --git a/sysdeps/x86_64/fpu/svml_d_exp108_core.S b/sysdeps/x86_64/fpu/svml_d_exp108_core.S index 745d3c7ec7..ad2ba994c0 100644 --- a/sysdeps/x86_64/fpu/svml_d_exp108_core.S +++ b/sysdeps/x86_64/fpu/svml_d_exp108_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVeN8v_exp10) diff --git a/sysdeps/x86_64/fpu/svml_d_exp22_core.S b/sysdeps/x86_64/fpu/svml_d_exp22_core.S index 3639892544..4205e5510d 100644 --- a/sysdeps/x86_64/fpu/svml_d_exp22_core.S +++ b/sysdeps/x86_64/fpu/svml_d_exp22_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVbN2v_exp2) diff --git a/sysdeps/x86_64/fpu/svml_d_exp24_core.S b/sysdeps/x86_64/fpu/svml_d_exp24_core.S index aea3afc3e3..4be1ee4e48 100644 --- a/sysdeps/x86_64/fpu/svml_d_exp24_core.S +++ b/sysdeps/x86_64/fpu/svml_d_exp24_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVdN4v_exp2) diff --git a/sysdeps/x86_64/fpu/svml_d_exp24_core_avx.S b/sysdeps/x86_64/fpu/svml_d_exp24_core_avx.S index 68f28b8f63..b09da67af1 100644 --- a/sysdeps/x86_64/fpu/svml_d_exp24_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_d_exp24_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVcN4v_exp2) diff --git a/sysdeps/x86_64/fpu/svml_d_exp28_core.S b/sysdeps/x86_64/fpu/svml_d_exp28_core.S index dc0b3e77d0..0e8e027713 100644 --- a/sysdeps/x86_64/fpu/svml_d_exp28_core.S +++ b/sysdeps/x86_64/fpu/svml_d_exp28_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVeN8v_exp2) diff --git a/sysdeps/x86_64/fpu/svml_d_exp2_core.S b/sysdeps/x86_64/fpu/svml_d_exp2_core.S index 14e41b9707..15109ef829 100644 --- a/sysdeps/x86_64/fpu/svml_d_exp2_core.S +++ b/sysdeps/x86_64/fpu/svml_d_exp2_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVbN2v_exp) diff --git a/sysdeps/x86_64/fpu/svml_d_exp4_core.S b/sysdeps/x86_64/fpu/svml_d_exp4_core.S index cf91c08ab4..de35ab001f 100644 --- a/sysdeps/x86_64/fpu/svml_d_exp4_core.S +++ b/sysdeps/x86_64/fpu/svml_d_exp4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVdN4v_exp) diff --git a/sysdeps/x86_64/fpu/svml_d_exp4_core_avx.S b/sysdeps/x86_64/fpu/svml_d_exp4_core_avx.S index b1ed2bc0ae..452558041c 100644 --- a/sysdeps/x86_64/fpu/svml_d_exp4_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_d_exp4_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVcN4v_exp) diff --git a/sysdeps/x86_64/fpu/svml_d_exp8_core.S b/sysdeps/x86_64/fpu/svml_d_exp8_core.S index ef7d62c1ec..88e663fa9b 100644 --- a/sysdeps/x86_64/fpu/svml_d_exp8_core.S +++ b/sysdeps/x86_64/fpu/svml_d_exp8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVeN8v_exp) diff --git a/sysdeps/x86_64/fpu/svml_d_expm12_core.S b/sysdeps/x86_64/fpu/svml_d_expm12_core.S index b5bfd598a8..315d12e2e9 100644 --- a/sysdeps/x86_64/fpu/svml_d_expm12_core.S +++ b/sysdeps/x86_64/fpu/svml_d_expm12_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVbN2v_expm1) diff --git a/sysdeps/x86_64/fpu/svml_d_expm14_core.S b/sysdeps/x86_64/fpu/svml_d_expm14_core.S index 1986f086ff..902a85bd4a 100644 --- a/sysdeps/x86_64/fpu/svml_d_expm14_core.S +++ b/sysdeps/x86_64/fpu/svml_d_expm14_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVdN4v_expm1) diff --git a/sysdeps/x86_64/fpu/svml_d_expm14_core_avx.S b/sysdeps/x86_64/fpu/svml_d_expm14_core_avx.S index 333a7011ae..f8f7d15759 100644 --- a/sysdeps/x86_64/fpu/svml_d_expm14_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_d_expm14_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVcN4v_expm1) diff --git a/sysdeps/x86_64/fpu/svml_d_expm18_core.S b/sysdeps/x86_64/fpu/svml_d_expm18_core.S index d008c4273d..513688ebf5 100644 --- a/sysdeps/x86_64/fpu/svml_d_expm18_core.S +++ b/sysdeps/x86_64/fpu/svml_d_expm18_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVeN8v_expm1) diff --git a/sysdeps/x86_64/fpu/svml_d_hypot2_core.S b/sysdeps/x86_64/fpu/svml_d_hypot2_core.S index 6532e46a8b..c746560128 100644 --- a/sysdeps/x86_64/fpu/svml_d_hypot2_core.S +++ b/sysdeps/x86_64/fpu/svml_d_hypot2_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVbN2vv_hypot) diff --git a/sysdeps/x86_64/fpu/svml_d_hypot4_core.S b/sysdeps/x86_64/fpu/svml_d_hypot4_core.S index 1383ac5304..aa1e2b330b 100644 --- a/sysdeps/x86_64/fpu/svml_d_hypot4_core.S +++ b/sysdeps/x86_64/fpu/svml_d_hypot4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVdN4vv_hypot) diff --git a/sysdeps/x86_64/fpu/svml_d_hypot4_core_avx.S b/sysdeps/x86_64/fpu/svml_d_hypot4_core_avx.S index 6b1b165a2c..7028c55eab 100644 --- a/sysdeps/x86_64/fpu/svml_d_hypot4_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_d_hypot4_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVcN4vv_hypot) diff --git a/sysdeps/x86_64/fpu/svml_d_hypot8_core.S b/sysdeps/x86_64/fpu/svml_d_hypot8_core.S index ec73ba6184..10c831fd08 100644 --- a/sysdeps/x86_64/fpu/svml_d_hypot8_core.S +++ b/sysdeps/x86_64/fpu/svml_d_hypot8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVeN8vv_hypot) diff --git a/sysdeps/x86_64/fpu/svml_d_log102_core.S b/sysdeps/x86_64/fpu/svml_d_log102_core.S index 9e0aa00f7e..a63e82bdbc 100644 --- a/sysdeps/x86_64/fpu/svml_d_log102_core.S +++ b/sysdeps/x86_64/fpu/svml_d_log102_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVbN2v_log10) diff --git a/sysdeps/x86_64/fpu/svml_d_log104_core.S b/sysdeps/x86_64/fpu/svml_d_log104_core.S index cc5e285dee..051ad8284a 100644 --- a/sysdeps/x86_64/fpu/svml_d_log104_core.S +++ b/sysdeps/x86_64/fpu/svml_d_log104_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVdN4v_log10) diff --git a/sysdeps/x86_64/fpu/svml_d_log104_core_avx.S b/sysdeps/x86_64/fpu/svml_d_log104_core_avx.S index ea1cb93a9d..f08b78e35e 100644 --- a/sysdeps/x86_64/fpu/svml_d_log104_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_d_log104_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVcN4v_log10) diff --git a/sysdeps/x86_64/fpu/svml_d_log108_core.S b/sysdeps/x86_64/fpu/svml_d_log108_core.S index 59d5835cc7..8b5a59cf00 100644 --- a/sysdeps/x86_64/fpu/svml_d_log108_core.S +++ b/sysdeps/x86_64/fpu/svml_d_log108_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVeN8v_log10) diff --git a/sysdeps/x86_64/fpu/svml_d_log1p2_core.S b/sysdeps/x86_64/fpu/svml_d_log1p2_core.S index b40e238e11..058e6d47da 100644 --- a/sysdeps/x86_64/fpu/svml_d_log1p2_core.S +++ b/sysdeps/x86_64/fpu/svml_d_log1p2_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVbN2v_log1p) diff --git a/sysdeps/x86_64/fpu/svml_d_log1p4_core.S b/sysdeps/x86_64/fpu/svml_d_log1p4_core.S index 2c76849ca8..7c27ab9a5c 100644 --- a/sysdeps/x86_64/fpu/svml_d_log1p4_core.S +++ b/sysdeps/x86_64/fpu/svml_d_log1p4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVdN4v_log1p) diff --git a/sysdeps/x86_64/fpu/svml_d_log1p4_core_avx.S b/sysdeps/x86_64/fpu/svml_d_log1p4_core_avx.S index 42ace645e7..8b0b20f018 100644 --- a/sysdeps/x86_64/fpu/svml_d_log1p4_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_d_log1p4_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVcN4v_log1p) diff --git a/sysdeps/x86_64/fpu/svml_d_log1p8_core.S b/sysdeps/x86_64/fpu/svml_d_log1p8_core.S index cca39f1847..1c6be998d7 100644 --- a/sysdeps/x86_64/fpu/svml_d_log1p8_core.S +++ b/sysdeps/x86_64/fpu/svml_d_log1p8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVeN8v_log1p) diff --git a/sysdeps/x86_64/fpu/svml_d_log22_core.S b/sysdeps/x86_64/fpu/svml_d_log22_core.S index 8c8464b2f8..5e998a38e1 100644 --- a/sysdeps/x86_64/fpu/svml_d_log22_core.S +++ b/sysdeps/x86_64/fpu/svml_d_log22_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVbN2v_log2) diff --git a/sysdeps/x86_64/fpu/svml_d_log24_core.S b/sysdeps/x86_64/fpu/svml_d_log24_core.S index b75936f785..b2c3c4a727 100644 --- a/sysdeps/x86_64/fpu/svml_d_log24_core.S +++ b/sysdeps/x86_64/fpu/svml_d_log24_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVdN4v_log2) diff --git a/sysdeps/x86_64/fpu/svml_d_log24_core_avx.S b/sysdeps/x86_64/fpu/svml_d_log24_core_avx.S index f4a946033f..eaeee60be5 100644 --- a/sysdeps/x86_64/fpu/svml_d_log24_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_d_log24_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVcN4v_log2) diff --git a/sysdeps/x86_64/fpu/svml_d_log28_core.S b/sysdeps/x86_64/fpu/svml_d_log28_core.S index e547d8431b..e81a0d27d7 100644 --- a/sysdeps/x86_64/fpu/svml_d_log28_core.S +++ b/sysdeps/x86_64/fpu/svml_d_log28_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVeN8v_log2) diff --git a/sysdeps/x86_64/fpu/svml_d_log2_core.S b/sysdeps/x86_64/fpu/svml_d_log2_core.S index 1e9790d78c..e38d58d465 100644 --- a/sysdeps/x86_64/fpu/svml_d_log2_core.S +++ b/sysdeps/x86_64/fpu/svml_d_log2_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVbN2v_log) diff --git a/sysdeps/x86_64/fpu/svml_d_log4_core.S b/sysdeps/x86_64/fpu/svml_d_log4_core.S index cac601bb62..ab2801d343 100644 --- a/sysdeps/x86_64/fpu/svml_d_log4_core.S +++ b/sysdeps/x86_64/fpu/svml_d_log4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVdN4v_log) diff --git a/sysdeps/x86_64/fpu/svml_d_log4_core_avx.S b/sysdeps/x86_64/fpu/svml_d_log4_core_avx.S index f769844917..ace1ac535a 100644 --- a/sysdeps/x86_64/fpu/svml_d_log4_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_d_log4_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVcN4v_log) diff --git a/sysdeps/x86_64/fpu/svml_d_log8_core.S b/sysdeps/x86_64/fpu/svml_d_log8_core.S index 56284de286..37c0bcce11 100644 --- a/sysdeps/x86_64/fpu/svml_d_log8_core.S +++ b/sysdeps/x86_64/fpu/svml_d_log8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVeN8v_log) diff --git a/sysdeps/x86_64/fpu/svml_d_pow2_core.S b/sysdeps/x86_64/fpu/svml_d_pow2_core.S index f8cf580f76..7142d6ece4 100644 --- a/sysdeps/x86_64/fpu/svml_d_pow2_core.S +++ b/sysdeps/x86_64/fpu/svml_d_pow2_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVbN2vv_pow) diff --git a/sysdeps/x86_64/fpu/svml_d_pow4_core.S b/sysdeps/x86_64/fpu/svml_d_pow4_core.S index 4cf403230d..572ba50519 100644 --- a/sysdeps/x86_64/fpu/svml_d_pow4_core.S +++ b/sysdeps/x86_64/fpu/svml_d_pow4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVdN4vv_pow) diff --git a/sysdeps/x86_64/fpu/svml_d_pow4_core_avx.S b/sysdeps/x86_64/fpu/svml_d_pow4_core_avx.S index f72e9532f3..e8f7c56d82 100644 --- a/sysdeps/x86_64/fpu/svml_d_pow4_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_d_pow4_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVcN4vv_pow) diff --git a/sysdeps/x86_64/fpu/svml_d_pow8_core.S b/sysdeps/x86_64/fpu/svml_d_pow8_core.S index 0b99cf6570..3f7d63cad0 100644 --- a/sysdeps/x86_64/fpu/svml_d_pow8_core.S +++ b/sysdeps/x86_64/fpu/svml_d_pow8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVeN8vv_pow) diff --git a/sysdeps/x86_64/fpu/svml_d_sin2_core.S b/sysdeps/x86_64/fpu/svml_d_sin2_core.S index 40f23bf473..c101822478 100644 --- a/sysdeps/x86_64/fpu/svml_d_sin2_core.S +++ b/sysdeps/x86_64/fpu/svml_d_sin2_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVbN2v_sin) diff --git a/sysdeps/x86_64/fpu/svml_d_sin4_core.S b/sysdeps/x86_64/fpu/svml_d_sin4_core.S index f7c6e5de88..53464f52e0 100644 --- a/sysdeps/x86_64/fpu/svml_d_sin4_core.S +++ b/sysdeps/x86_64/fpu/svml_d_sin4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVdN4v_sin) diff --git a/sysdeps/x86_64/fpu/svml_d_sin4_core_avx.S b/sysdeps/x86_64/fpu/svml_d_sin4_core_avx.S index 694ac1977a..d291d020dc 100644 --- a/sysdeps/x86_64/fpu/svml_d_sin4_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_d_sin4_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVcN4v_sin) diff --git a/sysdeps/x86_64/fpu/svml_d_sin8_core.S b/sysdeps/x86_64/fpu/svml_d_sin8_core.S index c3c978a843..03dbf25620 100644 --- a/sysdeps/x86_64/fpu/svml_d_sin8_core.S +++ b/sysdeps/x86_64/fpu/svml_d_sin8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVeN8v_sin) diff --git a/sysdeps/x86_64/fpu/svml_d_sincos2_core.S b/sysdeps/x86_64/fpu/svml_d_sincos2_core.S index 617e206870..3e9f604ead 100644 --- a/sysdeps/x86_64/fpu/svml_d_sincos2_core.S +++ b/sysdeps/x86_64/fpu/svml_d_sincos2_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVbN2vl8l8_sincos) diff --git a/sysdeps/x86_64/fpu/svml_d_sincos4_core.S b/sysdeps/x86_64/fpu/svml_d_sincos4_core.S index 53d491102e..b20361129b 100644 --- a/sysdeps/x86_64/fpu/svml_d_sincos4_core.S +++ b/sysdeps/x86_64/fpu/svml_d_sincos4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVdN4vl8l8_sincos) diff --git a/sysdeps/x86_64/fpu/svml_d_sincos4_core_avx.S b/sysdeps/x86_64/fpu/svml_d_sincos4_core_avx.S index ef798926f3..242c812c7c 100644 --- a/sysdeps/x86_64/fpu/svml_d_sincos4_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_d_sincos4_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVcN4vl8l8_sincos) diff --git a/sysdeps/x86_64/fpu/svml_d_sincos8_core.S b/sysdeps/x86_64/fpu/svml_d_sincos8_core.S index d9ae0bedd0..6a39b7dbb4 100644 --- a/sysdeps/x86_64/fpu/svml_d_sincos8_core.S +++ b/sysdeps/x86_64/fpu/svml_d_sincos8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVeN8vl8l8_sincos) diff --git a/sysdeps/x86_64/fpu/svml_d_sinh2_core.S b/sysdeps/x86_64/fpu/svml_d_sinh2_core.S index 205ad3b582..ab96636d0e 100644 --- a/sysdeps/x86_64/fpu/svml_d_sinh2_core.S +++ b/sysdeps/x86_64/fpu/svml_d_sinh2_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVbN2v_sinh) diff --git a/sysdeps/x86_64/fpu/svml_d_sinh4_core.S b/sysdeps/x86_64/fpu/svml_d_sinh4_core.S index 8f8bc794d6..9017582a06 100644 --- a/sysdeps/x86_64/fpu/svml_d_sinh4_core.S +++ b/sysdeps/x86_64/fpu/svml_d_sinh4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVdN4v_sinh) diff --git a/sysdeps/x86_64/fpu/svml_d_sinh4_core_avx.S b/sysdeps/x86_64/fpu/svml_d_sinh4_core_avx.S index 771fb2cd78..71aeb8d84d 100644 --- a/sysdeps/x86_64/fpu/svml_d_sinh4_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_d_sinh4_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVcN4v_sinh) diff --git a/sysdeps/x86_64/fpu/svml_d_sinh8_core.S b/sysdeps/x86_64/fpu/svml_d_sinh8_core.S index 0279264b30..1dd49a9dbb 100644 --- a/sysdeps/x86_64/fpu/svml_d_sinh8_core.S +++ b/sysdeps/x86_64/fpu/svml_d_sinh8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVeN8v_sinh) diff --git a/sysdeps/x86_64/fpu/svml_d_tan2_core.S b/sysdeps/x86_64/fpu/svml_d_tan2_core.S index 6fdc334a40..f127f7819c 100644 --- a/sysdeps/x86_64/fpu/svml_d_tan2_core.S +++ b/sysdeps/x86_64/fpu/svml_d_tan2_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVbN2v_tan) diff --git a/sysdeps/x86_64/fpu/svml_d_tan4_core.S b/sysdeps/x86_64/fpu/svml_d_tan4_core.S index 50e5331768..c1325c0984 100644 --- a/sysdeps/x86_64/fpu/svml_d_tan4_core.S +++ b/sysdeps/x86_64/fpu/svml_d_tan4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVdN4v_tan) diff --git a/sysdeps/x86_64/fpu/svml_d_tan4_core_avx.S b/sysdeps/x86_64/fpu/svml_d_tan4_core_avx.S index e4b1f1ed93..0088977a95 100644 --- a/sysdeps/x86_64/fpu/svml_d_tan4_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_d_tan4_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVcN4v_tan) diff --git a/sysdeps/x86_64/fpu/svml_d_tan8_core.S b/sysdeps/x86_64/fpu/svml_d_tan8_core.S index fd26488470..b92659d894 100644 --- a/sysdeps/x86_64/fpu/svml_d_tan8_core.S +++ b/sysdeps/x86_64/fpu/svml_d_tan8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVeN8v_tan) diff --git a/sysdeps/x86_64/fpu/svml_d_tanh2_core.S b/sysdeps/x86_64/fpu/svml_d_tanh2_core.S index 1970e4622c..867adfaeef 100644 --- a/sysdeps/x86_64/fpu/svml_d_tanh2_core.S +++ b/sysdeps/x86_64/fpu/svml_d_tanh2_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVbN2v_tanh) diff --git a/sysdeps/x86_64/fpu/svml_d_tanh4_core.S b/sysdeps/x86_64/fpu/svml_d_tanh4_core.S index 1205efdec8..720539fa07 100644 --- a/sysdeps/x86_64/fpu/svml_d_tanh4_core.S +++ b/sysdeps/x86_64/fpu/svml_d_tanh4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVdN4v_tanh) diff --git a/sysdeps/x86_64/fpu/svml_d_tanh4_core_avx.S b/sysdeps/x86_64/fpu/svml_d_tanh4_core_avx.S index c42f63c865..270a76e495 100644 --- a/sysdeps/x86_64/fpu/svml_d_tanh4_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_d_tanh4_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVcN4v_tanh) diff --git a/sysdeps/x86_64/fpu/svml_d_tanh8_core.S b/sysdeps/x86_64/fpu/svml_d_tanh8_core.S index fe7c82370d..0ec89c2636 100644 --- a/sysdeps/x86_64/fpu/svml_d_tanh8_core.S +++ b/sysdeps/x86_64/fpu/svml_d_tanh8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_d_wrapper_impl.h" +#include "svml_d_wrapper_impl.h.S" .text ENTRY (_ZGVeN8v_tanh) diff --git a/sysdeps/x86_64/fpu/svml_d_wrapper_impl.h b/sysdeps/x86_64/fpu/svml_d_wrapper_impl.h.S similarity index 100% rename from sysdeps/x86_64/fpu/svml_d_wrapper_impl.h rename to sysdeps/x86_64/fpu/svml_d_wrapper_impl.h.S diff --git a/sysdeps/x86_64/fpu/svml_s_acosf16_core.S b/sysdeps/x86_64/fpu/svml_s_acosf16_core.S index 8dbe96d505..054713e328 100644 --- a/sysdeps/x86_64/fpu/svml_s_acosf16_core.S +++ b/sysdeps/x86_64/fpu/svml_s_acosf16_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVeN16v_acosf) diff --git a/sysdeps/x86_64/fpu/svml_s_acosf4_core.S b/sysdeps/x86_64/fpu/svml_s_acosf4_core.S index aeb82221f8..4160c34fb4 100644 --- a/sysdeps/x86_64/fpu/svml_s_acosf4_core.S +++ b/sysdeps/x86_64/fpu/svml_s_acosf4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVbN4v_acosf) diff --git a/sysdeps/x86_64/fpu/svml_s_acosf8_core.S b/sysdeps/x86_64/fpu/svml_s_acosf8_core.S index 189f81005e..8e2efc1146 100644 --- a/sysdeps/x86_64/fpu/svml_s_acosf8_core.S +++ b/sysdeps/x86_64/fpu/svml_s_acosf8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVdN8v_acosf) diff --git a/sysdeps/x86_64/fpu/svml_s_acosf8_core_avx.S b/sysdeps/x86_64/fpu/svml_s_acosf8_core_avx.S index fb432639ab..f0ee911cbe 100644 --- a/sysdeps/x86_64/fpu/svml_s_acosf8_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_s_acosf8_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVcN8v_acosf) diff --git a/sysdeps/x86_64/fpu/svml_s_acoshf16_core.S b/sysdeps/x86_64/fpu/svml_s_acoshf16_core.S index e5ece41ec6..391f1af733 100644 --- a/sysdeps/x86_64/fpu/svml_s_acoshf16_core.S +++ b/sysdeps/x86_64/fpu/svml_s_acoshf16_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVeN16v_acoshf) diff --git a/sysdeps/x86_64/fpu/svml_s_acoshf4_core.S b/sysdeps/x86_64/fpu/svml_s_acoshf4_core.S index d728e9f54f..ecb8705328 100644 --- a/sysdeps/x86_64/fpu/svml_s_acoshf4_core.S +++ b/sysdeps/x86_64/fpu/svml_s_acoshf4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVbN4v_acoshf) diff --git a/sysdeps/x86_64/fpu/svml_s_acoshf8_core.S b/sysdeps/x86_64/fpu/svml_s_acoshf8_core.S index 1f8352077e..cbac2627b7 100644 --- a/sysdeps/x86_64/fpu/svml_s_acoshf8_core.S +++ b/sysdeps/x86_64/fpu/svml_s_acoshf8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVdN8v_acoshf) diff --git a/sysdeps/x86_64/fpu/svml_s_acoshf8_core_avx.S b/sysdeps/x86_64/fpu/svml_s_acoshf8_core_avx.S index b9fc52c289..ead2bf3f2b 100644 --- a/sysdeps/x86_64/fpu/svml_s_acoshf8_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_s_acoshf8_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVcN8v_acoshf) diff --git a/sysdeps/x86_64/fpu/svml_s_asinf16_core.S b/sysdeps/x86_64/fpu/svml_s_asinf16_core.S index 54e947edd1..717d340b24 100644 --- a/sysdeps/x86_64/fpu/svml_s_asinf16_core.S +++ b/sysdeps/x86_64/fpu/svml_s_asinf16_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVeN16v_asinf) diff --git a/sysdeps/x86_64/fpu/svml_s_asinf4_core.S b/sysdeps/x86_64/fpu/svml_s_asinf4_core.S index 10bddc352b..6b94efd9d3 100644 --- a/sysdeps/x86_64/fpu/svml_s_asinf4_core.S +++ b/sysdeps/x86_64/fpu/svml_s_asinf4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVbN4v_asinf) diff --git a/sysdeps/x86_64/fpu/svml_s_asinf8_core.S b/sysdeps/x86_64/fpu/svml_s_asinf8_core.S index 77f4d83a2c..4e490cbd5f 100644 --- a/sysdeps/x86_64/fpu/svml_s_asinf8_core.S +++ b/sysdeps/x86_64/fpu/svml_s_asinf8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVdN8v_asinf) diff --git a/sysdeps/x86_64/fpu/svml_s_asinf8_core_avx.S b/sysdeps/x86_64/fpu/svml_s_asinf8_core_avx.S index 6202b4d4cf..cde5528197 100644 --- a/sysdeps/x86_64/fpu/svml_s_asinf8_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_s_asinf8_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVcN8v_asinf) diff --git a/sysdeps/x86_64/fpu/svml_s_asinhf16_core.S b/sysdeps/x86_64/fpu/svml_s_asinhf16_core.S index 16de57456e..ffb49184f7 100644 --- a/sysdeps/x86_64/fpu/svml_s_asinhf16_core.S +++ b/sysdeps/x86_64/fpu/svml_s_asinhf16_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVeN16v_asinhf) diff --git a/sysdeps/x86_64/fpu/svml_s_asinhf4_core.S b/sysdeps/x86_64/fpu/svml_s_asinhf4_core.S index 07dacc599f..ad4acbbd66 100644 --- a/sysdeps/x86_64/fpu/svml_s_asinhf4_core.S +++ b/sysdeps/x86_64/fpu/svml_s_asinhf4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVbN4v_asinhf) diff --git a/sysdeps/x86_64/fpu/svml_s_asinhf8_core.S b/sysdeps/x86_64/fpu/svml_s_asinhf8_core.S index b874f4256b..41a1527162 100644 --- a/sysdeps/x86_64/fpu/svml_s_asinhf8_core.S +++ b/sysdeps/x86_64/fpu/svml_s_asinhf8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVdN8v_asinhf) diff --git a/sysdeps/x86_64/fpu/svml_s_asinhf8_core_avx.S b/sysdeps/x86_64/fpu/svml_s_asinhf8_core_avx.S index b00a52e005..44607cd889 100644 --- a/sysdeps/x86_64/fpu/svml_s_asinhf8_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_s_asinhf8_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVcN8v_asinhf) diff --git a/sysdeps/x86_64/fpu/svml_s_atan2f16_core.S b/sysdeps/x86_64/fpu/svml_s_atan2f16_core.S index 345792d376..612b5af828 100644 --- a/sysdeps/x86_64/fpu/svml_s_atan2f16_core.S +++ b/sysdeps/x86_64/fpu/svml_s_atan2f16_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVeN16vv_atan2f) diff --git a/sysdeps/x86_64/fpu/svml_s_atan2f4_core.S b/sysdeps/x86_64/fpu/svml_s_atan2f4_core.S index 536b739f04..a3fb092911 100644 --- a/sysdeps/x86_64/fpu/svml_s_atan2f4_core.S +++ b/sysdeps/x86_64/fpu/svml_s_atan2f4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVbN4vv_atan2f) diff --git a/sysdeps/x86_64/fpu/svml_s_atan2f8_core.S b/sysdeps/x86_64/fpu/svml_s_atan2f8_core.S index 67376ca528..2f694b6486 100644 --- a/sysdeps/x86_64/fpu/svml_s_atan2f8_core.S +++ b/sysdeps/x86_64/fpu/svml_s_atan2f8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVdN8vv_atan2f) diff --git a/sysdeps/x86_64/fpu/svml_s_atan2f8_core_avx.S b/sysdeps/x86_64/fpu/svml_s_atan2f8_core_avx.S index 1c670d627f..06c856191b 100644 --- a/sysdeps/x86_64/fpu/svml_s_atan2f8_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_s_atan2f8_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY(_ZGVcN8vv_atan2f) diff --git a/sysdeps/x86_64/fpu/svml_s_atanf16_core.S b/sysdeps/x86_64/fpu/svml_s_atanf16_core.S index b1471451a0..59a0267aa0 100644 --- a/sysdeps/x86_64/fpu/svml_s_atanf16_core.S +++ b/sysdeps/x86_64/fpu/svml_s_atanf16_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVeN16v_atanf) diff --git a/sysdeps/x86_64/fpu/svml_s_atanf4_core.S b/sysdeps/x86_64/fpu/svml_s_atanf4_core.S index ea118a7984..2567206463 100644 --- a/sysdeps/x86_64/fpu/svml_s_atanf4_core.S +++ b/sysdeps/x86_64/fpu/svml_s_atanf4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVbN4v_atanf) diff --git a/sysdeps/x86_64/fpu/svml_s_atanf8_core.S b/sysdeps/x86_64/fpu/svml_s_atanf8_core.S index 8fad748544..b7961c7dbc 100644 --- a/sysdeps/x86_64/fpu/svml_s_atanf8_core.S +++ b/sysdeps/x86_64/fpu/svml_s_atanf8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVdN8v_atanf) diff --git a/sysdeps/x86_64/fpu/svml_s_atanf8_core_avx.S b/sysdeps/x86_64/fpu/svml_s_atanf8_core_avx.S index 1216b8a057..bedb807e1f 100644 --- a/sysdeps/x86_64/fpu/svml_s_atanf8_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_s_atanf8_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVcN8v_atanf) diff --git a/sysdeps/x86_64/fpu/svml_s_atanhf16_core.S b/sysdeps/x86_64/fpu/svml_s_atanhf16_core.S index 96dce010ec..240d943d6c 100644 --- a/sysdeps/x86_64/fpu/svml_s_atanhf16_core.S +++ b/sysdeps/x86_64/fpu/svml_s_atanhf16_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVeN16v_atanhf) diff --git a/sysdeps/x86_64/fpu/svml_s_atanhf4_core.S b/sysdeps/x86_64/fpu/svml_s_atanhf4_core.S index 1c1ec2bd0f..af4f58944f 100644 --- a/sysdeps/x86_64/fpu/svml_s_atanhf4_core.S +++ b/sysdeps/x86_64/fpu/svml_s_atanhf4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVbN4v_atanhf) diff --git a/sysdeps/x86_64/fpu/svml_s_atanhf8_core.S b/sysdeps/x86_64/fpu/svml_s_atanhf8_core.S index d92825330e..d23d62a18b 100644 --- a/sysdeps/x86_64/fpu/svml_s_atanhf8_core.S +++ b/sysdeps/x86_64/fpu/svml_s_atanhf8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVdN8v_atanhf) diff --git a/sysdeps/x86_64/fpu/svml_s_atanhf8_core_avx.S b/sysdeps/x86_64/fpu/svml_s_atanhf8_core_avx.S index 54d0b77b08..e5ec0c8eac 100644 --- a/sysdeps/x86_64/fpu/svml_s_atanhf8_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_s_atanhf8_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVcN8v_atanhf) diff --git a/sysdeps/x86_64/fpu/svml_s_cbrtf16_core.S b/sysdeps/x86_64/fpu/svml_s_cbrtf16_core.S index efe9149807..726631e734 100644 --- a/sysdeps/x86_64/fpu/svml_s_cbrtf16_core.S +++ b/sysdeps/x86_64/fpu/svml_s_cbrtf16_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVeN16v_cbrtf) diff --git a/sysdeps/x86_64/fpu/svml_s_cbrtf4_core.S b/sysdeps/x86_64/fpu/svml_s_cbrtf4_core.S index 687c549d7f..44e4f9f678 100644 --- a/sysdeps/x86_64/fpu/svml_s_cbrtf4_core.S +++ b/sysdeps/x86_64/fpu/svml_s_cbrtf4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVbN4v_cbrtf) diff --git a/sysdeps/x86_64/fpu/svml_s_cbrtf8_core.S b/sysdeps/x86_64/fpu/svml_s_cbrtf8_core.S index 2bb6fe8e78..e202f42255 100644 --- a/sysdeps/x86_64/fpu/svml_s_cbrtf8_core.S +++ b/sysdeps/x86_64/fpu/svml_s_cbrtf8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVdN8v_cbrtf) diff --git a/sysdeps/x86_64/fpu/svml_s_cbrtf8_core_avx.S b/sysdeps/x86_64/fpu/svml_s_cbrtf8_core_avx.S index 592f2cd419..b5f0f8ebdb 100644 --- a/sysdeps/x86_64/fpu/svml_s_cbrtf8_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_s_cbrtf8_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVcN8v_cbrtf) diff --git a/sysdeps/x86_64/fpu/svml_s_cosf16_core.S b/sysdeps/x86_64/fpu/svml_s_cosf16_core.S index 8daeffc289..8775f8da9c 100644 --- a/sysdeps/x86_64/fpu/svml_s_cosf16_core.S +++ b/sysdeps/x86_64/fpu/svml_s_cosf16_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVeN16v_cosf) diff --git a/sysdeps/x86_64/fpu/svml_s_cosf4_core.S b/sysdeps/x86_64/fpu/svml_s_cosf4_core.S index c6c3a4a622..5d9806898b 100644 --- a/sysdeps/x86_64/fpu/svml_s_cosf4_core.S +++ b/sysdeps/x86_64/fpu/svml_s_cosf4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVbN4v_cosf) diff --git a/sysdeps/x86_64/fpu/svml_s_cosf8_core.S b/sysdeps/x86_64/fpu/svml_s_cosf8_core.S index a4033da6de..5730e4265d 100644 --- a/sysdeps/x86_64/fpu/svml_s_cosf8_core.S +++ b/sysdeps/x86_64/fpu/svml_s_cosf8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVdN8v_cosf) diff --git a/sysdeps/x86_64/fpu/svml_s_cosf8_core_avx.S b/sysdeps/x86_64/fpu/svml_s_cosf8_core_avx.S index 12c6fddfa8..ab49929b56 100644 --- a/sysdeps/x86_64/fpu/svml_s_cosf8_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_s_cosf8_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVcN8v_cosf) diff --git a/sysdeps/x86_64/fpu/svml_s_coshf16_core.S b/sysdeps/x86_64/fpu/svml_s_coshf16_core.S index 97667390aa..8668f5bc86 100644 --- a/sysdeps/x86_64/fpu/svml_s_coshf16_core.S +++ b/sysdeps/x86_64/fpu/svml_s_coshf16_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVeN16v_coshf) diff --git a/sysdeps/x86_64/fpu/svml_s_coshf4_core.S b/sysdeps/x86_64/fpu/svml_s_coshf4_core.S index 8803c5e70b..82b893cd76 100644 --- a/sysdeps/x86_64/fpu/svml_s_coshf4_core.S +++ b/sysdeps/x86_64/fpu/svml_s_coshf4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVbN4v_coshf) diff --git a/sysdeps/x86_64/fpu/svml_s_coshf8_core.S b/sysdeps/x86_64/fpu/svml_s_coshf8_core.S index 85b144938e..1527b69e28 100644 --- a/sysdeps/x86_64/fpu/svml_s_coshf8_core.S +++ b/sysdeps/x86_64/fpu/svml_s_coshf8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVdN8v_coshf) diff --git a/sysdeps/x86_64/fpu/svml_s_coshf8_core_avx.S b/sysdeps/x86_64/fpu/svml_s_coshf8_core_avx.S index 8e4e1c19bb..f4ccf65eb9 100644 --- a/sysdeps/x86_64/fpu/svml_s_coshf8_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_s_coshf8_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVcN8v_coshf) diff --git a/sysdeps/x86_64/fpu/svml_s_erfcf16_core.S b/sysdeps/x86_64/fpu/svml_s_erfcf16_core.S index 0a14a1a4da..ca5a3cae8a 100644 --- a/sysdeps/x86_64/fpu/svml_s_erfcf16_core.S +++ b/sysdeps/x86_64/fpu/svml_s_erfcf16_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVeN16v_erfcf) diff --git a/sysdeps/x86_64/fpu/svml_s_erfcf4_core.S b/sysdeps/x86_64/fpu/svml_s_erfcf4_core.S index 0a7e3b79ee..ee98c24e3e 100644 --- a/sysdeps/x86_64/fpu/svml_s_erfcf4_core.S +++ b/sysdeps/x86_64/fpu/svml_s_erfcf4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVbN4v_erfcf) diff --git a/sysdeps/x86_64/fpu/svml_s_erfcf8_core.S b/sysdeps/x86_64/fpu/svml_s_erfcf8_core.S index 8122963d73..ef1f77458b 100644 --- a/sysdeps/x86_64/fpu/svml_s_erfcf8_core.S +++ b/sysdeps/x86_64/fpu/svml_s_erfcf8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVdN8v_erfcf) diff --git a/sysdeps/x86_64/fpu/svml_s_erfcf8_core_avx.S b/sysdeps/x86_64/fpu/svml_s_erfcf8_core_avx.S index 4f347c4d3c..803c9533c2 100644 --- a/sysdeps/x86_64/fpu/svml_s_erfcf8_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_s_erfcf8_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVcN8v_erfcf) diff --git a/sysdeps/x86_64/fpu/svml_s_erff16_core.S b/sysdeps/x86_64/fpu/svml_s_erff16_core.S index d544a6742d..95be88c16d 100644 --- a/sysdeps/x86_64/fpu/svml_s_erff16_core.S +++ b/sysdeps/x86_64/fpu/svml_s_erff16_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVeN16v_erff) diff --git a/sysdeps/x86_64/fpu/svml_s_erff4_core.S b/sysdeps/x86_64/fpu/svml_s_erff4_core.S index 4a83c8b6cc..3f9aace76b 100644 --- a/sysdeps/x86_64/fpu/svml_s_erff4_core.S +++ b/sysdeps/x86_64/fpu/svml_s_erff4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVbN4v_erff) diff --git a/sysdeps/x86_64/fpu/svml_s_erff8_core.S b/sysdeps/x86_64/fpu/svml_s_erff8_core.S index d91b5ad0c2..eb018cde99 100644 --- a/sysdeps/x86_64/fpu/svml_s_erff8_core.S +++ b/sysdeps/x86_64/fpu/svml_s_erff8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVdN8v_erff) diff --git a/sysdeps/x86_64/fpu/svml_s_erff8_core_avx.S b/sysdeps/x86_64/fpu/svml_s_erff8_core_avx.S index b2a8e7a152..87ded07bf1 100644 --- a/sysdeps/x86_64/fpu/svml_s_erff8_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_s_erff8_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVcN8v_erff) diff --git a/sysdeps/x86_64/fpu/svml_s_exp10f16_core.S b/sysdeps/x86_64/fpu/svml_s_exp10f16_core.S index 6e59aa2d45..64bfc69929 100644 --- a/sysdeps/x86_64/fpu/svml_s_exp10f16_core.S +++ b/sysdeps/x86_64/fpu/svml_s_exp10f16_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVeN16v_exp10f) diff --git a/sysdeps/x86_64/fpu/svml_s_exp10f4_core.S b/sysdeps/x86_64/fpu/svml_s_exp10f4_core.S index 3ebc7ed06d..652231cacf 100644 --- a/sysdeps/x86_64/fpu/svml_s_exp10f4_core.S +++ b/sysdeps/x86_64/fpu/svml_s_exp10f4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVbN4v_exp10f) diff --git a/sysdeps/x86_64/fpu/svml_s_exp10f8_core.S b/sysdeps/x86_64/fpu/svml_s_exp10f8_core.S index 338caf3fc2..61a9b908ca 100644 --- a/sysdeps/x86_64/fpu/svml_s_exp10f8_core.S +++ b/sysdeps/x86_64/fpu/svml_s_exp10f8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVdN8v_exp10f) diff --git a/sysdeps/x86_64/fpu/svml_s_exp10f8_core_avx.S b/sysdeps/x86_64/fpu/svml_s_exp10f8_core_avx.S index e0b6202662..f436570d36 100644 --- a/sysdeps/x86_64/fpu/svml_s_exp10f8_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_s_exp10f8_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVcN8v_exp10f) diff --git a/sysdeps/x86_64/fpu/svml_s_exp2f16_core.S b/sysdeps/x86_64/fpu/svml_s_exp2f16_core.S index 2a73400a0b..0d3d6c0c9d 100644 --- a/sysdeps/x86_64/fpu/svml_s_exp2f16_core.S +++ b/sysdeps/x86_64/fpu/svml_s_exp2f16_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVeN16v_exp2f) diff --git a/sysdeps/x86_64/fpu/svml_s_exp2f4_core.S b/sysdeps/x86_64/fpu/svml_s_exp2f4_core.S index ef6d68974c..05975db34f 100644 --- a/sysdeps/x86_64/fpu/svml_s_exp2f4_core.S +++ b/sysdeps/x86_64/fpu/svml_s_exp2f4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVbN4v_exp2f) diff --git a/sysdeps/x86_64/fpu/svml_s_exp2f8_core.S b/sysdeps/x86_64/fpu/svml_s_exp2f8_core.S index f7efe3736c..0dbeb46254 100644 --- a/sysdeps/x86_64/fpu/svml_s_exp2f8_core.S +++ b/sysdeps/x86_64/fpu/svml_s_exp2f8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVdN8v_exp2f) diff --git a/sysdeps/x86_64/fpu/svml_s_exp2f8_core_avx.S b/sysdeps/x86_64/fpu/svml_s_exp2f8_core_avx.S index b394654549..77e67248a7 100644 --- a/sysdeps/x86_64/fpu/svml_s_exp2f8_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_s_exp2f8_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVcN8v_exp2f) diff --git a/sysdeps/x86_64/fpu/svml_s_expf16_core.S b/sysdeps/x86_64/fpu/svml_s_expf16_core.S index cb3fc1f333..b99898deb3 100644 --- a/sysdeps/x86_64/fpu/svml_s_expf16_core.S +++ b/sysdeps/x86_64/fpu/svml_s_expf16_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVeN16v_expf) diff --git a/sysdeps/x86_64/fpu/svml_s_expf4_core.S b/sysdeps/x86_64/fpu/svml_s_expf4_core.S index 587e90bf33..2aaefa163e 100644 --- a/sysdeps/x86_64/fpu/svml_s_expf4_core.S +++ b/sysdeps/x86_64/fpu/svml_s_expf4_core.S @@ -18,7 +18,7 @@ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVbN4v_expf) diff --git a/sysdeps/x86_64/fpu/svml_s_expf8_core.S b/sysdeps/x86_64/fpu/svml_s_expf8_core.S index 01ca10da37..6f14117d74 100644 --- a/sysdeps/x86_64/fpu/svml_s_expf8_core.S +++ b/sysdeps/x86_64/fpu/svml_s_expf8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVdN8v_expf) diff --git a/sysdeps/x86_64/fpu/svml_s_expf8_core_avx.S b/sysdeps/x86_64/fpu/svml_s_expf8_core_avx.S index a3ede96599..6e2cd7b8af 100644 --- a/sysdeps/x86_64/fpu/svml_s_expf8_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_s_expf8_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY(_ZGVcN8v_expf) diff --git a/sysdeps/x86_64/fpu/svml_s_expm1f16_core.S b/sysdeps/x86_64/fpu/svml_s_expm1f16_core.S index 082cf1e6e5..7f3d9826ae 100644 --- a/sysdeps/x86_64/fpu/svml_s_expm1f16_core.S +++ b/sysdeps/x86_64/fpu/svml_s_expm1f16_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVeN16v_expm1f) diff --git a/sysdeps/x86_64/fpu/svml_s_expm1f4_core.S b/sysdeps/x86_64/fpu/svml_s_expm1f4_core.S index c1b1860728..13f5ccdf3a 100644 --- a/sysdeps/x86_64/fpu/svml_s_expm1f4_core.S +++ b/sysdeps/x86_64/fpu/svml_s_expm1f4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVbN4v_expm1f) diff --git a/sysdeps/x86_64/fpu/svml_s_expm1f8_core.S b/sysdeps/x86_64/fpu/svml_s_expm1f8_core.S index a39538dfd7..3f69069585 100644 --- a/sysdeps/x86_64/fpu/svml_s_expm1f8_core.S +++ b/sysdeps/x86_64/fpu/svml_s_expm1f8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVdN8v_expm1f) diff --git a/sysdeps/x86_64/fpu/svml_s_expm1f8_core_avx.S b/sysdeps/x86_64/fpu/svml_s_expm1f8_core_avx.S index eaaca17ce7..dc6a7a4973 100644 --- a/sysdeps/x86_64/fpu/svml_s_expm1f8_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_s_expm1f8_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVcN8v_expm1f) diff --git a/sysdeps/x86_64/fpu/svml_s_hypotf16_core.S b/sysdeps/x86_64/fpu/svml_s_hypotf16_core.S index 34ca783049..672f05269c 100644 --- a/sysdeps/x86_64/fpu/svml_s_hypotf16_core.S +++ b/sysdeps/x86_64/fpu/svml_s_hypotf16_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVeN16vv_hypotf) diff --git a/sysdeps/x86_64/fpu/svml_s_hypotf4_core.S b/sysdeps/x86_64/fpu/svml_s_hypotf4_core.S index e1d8ad19a6..dd09fad865 100644 --- a/sysdeps/x86_64/fpu/svml_s_hypotf4_core.S +++ b/sysdeps/x86_64/fpu/svml_s_hypotf4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVbN4vv_hypotf) diff --git a/sysdeps/x86_64/fpu/svml_s_hypotf8_core.S b/sysdeps/x86_64/fpu/svml_s_hypotf8_core.S index f5aa9f1e10..6d87708238 100644 --- a/sysdeps/x86_64/fpu/svml_s_hypotf8_core.S +++ b/sysdeps/x86_64/fpu/svml_s_hypotf8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVdN8vv_hypotf) diff --git a/sysdeps/x86_64/fpu/svml_s_hypotf8_core_avx.S b/sysdeps/x86_64/fpu/svml_s_hypotf8_core_avx.S index 707e91d7d3..7edb0d3cf2 100644 --- a/sysdeps/x86_64/fpu/svml_s_hypotf8_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_s_hypotf8_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY(_ZGVcN8vv_hypotf) diff --git a/sysdeps/x86_64/fpu/svml_s_log10f16_core.S b/sysdeps/x86_64/fpu/svml_s_log10f16_core.S index 8544bfb78c..e9df420be5 100644 --- a/sysdeps/x86_64/fpu/svml_s_log10f16_core.S +++ b/sysdeps/x86_64/fpu/svml_s_log10f16_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVeN16v_log10f) diff --git a/sysdeps/x86_64/fpu/svml_s_log10f4_core.S b/sysdeps/x86_64/fpu/svml_s_log10f4_core.S index 82188bedf4..7ac8512459 100644 --- a/sysdeps/x86_64/fpu/svml_s_log10f4_core.S +++ b/sysdeps/x86_64/fpu/svml_s_log10f4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVbN4v_log10f) diff --git a/sysdeps/x86_64/fpu/svml_s_log10f8_core.S b/sysdeps/x86_64/fpu/svml_s_log10f8_core.S index 03eea3415c..9f6006d2d1 100644 --- a/sysdeps/x86_64/fpu/svml_s_log10f8_core.S +++ b/sysdeps/x86_64/fpu/svml_s_log10f8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVdN8v_log10f) diff --git a/sysdeps/x86_64/fpu/svml_s_log10f8_core_avx.S b/sysdeps/x86_64/fpu/svml_s_log10f8_core_avx.S index 9943a86eb5..b811d10876 100644 --- a/sysdeps/x86_64/fpu/svml_s_log10f8_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_s_log10f8_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVcN8v_log10f) diff --git a/sysdeps/x86_64/fpu/svml_s_log1pf16_core.S b/sysdeps/x86_64/fpu/svml_s_log1pf16_core.S index 9e70217b1e..20c838b4de 100644 --- a/sysdeps/x86_64/fpu/svml_s_log1pf16_core.S +++ b/sysdeps/x86_64/fpu/svml_s_log1pf16_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVeN16v_log1pf) diff --git a/sysdeps/x86_64/fpu/svml_s_log1pf4_core.S b/sysdeps/x86_64/fpu/svml_s_log1pf4_core.S index 4de7f84564..2e179b91e6 100644 --- a/sysdeps/x86_64/fpu/svml_s_log1pf4_core.S +++ b/sysdeps/x86_64/fpu/svml_s_log1pf4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVbN4v_log1pf) diff --git a/sysdeps/x86_64/fpu/svml_s_log1pf8_core.S b/sysdeps/x86_64/fpu/svml_s_log1pf8_core.S index edf35f29ca..9a24ad132f 100644 --- a/sysdeps/x86_64/fpu/svml_s_log1pf8_core.S +++ b/sysdeps/x86_64/fpu/svml_s_log1pf8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVdN8v_log1pf) diff --git a/sysdeps/x86_64/fpu/svml_s_log1pf8_core_avx.S b/sysdeps/x86_64/fpu/svml_s_log1pf8_core_avx.S index 1acd26070f..3055ce8d96 100644 --- a/sysdeps/x86_64/fpu/svml_s_log1pf8_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_s_log1pf8_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVcN8v_log1pf) diff --git a/sysdeps/x86_64/fpu/svml_s_log2f16_core.S b/sysdeps/x86_64/fpu/svml_s_log2f16_core.S index 1a21fe6996..9305f1fc2d 100644 --- a/sysdeps/x86_64/fpu/svml_s_log2f16_core.S +++ b/sysdeps/x86_64/fpu/svml_s_log2f16_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVeN16v_log2f) diff --git a/sysdeps/x86_64/fpu/svml_s_log2f4_core.S b/sysdeps/x86_64/fpu/svml_s_log2f4_core.S index fd28c9e43b..4bcc88b349 100644 --- a/sysdeps/x86_64/fpu/svml_s_log2f4_core.S +++ b/sysdeps/x86_64/fpu/svml_s_log2f4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVbN4v_log2f) diff --git a/sysdeps/x86_64/fpu/svml_s_log2f8_core.S b/sysdeps/x86_64/fpu/svml_s_log2f8_core.S index 8f6254f7d2..db51a650be 100644 --- a/sysdeps/x86_64/fpu/svml_s_log2f8_core.S +++ b/sysdeps/x86_64/fpu/svml_s_log2f8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVdN8v_log2f) diff --git a/sysdeps/x86_64/fpu/svml_s_log2f8_core_avx.S b/sysdeps/x86_64/fpu/svml_s_log2f8_core_avx.S index 6a1832faa4..743fcd3d91 100644 --- a/sysdeps/x86_64/fpu/svml_s_log2f8_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_s_log2f8_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVcN8v_log2f) diff --git a/sysdeps/x86_64/fpu/svml_s_logf16_core.S b/sysdeps/x86_64/fpu/svml_s_logf16_core.S index d9df2536d2..2de06af230 100644 --- a/sysdeps/x86_64/fpu/svml_s_logf16_core.S +++ b/sysdeps/x86_64/fpu/svml_s_logf16_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVeN16v_logf) diff --git a/sysdeps/x86_64/fpu/svml_s_logf4_core.S b/sysdeps/x86_64/fpu/svml_s_logf4_core.S index 8300d4464e..6edb8f6cec 100644 --- a/sysdeps/x86_64/fpu/svml_s_logf4_core.S +++ b/sysdeps/x86_64/fpu/svml_s_logf4_core.S @@ -18,7 +18,7 @@ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVbN4v_logf) diff --git a/sysdeps/x86_64/fpu/svml_s_logf8_core.S b/sysdeps/x86_64/fpu/svml_s_logf8_core.S index 2d779866f4..df57322134 100644 --- a/sysdeps/x86_64/fpu/svml_s_logf8_core.S +++ b/sysdeps/x86_64/fpu/svml_s_logf8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVdN8v_logf) diff --git a/sysdeps/x86_64/fpu/svml_s_logf8_core_avx.S b/sysdeps/x86_64/fpu/svml_s_logf8_core_avx.S index 8e77a9ea2d..a78dca2ce5 100644 --- a/sysdeps/x86_64/fpu/svml_s_logf8_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_s_logf8_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY(_ZGVcN8v_logf) diff --git a/sysdeps/x86_64/fpu/svml_s_powf16_core.S b/sysdeps/x86_64/fpu/svml_s_powf16_core.S index 117d907007..69fef6a25d 100644 --- a/sysdeps/x86_64/fpu/svml_s_powf16_core.S +++ b/sysdeps/x86_64/fpu/svml_s_powf16_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVeN16vv_powf) diff --git a/sysdeps/x86_64/fpu/svml_s_powf4_core.S b/sysdeps/x86_64/fpu/svml_s_powf4_core.S index d328436a0a..f28a9ed9d5 100644 --- a/sysdeps/x86_64/fpu/svml_s_powf4_core.S +++ b/sysdeps/x86_64/fpu/svml_s_powf4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVbN4vv_powf) diff --git a/sysdeps/x86_64/fpu/svml_s_powf8_core.S b/sysdeps/x86_64/fpu/svml_s_powf8_core.S index 881c841eb5..ace548b93e 100644 --- a/sysdeps/x86_64/fpu/svml_s_powf8_core.S +++ b/sysdeps/x86_64/fpu/svml_s_powf8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVdN8vv_powf) diff --git a/sysdeps/x86_64/fpu/svml_s_powf8_core_avx.S b/sysdeps/x86_64/fpu/svml_s_powf8_core_avx.S index 7d71c56106..d269163620 100644 --- a/sysdeps/x86_64/fpu/svml_s_powf8_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_s_powf8_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY(_ZGVcN8vv_powf) diff --git a/sysdeps/x86_64/fpu/svml_s_sincosf16_core.S b/sysdeps/x86_64/fpu/svml_s_sincosf16_core.S index c46f34cc33..6b13904f32 100644 --- a/sysdeps/x86_64/fpu/svml_s_sincosf16_core.S +++ b/sysdeps/x86_64/fpu/svml_s_sincosf16_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVeN16vl4l4_sincosf) diff --git a/sysdeps/x86_64/fpu/svml_s_sincosf4_core.S b/sysdeps/x86_64/fpu/svml_s_sincosf4_core.S index a2c38364fb..5e8e68cb46 100644 --- a/sysdeps/x86_64/fpu/svml_s_sincosf4_core.S +++ b/sysdeps/x86_64/fpu/svml_s_sincosf4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVbN4vl4l4_sincosf) diff --git a/sysdeps/x86_64/fpu/svml_s_sincosf8_core.S b/sysdeps/x86_64/fpu/svml_s_sincosf8_core.S index c6e9d544a2..62d4ed96a0 100644 --- a/sysdeps/x86_64/fpu/svml_s_sincosf8_core.S +++ b/sysdeps/x86_64/fpu/svml_s_sincosf8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVdN8vl4l4_sincosf) diff --git a/sysdeps/x86_64/fpu/svml_s_sincosf8_core_avx.S b/sysdeps/x86_64/fpu/svml_s_sincosf8_core_avx.S index fe5fbd929d..39d3b6135c 100644 --- a/sysdeps/x86_64/fpu/svml_s_sincosf8_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_s_sincosf8_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVcN8vl4l4_sincosf) diff --git a/sysdeps/x86_64/fpu/svml_s_sinf16_core.S b/sysdeps/x86_64/fpu/svml_s_sinf16_core.S index d456e801b6..32a89294f6 100644 --- a/sysdeps/x86_64/fpu/svml_s_sinf16_core.S +++ b/sysdeps/x86_64/fpu/svml_s_sinf16_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVeN16v_sinf) diff --git a/sysdeps/x86_64/fpu/svml_s_sinf4_core.S b/sysdeps/x86_64/fpu/svml_s_sinf4_core.S index 5b89563158..ad7e12f8da 100644 --- a/sysdeps/x86_64/fpu/svml_s_sinf4_core.S +++ b/sysdeps/x86_64/fpu/svml_s_sinf4_core.S @@ -18,7 +18,7 @@ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVbN4v_sinf) diff --git a/sysdeps/x86_64/fpu/svml_s_sinf8_core.S b/sysdeps/x86_64/fpu/svml_s_sinf8_core.S index f1bf44fa6f..bb80a43360 100644 --- a/sysdeps/x86_64/fpu/svml_s_sinf8_core.S +++ b/sysdeps/x86_64/fpu/svml_s_sinf8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVdN8v_sinf) diff --git a/sysdeps/x86_64/fpu/svml_s_sinf8_core_avx.S b/sysdeps/x86_64/fpu/svml_s_sinf8_core_avx.S index 14de999a89..a296e1a233 100644 --- a/sysdeps/x86_64/fpu/svml_s_sinf8_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_s_sinf8_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY(_ZGVcN8v_sinf) diff --git a/sysdeps/x86_64/fpu/svml_s_sinhf16_core.S b/sysdeps/x86_64/fpu/svml_s_sinhf16_core.S index da1269c156..666270e804 100644 --- a/sysdeps/x86_64/fpu/svml_s_sinhf16_core.S +++ b/sysdeps/x86_64/fpu/svml_s_sinhf16_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVeN16v_sinhf) diff --git a/sysdeps/x86_64/fpu/svml_s_sinhf4_core.S b/sysdeps/x86_64/fpu/svml_s_sinhf4_core.S index c233bf1ac6..50b36b81a6 100644 --- a/sysdeps/x86_64/fpu/svml_s_sinhf4_core.S +++ b/sysdeps/x86_64/fpu/svml_s_sinhf4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVbN4v_sinhf) diff --git a/sysdeps/x86_64/fpu/svml_s_sinhf8_core.S b/sysdeps/x86_64/fpu/svml_s_sinhf8_core.S index 9e301d8896..1d2913eb88 100644 --- a/sysdeps/x86_64/fpu/svml_s_sinhf8_core.S +++ b/sysdeps/x86_64/fpu/svml_s_sinhf8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVdN8v_sinhf) diff --git a/sysdeps/x86_64/fpu/svml_s_sinhf8_core_avx.S b/sysdeps/x86_64/fpu/svml_s_sinhf8_core_avx.S index f21eb1e26c..555ca75a04 100644 --- a/sysdeps/x86_64/fpu/svml_s_sinhf8_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_s_sinhf8_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVcN8v_sinhf) diff --git a/sysdeps/x86_64/fpu/svml_s_tanf16_core.S b/sysdeps/x86_64/fpu/svml_s_tanf16_core.S index f8ce7880fb..1e66c2c186 100644 --- a/sysdeps/x86_64/fpu/svml_s_tanf16_core.S +++ b/sysdeps/x86_64/fpu/svml_s_tanf16_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVeN16v_tanf) diff --git a/sysdeps/x86_64/fpu/svml_s_tanf4_core.S b/sysdeps/x86_64/fpu/svml_s_tanf4_core.S index 3b6c0603c8..868a6ab327 100644 --- a/sysdeps/x86_64/fpu/svml_s_tanf4_core.S +++ b/sysdeps/x86_64/fpu/svml_s_tanf4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVbN4v_tanf) diff --git a/sysdeps/x86_64/fpu/svml_s_tanf8_core.S b/sysdeps/x86_64/fpu/svml_s_tanf8_core.S index 084f2b4c95..92a2e583c0 100644 --- a/sysdeps/x86_64/fpu/svml_s_tanf8_core.S +++ b/sysdeps/x86_64/fpu/svml_s_tanf8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVdN8v_tanf) diff --git a/sysdeps/x86_64/fpu/svml_s_tanf8_core_avx.S b/sysdeps/x86_64/fpu/svml_s_tanf8_core_avx.S index 8d42d3bec4..0b506755d8 100644 --- a/sysdeps/x86_64/fpu/svml_s_tanf8_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_s_tanf8_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVcN8v_tanf) diff --git a/sysdeps/x86_64/fpu/svml_s_tanhf16_core.S b/sysdeps/x86_64/fpu/svml_s_tanhf16_core.S index c25c5925a4..b7166b480a 100644 --- a/sysdeps/x86_64/fpu/svml_s_tanhf16_core.S +++ b/sysdeps/x86_64/fpu/svml_s_tanhf16_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVeN16v_tanhf) diff --git a/sysdeps/x86_64/fpu/svml_s_tanhf4_core.S b/sysdeps/x86_64/fpu/svml_s_tanhf4_core.S index a6cf56cbe4..5fe52830b1 100644 --- a/sysdeps/x86_64/fpu/svml_s_tanhf4_core.S +++ b/sysdeps/x86_64/fpu/svml_s_tanhf4_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVbN4v_tanhf) diff --git a/sysdeps/x86_64/fpu/svml_s_tanhf8_core.S b/sysdeps/x86_64/fpu/svml_s_tanhf8_core.S index 610c4e0759..9ea6b9bc8c 100644 --- a/sysdeps/x86_64/fpu/svml_s_tanhf8_core.S +++ b/sysdeps/x86_64/fpu/svml_s_tanhf8_core.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVdN8v_tanhf) diff --git a/sysdeps/x86_64/fpu/svml_s_tanhf8_core_avx.S b/sysdeps/x86_64/fpu/svml_s_tanhf8_core_avx.S index 5e9eca577f..9230746e01 100644 --- a/sysdeps/x86_64/fpu/svml_s_tanhf8_core_avx.S +++ b/sysdeps/x86_64/fpu/svml_s_tanhf8_core_avx.S @@ -17,7 +17,7 @@ . */ #include -#include "svml_s_wrapper_impl.h" +#include "svml_s_wrapper_impl.h.S" .text ENTRY (_ZGVcN8v_tanhf) diff --git a/sysdeps/x86_64/fpu/svml_s_wrapper_impl.h b/sysdeps/x86_64/fpu/svml_s_wrapper_impl.h.S similarity index 100% rename from sysdeps/x86_64/fpu/svml_s_wrapper_impl.h rename to sysdeps/x86_64/fpu/svml_s_wrapper_impl.h.S From patchwork Fri Nov 18 06:37:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Noah Goldstein X-Patchwork-Id: 60813 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 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k34-20020a635a62000000b00476ed2a6215mr5450138pgm.559.1668753449785; Thu, 17 Nov 2022 22:37:29 -0800 (PST) Received: from noahgold-desk.. ([192.55.60.47]) by smtp.gmail.com with ESMTPSA id j7-20020a170902da8700b00176a6ba5969sm2670692plx.98.2022.11.17.22.37.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Nov 2022 22:37:28 -0800 (PST) To: libc-alpha@sourceware.org Cc: goldstein.w.n@gmail.com, hjl.tools@gmail.com, carlos@systemhalted.org Subject: [PATCH v1 2/3] x86/fpu: Reformat svml_{s|d}_wrapper_impl.h.S Date: Thu, 17 Nov 2022 22:37:22 -0800 Message-Id: <20221118063723.858936-2-goldstein.w.n@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221118063723.858936-1-goldstein.w.n@gmail.com> References: <20221118063723.858936-1-goldstein.w.n@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Noah Goldstein via Libc-alpha From: Noah Goldstein Reply-To: Noah Goldstein Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org Sender: "Libc-alpha" Just reformat with the style convention used in other x86 assembler files. This doesn't change libm.so or libmvec.so. --- sysdeps/x86_64/fpu/svml_d_wrapper_impl.h.S | 474 +++++++++--------- sysdeps/x86_64/fpu/svml_s_wrapper_impl.h.S | 546 ++++++++++----------- 2 files changed, 510 insertions(+), 510 deletions(-) diff --git a/sysdeps/x86_64/fpu/svml_d_wrapper_impl.h.S b/sysdeps/x86_64/fpu/svml_d_wrapper_impl.h.S index 2334713015..b03a2122b9 100644 --- a/sysdeps/x86_64/fpu/svml_d_wrapper_impl.h.S +++ b/sysdeps/x86_64/fpu/svml_d_wrapper_impl.h.S @@ -18,273 +18,273 @@ /* SSE2 ISA version as wrapper to scalar. */ .macro WRAPPER_IMPL_SSE2 callee - subq $40, %rsp - cfi_adjust_cfa_offset(40) - movaps %xmm0, (%rsp) - call JUMPTARGET(\callee) - movsd %xmm0, 16(%rsp) - movsd 8(%rsp), %xmm0 - call JUMPTARGET(\callee) - movsd 16(%rsp), %xmm1 - movsd %xmm0, 24(%rsp) - unpcklpd %xmm0, %xmm1 - movaps %xmm1, %xmm0 - addq $40, %rsp - cfi_adjust_cfa_offset(-40) - ret + subq $40, %rsp + cfi_adjust_cfa_offset (40) + movaps %xmm0, (%rsp) + call JUMPTARGET(\callee) + movsd %xmm0, 16(%rsp) + movsd 8(%rsp), %xmm0 + call JUMPTARGET(\callee) + movsd 16(%rsp), %xmm1 + movsd %xmm0, 24(%rsp) + unpcklpd %xmm0, %xmm1 + movaps %xmm1, %xmm0 + addq $40, %rsp + cfi_adjust_cfa_offset (-40) + ret .endm /* 2 argument SSE2 ISA version as wrapper to scalar. */ .macro WRAPPER_IMPL_SSE2_ff callee - subq $56, %rsp - cfi_adjust_cfa_offset(56) - movaps %xmm0, (%rsp) - movaps %xmm1, 16(%rsp) - call JUMPTARGET(\callee) - movsd %xmm0, 32(%rsp) - movsd 8(%rsp), %xmm0 - movsd 24(%rsp), %xmm1 - call JUMPTARGET(\callee) - movsd 32(%rsp), %xmm1 - movsd %xmm0, 40(%rsp) - unpcklpd %xmm0, %xmm1 - movaps %xmm1, %xmm0 - addq $56, %rsp - cfi_adjust_cfa_offset(-56) - ret + subq $56, %rsp + cfi_adjust_cfa_offset (56) + movaps %xmm0, (%rsp) + movaps %xmm1, 16(%rsp) + call JUMPTARGET(\callee) + movsd %xmm0, 32(%rsp) + movsd 8(%rsp), %xmm0 + movsd 24(%rsp), %xmm1 + call JUMPTARGET(\callee) + movsd 32(%rsp), %xmm1 + movsd %xmm0, 40(%rsp) + unpcklpd %xmm0, %xmm1 + movaps %xmm1, %xmm0 + addq $56, %rsp + cfi_adjust_cfa_offset (-56) + ret .endm /* 3 argument SSE2 ISA version as wrapper to scalar. */ .macro WRAPPER_IMPL_SSE2_fFF callee - pushq %rbp - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%rbp, 0) - pushq %rbx - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%rbx, 0) - movq %rdi, %rbp - movq %rsi, %rbx - subq $40, %rsp - cfi_adjust_cfa_offset(40) - leaq 16(%rsp), %rsi - leaq 24(%rsp), %rdi - movaps %xmm0, (%rsp) - call JUMPTARGET(\callee) - leaq 16(%rsp), %rsi - leaq 24(%rsp), %rdi - movsd 24(%rsp), %xmm0 - movapd (%rsp), %xmm1 - movsd %xmm0, 0(%rbp) - unpckhpd %xmm1, %xmm1 - movsd 16(%rsp), %xmm0 - movsd %xmm0, (%rbx) - movapd %xmm1, %xmm0 - call JUMPTARGET(\callee) - movsd 24(%rsp), %xmm0 - movsd %xmm0, 8(%rbp) - movsd 16(%rsp), %xmm0 - movsd %xmm0, 8(%rbx) - addq $40, %rsp - cfi_adjust_cfa_offset(-40) - popq %rbx - cfi_adjust_cfa_offset (-8) - cfi_restore (%rbx) - popq %rbp - cfi_adjust_cfa_offset (-8) - cfi_restore (%rbp) - ret + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + pushq %rbx + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbx, 0) + movq %rdi, %rbp + movq %rsi, %rbx + subq $40, %rsp + cfi_adjust_cfa_offset (40) + leaq 16(%rsp), %rsi + leaq 24(%rsp), %rdi + movaps %xmm0, (%rsp) + call JUMPTARGET(\callee) + leaq 16(%rsp), %rsi + leaq 24(%rsp), %rdi + movsd 24(%rsp), %xmm0 + movapd (%rsp), %xmm1 + movsd %xmm0, 0(%rbp) + unpckhpd %xmm1, %xmm1 + movsd 16(%rsp), %xmm0 + movsd %xmm0, (%rbx) + movapd %xmm1, %xmm0 + call JUMPTARGET(\callee) + movsd 24(%rsp), %xmm0 + movsd %xmm0, 8(%rbp) + movsd 16(%rsp), %xmm0 + movsd %xmm0, 8(%rbx) + addq $40, %rsp + cfi_adjust_cfa_offset (-40) + popq %rbx + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbx) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret .endm /* AVX/AVX2 ISA version as wrapper to SSE ISA version. */ .macro WRAPPER_IMPL_AVX callee - pushq %rbp - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%rbp, 0) - movq %rsp, %rbp - cfi_def_cfa_register (%rbp) - andq $-32, %rsp - subq $32, %rsp - vextractf128 $1, %ymm0, (%rsp) - vzeroupper - call HIDDEN_JUMPTARGET(\callee) - vmovapd %xmm0, 16(%rsp) - vmovaps (%rsp), %xmm0 - call HIDDEN_JUMPTARGET(\callee) - vmovapd %xmm0, %xmm1 - vmovapd 16(%rsp), %xmm0 - vinsertf128 $1, %xmm1, %ymm0, %ymm0 - movq %rbp, %rsp - cfi_def_cfa_register (%rsp) - popq %rbp - cfi_adjust_cfa_offset (-8) - cfi_restore (%rbp) - ret + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-32, %rsp + subq $32, %rsp + vextractf128 $1, %ymm0, (%rsp) + vzeroupper + call HIDDEN_JUMPTARGET(\callee) + vmovapd %xmm0, 16(%rsp) + vmovaps (%rsp), %xmm0 + call HIDDEN_JUMPTARGET(\callee) + vmovapd %xmm0, %xmm1 + vmovapd 16(%rsp), %xmm0 + vinsertf128 $1, %xmm1, %ymm0, %ymm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret .endm /* 2 argument AVX/AVX2 ISA version as wrapper to SSE ISA version. */ .macro WRAPPER_IMPL_AVX_ff callee - pushq %rbp - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%rbp, 0) - movq %rsp, %rbp - cfi_def_cfa_register (%rbp) - andq $-32, %rsp - subq $64, %rsp - vextractf128 $1, %ymm0, 16(%rsp) - vextractf128 $1, %ymm1, (%rsp) - vzeroupper - call HIDDEN_JUMPTARGET(\callee) - vmovaps %xmm0, 32(%rsp) - vmovaps 16(%rsp), %xmm0 - vmovaps (%rsp), %xmm1 - call HIDDEN_JUMPTARGET(\callee) - vmovaps %xmm0, %xmm1 - vmovaps 32(%rsp), %xmm0 - vinsertf128 $1, %xmm1, %ymm0, %ymm0 - movq %rbp, %rsp - cfi_def_cfa_register (%rsp) - popq %rbp - cfi_adjust_cfa_offset (-8) - cfi_restore (%rbp) - ret + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-32, %rsp + subq $64, %rsp + vextractf128 $1, %ymm0, 16(%rsp) + vextractf128 $1, %ymm1, (%rsp) + vzeroupper + call HIDDEN_JUMPTARGET(\callee) + vmovaps %xmm0, 32(%rsp) + vmovaps 16(%rsp), %xmm0 + vmovaps (%rsp), %xmm1 + call HIDDEN_JUMPTARGET(\callee) + vmovaps %xmm0, %xmm1 + vmovaps 32(%rsp), %xmm0 + vinsertf128 $1, %xmm1, %ymm0, %ymm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret .endm /* 3 argument AVX/AVX2 ISA version as wrapper to SSE ISA version. */ .macro WRAPPER_IMPL_AVX_fFF callee - pushq %rbp - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%rbp, 0) - movq %rsp, %rbp - cfi_def_cfa_register (%rbp) - andq $-32, %rsp - pushq %r13 - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%r13, 0) - pushq %r14 - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%r14, 0) - subq $48, %rsp - movq %rsi, %r14 - movq %rdi, %r13 - vextractf128 $1, %ymm0, 32(%rsp) - vzeroupper - call HIDDEN_JUMPTARGET(\callee) - vmovaps 32(%rsp), %xmm0 - lea (%rsp), %rdi - lea 16(%rsp), %rsi - call HIDDEN_JUMPTARGET(\callee) - vmovapd (%rsp), %xmm0 - vmovapd 16(%rsp), %xmm1 - vmovapd %xmm0, 16(%r13) - vmovapd %xmm1, 16(%r14) - addq $48, %rsp - popq %r14 - cfi_adjust_cfa_offset (-8) - cfi_restore (%r14) - popq %r13 - cfi_adjust_cfa_offset (-8) - cfi_restore (%r13) - movq %rbp, %rsp - cfi_def_cfa_register (%rsp) - popq %rbp - cfi_adjust_cfa_offset (-8) - cfi_restore (%rbp) - ret + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-32, %rsp + pushq %r13 + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%r13, 0) + pushq %r14 + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%r14, 0) + subq $48, %rsp + movq %rsi, %r14 + movq %rdi, %r13 + vextractf128 $1, %ymm0, 32(%rsp) + vzeroupper + call HIDDEN_JUMPTARGET(\callee) + vmovaps 32(%rsp), %xmm0 + lea (%rsp), %rdi + lea 16(%rsp), %rsi + call HIDDEN_JUMPTARGET(\callee) + vmovapd (%rsp), %xmm0 + vmovapd 16(%rsp), %xmm1 + vmovapd %xmm0, 16(%r13) + vmovapd %xmm1, 16(%r14) + addq $48, %rsp + popq %r14 + cfi_adjust_cfa_offset (-8) + cfi_restore (%r14) + popq %r13 + cfi_adjust_cfa_offset (-8) + cfi_restore (%r13) + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret .endm /* AVX512 ISA version as wrapper to AVX2 ISA version. */ .macro WRAPPER_IMPL_AVX512 callee - pushq %rbp - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%rbp, 0) - movq %rsp, %rbp - cfi_def_cfa_register (%rbp) - andq $-64, %rsp - subq $128, %rsp - vmovups %zmm0, (%rsp) - vmovupd (%rsp), %ymm0 - call HIDDEN_JUMPTARGET(\callee) - vmovupd %ymm0, 64(%rsp) - vmovupd 32(%rsp), %ymm0 - call HIDDEN_JUMPTARGET(\callee) - vmovupd %ymm0, 96(%rsp) - vmovups 64(%rsp), %zmm0 - movq %rbp, %rsp - cfi_def_cfa_register (%rsp) - popq %rbp - cfi_adjust_cfa_offset (-8) - cfi_restore (%rbp) - ret + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $128, %rsp + vmovups %zmm0, (%rsp) + vmovupd (%rsp), %ymm0 + call HIDDEN_JUMPTARGET(\callee) + vmovupd %ymm0, 64(%rsp) + vmovupd 32(%rsp), %ymm0 + call HIDDEN_JUMPTARGET(\callee) + vmovupd %ymm0, 96(%rsp) + vmovups 64(%rsp), %zmm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret .endm /* 2 argument AVX512 ISA version as wrapper to AVX2 ISA version. */ .macro WRAPPER_IMPL_AVX512_ff callee - pushq %rbp - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%rbp, 0) - movq %rsp, %rbp - cfi_def_cfa_register (%rbp) - andq $-64, %rsp - subq $192, %rsp - vmovups %zmm0, (%rsp) - vmovups %zmm1, 64(%rsp) - vmovupd (%rsp), %ymm0 - vmovupd 64(%rsp), %ymm1 - call HIDDEN_JUMPTARGET(\callee) - vmovupd %ymm0, 128(%rsp) - vmovupd 32(%rsp), %ymm0 - vmovupd 96(%rsp), %ymm1 - call HIDDEN_JUMPTARGET(\callee) - vmovupd %ymm0, 160(%rsp) - vmovups 128(%rsp), %zmm0 - movq %rbp, %rsp - cfi_def_cfa_register (%rsp) - popq %rbp - cfi_adjust_cfa_offset (-8) - cfi_restore (%rbp) - ret + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $192, %rsp + vmovups %zmm0, (%rsp) + vmovups %zmm1, 64(%rsp) + vmovupd (%rsp), %ymm0 + vmovupd 64(%rsp), %ymm1 + call HIDDEN_JUMPTARGET(\callee) + vmovupd %ymm0, 128(%rsp) + vmovupd 32(%rsp), %ymm0 + vmovupd 96(%rsp), %ymm1 + call HIDDEN_JUMPTARGET(\callee) + vmovupd %ymm0, 160(%rsp) + vmovups 128(%rsp), %zmm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret .endm /* 3 argument AVX512 ISA version as wrapper to AVX2 ISA version. */ .macro WRAPPER_IMPL_AVX512_fFF callee - pushq %rbp - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%rbp, 0) - movq %rsp, %rbp - cfi_def_cfa_register (%rbp) - andq $-64, %rsp - pushq %r12 - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%r12, 0) - pushq %r13 - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%r13, 0) - subq $176, %rsp - movq %rsi, %r13 - vmovups %zmm0, (%rsp) - movq %rdi, %r12 - vmovupd (%rsp), %ymm0 - call HIDDEN_JUMPTARGET(\callee) - vmovupd 32(%rsp), %ymm0 - lea 64(%rsp), %rdi - lea 96(%rsp), %rsi - call HIDDEN_JUMPTARGET(\callee) - vmovupd 64(%rsp), %ymm0 - vmovupd 96(%rsp), %ymm1 - vmovupd %ymm0, 32(%r12) - vmovupd %ymm1, 32(%r13) - vzeroupper - addq $176, %rsp - popq %r13 - cfi_adjust_cfa_offset (-8) - cfi_restore (%r13) - popq %r12 - cfi_adjust_cfa_offset (-8) - cfi_restore (%r12) - movq %rbp, %rsp - cfi_def_cfa_register (%rsp) - popq %rbp - cfi_adjust_cfa_offset (-8) - cfi_restore (%rbp) - ret + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + pushq %r12 + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%r12, 0) + pushq %r13 + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%r13, 0) + subq $176, %rsp + movq %rsi, %r13 + vmovups %zmm0, (%rsp) + movq %rdi, %r12 + vmovupd (%rsp), %ymm0 + call HIDDEN_JUMPTARGET(\callee) + vmovupd 32(%rsp), %ymm0 + lea 64(%rsp), %rdi + lea 96(%rsp), %rsi + call HIDDEN_JUMPTARGET(\callee) + vmovupd 64(%rsp), %ymm0 + vmovupd 96(%rsp), %ymm1 + vmovupd %ymm0, 32(%r12) + vmovupd %ymm1, 32(%r13) + vzeroupper + addq $176, %rsp + popq %r13 + cfi_adjust_cfa_offset (-8) + cfi_restore (%r13) + popq %r12 + cfi_adjust_cfa_offset (-8) + cfi_restore (%r12) + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret .endm diff --git a/sysdeps/x86_64/fpu/svml_s_wrapper_impl.h.S b/sysdeps/x86_64/fpu/svml_s_wrapper_impl.h.S index c23da7ec83..cecf6c8384 100644 --- a/sysdeps/x86_64/fpu/svml_s_wrapper_impl.h.S +++ b/sysdeps/x86_64/fpu/svml_s_wrapper_impl.h.S @@ -18,309 +18,309 @@ /* SSE2 ISA version as wrapper to scalar. */ .macro WRAPPER_IMPL_SSE2 callee - subq $40, %rsp - cfi_adjust_cfa_offset(40) - movaps %xmm0, (%rsp) - call JUMPTARGET(\callee) - movss %xmm0, 16(%rsp) - movss 4(%rsp), %xmm0 - call JUMPTARGET(\callee) - movss %xmm0, 20(%rsp) - movss 8(%rsp), %xmm0 - call JUMPTARGET(\callee) - movss %xmm0, 24(%rsp) - movss 12(%rsp), %xmm0 - call JUMPTARGET(\callee) - movss 16(%rsp), %xmm3 - movss 20(%rsp), %xmm2 - movss 24(%rsp), %xmm1 - movss %xmm0, 28(%rsp) - unpcklps %xmm1, %xmm3 - unpcklps %xmm0, %xmm2 - unpcklps %xmm2, %xmm3 - movaps %xmm3, %xmm0 - addq $40, %rsp - cfi_adjust_cfa_offset(-40) - ret + subq $40, %rsp + cfi_adjust_cfa_offset (40) + movaps %xmm0, (%rsp) + call JUMPTARGET(\callee) + movss %xmm0, 16(%rsp) + movss 4(%rsp), %xmm0 + call JUMPTARGET(\callee) + movss %xmm0, 20(%rsp) + movss 8(%rsp), %xmm0 + call JUMPTARGET(\callee) + movss %xmm0, 24(%rsp) + movss 12(%rsp), %xmm0 + call JUMPTARGET(\callee) + movss 16(%rsp), %xmm3 + movss 20(%rsp), %xmm2 + movss 24(%rsp), %xmm1 + movss %xmm0, 28(%rsp) + unpcklps %xmm1, %xmm3 + unpcklps %xmm0, %xmm2 + unpcklps %xmm2, %xmm3 + movaps %xmm3, %xmm0 + addq $40, %rsp + cfi_adjust_cfa_offset (-40) + ret .endm /* 2 argument SSE2 ISA version as wrapper to scalar. */ .macro WRAPPER_IMPL_SSE2_ff callee - subq $56, %rsp - cfi_adjust_cfa_offset(56) - movaps %xmm0, (%rsp) - movaps %xmm1, 16(%rsp) - call JUMPTARGET(\callee) - movss %xmm0, 32(%rsp) - movss 4(%rsp), %xmm0 - movss 20(%rsp), %xmm1 - call JUMPTARGET(\callee) - movss %xmm0, 36(%rsp) - movss 8(%rsp), %xmm0 - movss 24(%rsp), %xmm1 - call JUMPTARGET(\callee) - movss %xmm0, 40(%rsp) - movss 12(%rsp), %xmm0 - movss 28(%rsp), %xmm1 - call JUMPTARGET(\callee) - movss 32(%rsp), %xmm3 - movss 36(%rsp), %xmm2 - movss 40(%rsp), %xmm1 - movss %xmm0, 44(%rsp) - unpcklps %xmm1, %xmm3 - unpcklps %xmm0, %xmm2 - unpcklps %xmm2, %xmm3 - movaps %xmm3, %xmm0 - addq $56, %rsp - cfi_adjust_cfa_offset(-56) - ret + subq $56, %rsp + cfi_adjust_cfa_offset (56) + movaps %xmm0, (%rsp) + movaps %xmm1, 16(%rsp) + call JUMPTARGET(\callee) + movss %xmm0, 32(%rsp) + movss 4(%rsp), %xmm0 + movss 20(%rsp), %xmm1 + call JUMPTARGET(\callee) + movss %xmm0, 36(%rsp) + movss 8(%rsp), %xmm0 + movss 24(%rsp), %xmm1 + call JUMPTARGET(\callee) + movss %xmm0, 40(%rsp) + movss 12(%rsp), %xmm0 + movss 28(%rsp), %xmm1 + call JUMPTARGET(\callee) + movss 32(%rsp), %xmm3 + movss 36(%rsp), %xmm2 + movss 40(%rsp), %xmm1 + movss %xmm0, 44(%rsp) + unpcklps %xmm1, %xmm3 + unpcklps %xmm0, %xmm2 + unpcklps %xmm2, %xmm3 + movaps %xmm3, %xmm0 + addq $56, %rsp + cfi_adjust_cfa_offset (-56) + ret .endm /* 3 argument SSE2 ISA version as wrapper to scalar. */ .macro WRAPPER_IMPL_SSE2_fFF callee - pushq %rbp - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%rbp, 0) - pushq %rbx - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%rbx, 0) - movq %rdi, %rbp - movq %rsi, %rbx - subq $40, %rsp - cfi_adjust_cfa_offset(40) - leaq 24(%rsp), %rsi - leaq 28(%rsp), %rdi - movaps %xmm0, (%rsp) - call JUMPTARGET(\callee) - leaq 24(%rsp), %rsi - leaq 28(%rsp), %rdi - movss 28(%rsp), %xmm0 - movss %xmm0, 0(%rbp) - movaps (%rsp), %xmm1 - movss 24(%rsp), %xmm0 - movss %xmm0, (%rbx) - movaps %xmm1, %xmm0 - shufps $85, %xmm1, %xmm0 - call JUMPTARGET(\callee) - movss 28(%rsp), %xmm0 - leaq 24(%rsp), %rsi - movss %xmm0, 4(%rbp) - leaq 28(%rsp), %rdi - movaps (%rsp), %xmm1 - movss 24(%rsp), %xmm0 - movss %xmm0, 4(%rbx) - movaps %xmm1, %xmm0 - unpckhps %xmm1, %xmm0 - call JUMPTARGET(\callee) - movaps (%rsp), %xmm1 - leaq 24(%rsp), %rsi - leaq 28(%rsp), %rdi - movss 28(%rsp), %xmm0 - shufps $255, %xmm1, %xmm1 - movss %xmm0, 8(%rbp) - movss 24(%rsp), %xmm0 - movss %xmm0, 8(%rbx) - movaps %xmm1, %xmm0 - call JUMPTARGET(\callee) - movss 28(%rsp), %xmm0 - movss %xmm0, 12(%rbp) - movss 24(%rsp), %xmm0 - movss %xmm0, 12(%rbx) - addq $40, %rsp - cfi_adjust_cfa_offset(-40) - popq %rbx - cfi_adjust_cfa_offset (-8) - cfi_restore (%rbx) - popq %rbp - cfi_adjust_cfa_offset (-8) - cfi_restore (%rbp) - ret + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + pushq %rbx + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbx, 0) + movq %rdi, %rbp + movq %rsi, %rbx + subq $40, %rsp + cfi_adjust_cfa_offset (40) + leaq 24(%rsp), %rsi + leaq 28(%rsp), %rdi + movaps %xmm0, (%rsp) + call JUMPTARGET(\callee) + leaq 24(%rsp), %rsi + leaq 28(%rsp), %rdi + movss 28(%rsp), %xmm0 + movss %xmm0, 0(%rbp) + movaps (%rsp), %xmm1 + movss 24(%rsp), %xmm0 + movss %xmm0, (%rbx) + movaps %xmm1, %xmm0 + shufps $85, %xmm1, %xmm0 + call JUMPTARGET(\callee) + movss 28(%rsp), %xmm0 + leaq 24(%rsp), %rsi + movss %xmm0, 4(%rbp) + leaq 28(%rsp), %rdi + movaps (%rsp), %xmm1 + movss 24(%rsp), %xmm0 + movss %xmm0, 4(%rbx) + movaps %xmm1, %xmm0 + unpckhps %xmm1, %xmm0 + call JUMPTARGET(\callee) + movaps (%rsp), %xmm1 + leaq 24(%rsp), %rsi + leaq 28(%rsp), %rdi + movss 28(%rsp), %xmm0 + shufps $255, %xmm1, %xmm1 + movss %xmm0, 8(%rbp) + movss 24(%rsp), %xmm0 + movss %xmm0, 8(%rbx) + movaps %xmm1, %xmm0 + call JUMPTARGET(\callee) + movss 28(%rsp), %xmm0 + movss %xmm0, 12(%rbp) + movss 24(%rsp), %xmm0 + movss %xmm0, 12(%rbx) + addq $40, %rsp + cfi_adjust_cfa_offset (-40) + popq %rbx + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbx) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret .endm /* AVX/AVX2 ISA version as wrapper to SSE ISA version. */ .macro WRAPPER_IMPL_AVX callee - pushq %rbp - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%rbp, 0) - movq %rsp, %rbp - cfi_def_cfa_register (%rbp) - andq $-32, %rsp - subq $32, %rsp - vextractf128 $1, %ymm0, (%rsp) - vzeroupper - call HIDDEN_JUMPTARGET(\callee) - vmovaps %xmm0, 16(%rsp) - vmovaps (%rsp), %xmm0 - call HIDDEN_JUMPTARGET(\callee) - vmovaps %xmm0, %xmm1 - vmovaps 16(%rsp), %xmm0 - vinsertf128 $1, %xmm1, %ymm0, %ymm0 - movq %rbp, %rsp - cfi_def_cfa_register (%rsp) - popq %rbp - cfi_adjust_cfa_offset (-8) - cfi_restore (%rbp) - ret + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-32, %rsp + subq $32, %rsp + vextractf128 $1, %ymm0, (%rsp) + vzeroupper + call HIDDEN_JUMPTARGET(\callee) + vmovaps %xmm0, 16(%rsp) + vmovaps (%rsp), %xmm0 + call HIDDEN_JUMPTARGET(\callee) + vmovaps %xmm0, %xmm1 + vmovaps 16(%rsp), %xmm0 + vinsertf128 $1, %xmm1, %ymm0, %ymm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret .endm /* 2 argument AVX/AVX2 ISA version as wrapper to SSE ISA version. */ .macro WRAPPER_IMPL_AVX_ff callee - pushq %rbp - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%rbp, 0) - movq %rsp, %rbp - cfi_def_cfa_register (%rbp) - andq $-32, %rsp - subq $64, %rsp - vextractf128 $1, %ymm0, 16(%rsp) - vextractf128 $1, %ymm1, (%rsp) - vzeroupper - call HIDDEN_JUMPTARGET(\callee) - vmovaps %xmm0, 32(%rsp) - vmovaps 16(%rsp), %xmm0 - vmovaps (%rsp), %xmm1 - call HIDDEN_JUMPTARGET(\callee) - vmovaps %xmm0, %xmm1 - vmovaps 32(%rsp), %xmm0 - vinsertf128 $1, %xmm1, %ymm0, %ymm0 - movq %rbp, %rsp - cfi_def_cfa_register (%rsp) - popq %rbp - cfi_adjust_cfa_offset (-8) - cfi_restore (%rbp) - ret + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-32, %rsp + subq $64, %rsp + vextractf128 $1, %ymm0, 16(%rsp) + vextractf128 $1, %ymm1, (%rsp) + vzeroupper + call HIDDEN_JUMPTARGET(\callee) + vmovaps %xmm0, 32(%rsp) + vmovaps 16(%rsp), %xmm0 + vmovaps (%rsp), %xmm1 + call HIDDEN_JUMPTARGET(\callee) + vmovaps %xmm0, %xmm1 + vmovaps 32(%rsp), %xmm0 + vinsertf128 $1, %xmm1, %ymm0, %ymm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret .endm /* 3 argument AVX/AVX2 ISA version as wrapper to SSE ISA version. */ .macro WRAPPER_IMPL_AVX_fFF callee - pushq %rbp - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%rbp, 0) - movq %rsp, %rbp - cfi_def_cfa_register (%rbp) - andq $-32, %rsp - pushq %r13 - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%r13, 0) - pushq %r14 - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%r14, 0) - subq $48, %rsp - movq %rsi, %r14 - vmovaps %ymm0, (%rsp) - movq %rdi, %r13 - vmovaps 16(%rsp), %xmm1 - vmovaps %xmm1, 32(%rsp) - vzeroupper - vmovaps (%rsp), %xmm0 - call HIDDEN_JUMPTARGET(\callee) - vmovaps 32(%rsp), %xmm0 - lea (%rsp), %rdi - lea 16(%rsp), %rsi - call HIDDEN_JUMPTARGET(\callee) - vmovaps (%rsp), %xmm0 - vmovaps 16(%rsp), %xmm1 - vmovaps %xmm0, 16(%r13) - vmovaps %xmm1, 16(%r14) - addq $48, %rsp - popq %r14 - cfi_adjust_cfa_offset (-8) - cfi_restore (%r14) - popq %r13 - cfi_adjust_cfa_offset (-8) - cfi_restore (%r13) - movq %rbp, %rsp - cfi_def_cfa_register (%rsp) - popq %rbp - cfi_adjust_cfa_offset (-8) - cfi_restore (%rbp) - ret + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-32, %rsp + pushq %r13 + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%r13, 0) + pushq %r14 + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%r14, 0) + subq $48, %rsp + movq %rsi, %r14 + vmovaps %ymm0, (%rsp) + movq %rdi, %r13 + vmovaps 16(%rsp), %xmm1 + vmovaps %xmm1, 32(%rsp) + vzeroupper + vmovaps (%rsp), %xmm0 + call HIDDEN_JUMPTARGET(\callee) + vmovaps 32(%rsp), %xmm0 + lea (%rsp), %rdi + lea 16(%rsp), %rsi + call HIDDEN_JUMPTARGET(\callee) + vmovaps (%rsp), %xmm0 + vmovaps 16(%rsp), %xmm1 + vmovaps %xmm0, 16(%r13) + vmovaps %xmm1, 16(%r14) + addq $48, %rsp + popq %r14 + cfi_adjust_cfa_offset (-8) + cfi_restore (%r14) + popq %r13 + cfi_adjust_cfa_offset (-8) + cfi_restore (%r13) + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret .endm /* AVX512 ISA version as wrapper to AVX2 ISA version. */ .macro WRAPPER_IMPL_AVX512 callee - pushq %rbp - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%rbp, 0) - movq %rsp, %rbp - cfi_def_cfa_register (%rbp) - andq $-64, %rsp - subq $128, %rsp - vmovups %zmm0, (%rsp) - vmovupd (%rsp), %ymm0 - call HIDDEN_JUMPTARGET(\callee) - vmovupd %ymm0, 64(%rsp) - vmovupd 32(%rsp), %ymm0 - call HIDDEN_JUMPTARGET(\callee) - vmovupd %ymm0, 96(%rsp) - vmovups 64(%rsp), %zmm0 - movq %rbp, %rsp - cfi_def_cfa_register (%rsp) - popq %rbp - cfi_adjust_cfa_offset (-8) - cfi_restore (%rbp) - ret + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $128, %rsp + vmovups %zmm0, (%rsp) + vmovupd (%rsp), %ymm0 + call HIDDEN_JUMPTARGET(\callee) + vmovupd %ymm0, 64(%rsp) + vmovupd 32(%rsp), %ymm0 + call HIDDEN_JUMPTARGET(\callee) + vmovupd %ymm0, 96(%rsp) + vmovups 64(%rsp), %zmm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret .endm /* 2 argument AVX512 ISA version as wrapper to AVX2 ISA version. */ .macro WRAPPER_IMPL_AVX512_ff callee - pushq %rbp - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%rbp, 0) - movq %rsp, %rbp - cfi_def_cfa_register (%rbp) - andq $-64, %rsp - subq $192, %rsp - vmovups %zmm0, (%rsp) - vmovups %zmm1, 64(%rsp) - vmovups (%rsp), %ymm0 - vmovups 64(%rsp), %ymm1 - call HIDDEN_JUMPTARGET(\callee) - vmovups %ymm0, 128(%rsp) - vmovups 32(%rsp), %ymm0 - vmovups 96(%rsp), %ymm1 - call HIDDEN_JUMPTARGET(\callee) - vmovups %ymm0, 160(%rsp) - vmovups 128(%rsp), %zmm0 - movq %rbp, %rsp - cfi_def_cfa_register (%rsp) - popq %rbp - cfi_adjust_cfa_offset (-8) - cfi_restore (%rbp) - ret + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $192, %rsp + vmovups %zmm0, (%rsp) + vmovups %zmm1, 64(%rsp) + vmovups (%rsp), %ymm0 + vmovups 64(%rsp), %ymm1 + call HIDDEN_JUMPTARGET(\callee) + vmovups %ymm0, 128(%rsp) + vmovups 32(%rsp), %ymm0 + vmovups 96(%rsp), %ymm1 + call HIDDEN_JUMPTARGET(\callee) + vmovups %ymm0, 160(%rsp) + vmovups 128(%rsp), %zmm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret .endm /* 3 argument AVX512 ISA version as wrapper to AVX2 ISA version. */ .macro WRAPPER_IMPL_AVX512_fFF callee - pushq %rbp - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%rbp, 0) - movq %rsp, %rbp - cfi_def_cfa_register (%rbp) - andq $-64, %rsp - pushq %r12 - pushq %r13 - subq $176, %rsp - movq %rsi, %r13 - vmovaps %zmm0, (%rsp) - movq %rdi, %r12 - vmovaps (%rsp), %ymm0 - call HIDDEN_JUMPTARGET(\callee) - vmovaps 32(%rsp), %ymm0 - lea 64(%rsp), %rdi - lea 96(%rsp), %rsi - call HIDDEN_JUMPTARGET(\callee) - vmovaps 64(%rsp), %ymm0 - vmovaps 96(%rsp), %ymm1 - vmovaps %ymm0, 32(%r12) - vmovaps %ymm1, 32(%r13) - addq $176, %rsp - popq %r13 - popq %r12 - movq %rbp, %rsp - cfi_def_cfa_register (%rsp) - popq %rbp - cfi_adjust_cfa_offset (-8) - cfi_restore (%rbp) - ret + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + pushq %r12 + pushq %r13 + subq $176, %rsp + movq %rsi, %r13 + vmovaps %zmm0, (%rsp) + movq %rdi, %r12 + vmovaps (%rsp), %ymm0 + call HIDDEN_JUMPTARGET(\callee) + vmovaps 32(%rsp), %ymm0 + lea 64(%rsp), %rdi + lea 96(%rsp), %rsi + call HIDDEN_JUMPTARGET(\callee) + vmovaps 64(%rsp), %ymm0 + vmovaps 96(%rsp), %ymm1 + vmovaps %ymm0, 32(%r12) + vmovaps %ymm1, 32(%r13) + addq $176, %rsp + popq %r13 + popq %r12 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret .endm From patchwork Fri Nov 18 06:37:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Noah Goldstein X-Patchwork-Id: 60815 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A0FCB3852C40 for ; Fri, 18 Nov 2022 06:38:53 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A0FCB3852C40 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1668753533; bh=QceNBnNgEWH9AqG8/WrDK+Sk6u2hTbDopCaYutWgKt8=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=prAOUYcYxuUZMlOqQkv2lIZTnltA8dKC3vsYC7zoU5t+av+Oq5lNvjUSqm6Dn6x/A Y6XAdRNG0Z+UKqpO/NMZDFPGD07m/20Q7hN6c3kNtx2h+slMSDCriIq5xQWjRv2azB kL99iKbFof6Xd7+mroFLf4a3WUkf3h2bRYsJnOvc= X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by sourceware.org (Postfix) with ESMTPS id 31F4B3854574 for ; Fri, 18 Nov 2022 06:37:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 31F4B3854574 Received: by mail-pl1-x635.google.com with SMTP id jn7so1897876plb.13 for ; Thu, 17 Nov 2022 22:37:33 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QceNBnNgEWH9AqG8/WrDK+Sk6u2hTbDopCaYutWgKt8=; b=1Zk413IkoiBaZMVOr3twpcL7auMCzLwiNI+QyGlF5EIi28WgfK3c2z6TzfUQ3NtpbM AiyJ35xNPWUIwMDBQ3Rbanj9K2979AdX/gjwt9DT5S4hEB6kEvOJelcwtsAJOm73uKtM ZcPrq3MkoLB02gZ5o4qnqcFMjPfavjR4Ry8N4AA09lKyX7QuIBqQ35fv6xJKNV13FPzj dZbTGhTh054iY/Ce2v1cIFwmqRBZyRJv8jqHVZCO1/CQZH0A4aIHCy8ZALObJbnSkZL6 d+RizEWpVjxBRD0HdIhvme/HEGRklbBuKBuL3L4RVevxDwbG4omJmfGidQDCc+R456tL swiQ== X-Gm-Message-State: ANoB5pliZBt1RMQJbtsS+bVyktrXBWudhvL1xqeFQGAhs8qC2ejwnqs0 O9nFyXbzzztKMqY3v4cE4r/tBO/VEzQ= X-Google-Smtp-Source: AA0mqf5kpyAQbGIpU7WRGEiMJgQU8xeSa1khaUaIppO3mMNRkqVcUJjLlibh2L6S2vFS+u+b0QnlGQ== X-Received: by 2002:a17:902:8e87:b0:186:9fb9:1f88 with SMTP id bg7-20020a1709028e8700b001869fb91f88mr6305989plb.24.1668753451457; Thu, 17 Nov 2022 22:37:31 -0800 (PST) Received: from noahgold-desk.. ([192.55.60.47]) by smtp.gmail.com with ESMTPSA id j7-20020a170902da8700b00176a6ba5969sm2670692plx.98.2022.11.17.22.37.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 17 Nov 2022 22:37:30 -0800 (PST) To: libc-alpha@sourceware.org Cc: goldstein.w.n@gmail.com, hjl.tools@gmail.com, carlos@systemhalted.org Subject: [PATCH v1 3/3] x86/fpu: Cleanup code in svml_{s|d}_wrapper_impl.h.S Date: Thu, 17 Nov 2022 22:37:23 -0800 Message-Id: <20221118063723.858936-3-goldstein.w.n@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221118063723.858936-1-goldstein.w.n@gmail.com> References: <20221118063723.858936-1-goldstein.w.n@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Noah Goldstein via Libc-alpha From: Noah Goldstein Reply-To: Noah Goldstein Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org Sender: "Libc-alpha" 1. Remove unnecessary spills. 2. Split the shared avx/avx512 wrappers to a new file. 3. Fix some small nit missed optimizations. All math and mathvec tests pass on x86. --- sysdeps/x86_64/fpu/svml_d_wrapper_impl.h.S | 253 ++-------------- sysdeps/x86_64/fpu/svml_s_wrapper_impl.h.S | 309 ++++---------------- sysdeps/x86_64/fpu/svml_sd_wrapper_impl.h.S | 186 ++++++++++++ 3 files changed, 262 insertions(+), 486 deletions(-) create mode 100644 sysdeps/x86_64/fpu/svml_sd_wrapper_impl.h.S diff --git a/sysdeps/x86_64/fpu/svml_d_wrapper_impl.h.S b/sysdeps/x86_64/fpu/svml_d_wrapper_impl.h.S index b03a2122b9..e54c16ea6e 100644 --- a/sysdeps/x86_64/fpu/svml_d_wrapper_impl.h.S +++ b/sysdeps/x86_64/fpu/svml_d_wrapper_impl.h.S @@ -18,39 +18,38 @@ /* SSE2 ISA version as wrapper to scalar. */ .macro WRAPPER_IMPL_SSE2 callee - subq $40, %rsp - cfi_adjust_cfa_offset (40) + subq $24, %rsp + cfi_adjust_cfa_offset (24) movaps %xmm0, (%rsp) call JUMPTARGET(\callee) - movsd %xmm0, 16(%rsp) + movsd %xmm0, (%rsp) movsd 8(%rsp), %xmm0 call JUMPTARGET(\callee) - movsd 16(%rsp), %xmm1 - movsd %xmm0, 24(%rsp) + movsd (%rsp), %xmm1 unpcklpd %xmm0, %xmm1 movaps %xmm1, %xmm0 - addq $40, %rsp - cfi_adjust_cfa_offset (-40) + addq $24, %rsp + cfi_adjust_cfa_offset (-24) ret .endm + /* 2 argument SSE2 ISA version as wrapper to scalar. */ .macro WRAPPER_IMPL_SSE2_ff callee - subq $56, %rsp - cfi_adjust_cfa_offset (56) + subq $40, %rsp + cfi_adjust_cfa_offset (40) movaps %xmm0, (%rsp) movaps %xmm1, 16(%rsp) call JUMPTARGET(\callee) - movsd %xmm0, 32(%rsp) + movsd %xmm0, (%rsp) movsd 8(%rsp), %xmm0 movsd 24(%rsp), %xmm1 call JUMPTARGET(\callee) - movsd 32(%rsp), %xmm1 - movsd %xmm0, 40(%rsp) + movsd (%rsp), %xmm1 unpcklpd %xmm0, %xmm1 movaps %xmm1, %xmm0 - addq $56, %rsp - cfi_adjust_cfa_offset (-56) + addq $40, %rsp + cfi_adjust_cfa_offset (-40) ret .endm @@ -62,229 +61,25 @@ pushq %rbx cfi_adjust_cfa_offset (8) cfi_rel_offset (%rbx, 0) + subq $24, %rsp + cfi_adjust_cfa_offset (24) + movaps %xmm0, (%rsp) movq %rdi, %rbp movq %rsi, %rbx - subq $40, %rsp - cfi_adjust_cfa_offset (40) - leaq 16(%rsp), %rsi - leaq 24(%rsp), %rdi - movaps %xmm0, (%rsp) call JUMPTARGET(\callee) - leaq 16(%rsp), %rsi - leaq 24(%rsp), %rdi - movsd 24(%rsp), %xmm0 - movapd (%rsp), %xmm1 - movsd %xmm0, 0(%rbp) - unpckhpd %xmm1, %xmm1 - movsd 16(%rsp), %xmm0 - movsd %xmm0, (%rbx) - movapd %xmm1, %xmm0 + movsd 8(%rsp), %xmm0 + leaq 8(%rbp), %rdi + leaq 8(%rbx), %rsi call JUMPTARGET(\callee) - movsd 24(%rsp), %xmm0 - movsd %xmm0, 8(%rbp) - movsd 16(%rsp), %xmm0 - movsd %xmm0, 8(%rbx) - addq $40, %rsp - cfi_adjust_cfa_offset (-40) - popq %rbx + addq $24, %rsp + cfi_adjust_cfa_offset (-24) + pop %rbx cfi_adjust_cfa_offset (-8) cfi_restore (%rbx) - popq %rbp - cfi_adjust_cfa_offset (-8) - cfi_restore (%rbp) - ret -.endm - -/* AVX/AVX2 ISA version as wrapper to SSE ISA version. */ -.macro WRAPPER_IMPL_AVX callee - pushq %rbp - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%rbp, 0) - movq %rsp, %rbp - cfi_def_cfa_register (%rbp) - andq $-32, %rsp - subq $32, %rsp - vextractf128 $1, %ymm0, (%rsp) - vzeroupper - call HIDDEN_JUMPTARGET(\callee) - vmovapd %xmm0, 16(%rsp) - vmovaps (%rsp), %xmm0 - call HIDDEN_JUMPTARGET(\callee) - vmovapd %xmm0, %xmm1 - vmovapd 16(%rsp), %xmm0 - vinsertf128 $1, %xmm1, %ymm0, %ymm0 - movq %rbp, %rsp - cfi_def_cfa_register (%rsp) - popq %rbp - cfi_adjust_cfa_offset (-8) - cfi_restore (%rbp) - ret -.endm - -/* 2 argument AVX/AVX2 ISA version as wrapper to SSE ISA version. */ -.macro WRAPPER_IMPL_AVX_ff callee - pushq %rbp - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%rbp, 0) - movq %rsp, %rbp - cfi_def_cfa_register (%rbp) - andq $-32, %rsp - subq $64, %rsp - vextractf128 $1, %ymm0, 16(%rsp) - vextractf128 $1, %ymm1, (%rsp) - vzeroupper - call HIDDEN_JUMPTARGET(\callee) - vmovaps %xmm0, 32(%rsp) - vmovaps 16(%rsp), %xmm0 - vmovaps (%rsp), %xmm1 - call HIDDEN_JUMPTARGET(\callee) - vmovaps %xmm0, %xmm1 - vmovaps 32(%rsp), %xmm0 - vinsertf128 $1, %xmm1, %ymm0, %ymm0 - movq %rbp, %rsp - cfi_def_cfa_register (%rsp) - popq %rbp + pop %rbp cfi_adjust_cfa_offset (-8) cfi_restore (%rbp) ret .endm -/* 3 argument AVX/AVX2 ISA version as wrapper to SSE ISA version. */ -.macro WRAPPER_IMPL_AVX_fFF callee - pushq %rbp - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%rbp, 0) - movq %rsp, %rbp - cfi_def_cfa_register (%rbp) - andq $-32, %rsp - pushq %r13 - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%r13, 0) - pushq %r14 - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%r14, 0) - subq $48, %rsp - movq %rsi, %r14 - movq %rdi, %r13 - vextractf128 $1, %ymm0, 32(%rsp) - vzeroupper - call HIDDEN_JUMPTARGET(\callee) - vmovaps 32(%rsp), %xmm0 - lea (%rsp), %rdi - lea 16(%rsp), %rsi - call HIDDEN_JUMPTARGET(\callee) - vmovapd (%rsp), %xmm0 - vmovapd 16(%rsp), %xmm1 - vmovapd %xmm0, 16(%r13) - vmovapd %xmm1, 16(%r14) - addq $48, %rsp - popq %r14 - cfi_adjust_cfa_offset (-8) - cfi_restore (%r14) - popq %r13 - cfi_adjust_cfa_offset (-8) - cfi_restore (%r13) - movq %rbp, %rsp - cfi_def_cfa_register (%rsp) - popq %rbp - cfi_adjust_cfa_offset (-8) - cfi_restore (%rbp) - ret -.endm - -/* AVX512 ISA version as wrapper to AVX2 ISA version. */ -.macro WRAPPER_IMPL_AVX512 callee - pushq %rbp - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%rbp, 0) - movq %rsp, %rbp - cfi_def_cfa_register (%rbp) - andq $-64, %rsp - subq $128, %rsp - vmovups %zmm0, (%rsp) - vmovupd (%rsp), %ymm0 - call HIDDEN_JUMPTARGET(\callee) - vmovupd %ymm0, 64(%rsp) - vmovupd 32(%rsp), %ymm0 - call HIDDEN_JUMPTARGET(\callee) - vmovupd %ymm0, 96(%rsp) - vmovups 64(%rsp), %zmm0 - movq %rbp, %rsp - cfi_def_cfa_register (%rsp) - popq %rbp - cfi_adjust_cfa_offset (-8) - cfi_restore (%rbp) - ret -.endm - -/* 2 argument AVX512 ISA version as wrapper to AVX2 ISA version. */ -.macro WRAPPER_IMPL_AVX512_ff callee - pushq %rbp - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%rbp, 0) - movq %rsp, %rbp - cfi_def_cfa_register (%rbp) - andq $-64, %rsp - subq $192, %rsp - vmovups %zmm0, (%rsp) - vmovups %zmm1, 64(%rsp) - vmovupd (%rsp), %ymm0 - vmovupd 64(%rsp), %ymm1 - call HIDDEN_JUMPTARGET(\callee) - vmovupd %ymm0, 128(%rsp) - vmovupd 32(%rsp), %ymm0 - vmovupd 96(%rsp), %ymm1 - call HIDDEN_JUMPTARGET(\callee) - vmovupd %ymm0, 160(%rsp) - vmovups 128(%rsp), %zmm0 - movq %rbp, %rsp - cfi_def_cfa_register (%rsp) - popq %rbp - cfi_adjust_cfa_offset (-8) - cfi_restore (%rbp) - ret -.endm - -/* 3 argument AVX512 ISA version as wrapper to AVX2 ISA version. */ -.macro WRAPPER_IMPL_AVX512_fFF callee - pushq %rbp - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%rbp, 0) - movq %rsp, %rbp - cfi_def_cfa_register (%rbp) - andq $-64, %rsp - pushq %r12 - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%r12, 0) - pushq %r13 - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%r13, 0) - subq $176, %rsp - movq %rsi, %r13 - vmovups %zmm0, (%rsp) - movq %rdi, %r12 - vmovupd (%rsp), %ymm0 - call HIDDEN_JUMPTARGET(\callee) - vmovupd 32(%rsp), %ymm0 - lea 64(%rsp), %rdi - lea 96(%rsp), %rsi - call HIDDEN_JUMPTARGET(\callee) - vmovupd 64(%rsp), %ymm0 - vmovupd 96(%rsp), %ymm1 - vmovupd %ymm0, 32(%r12) - vmovupd %ymm1, 32(%r13) - vzeroupper - addq $176, %rsp - popq %r13 - cfi_adjust_cfa_offset (-8) - cfi_restore (%r13) - popq %r12 - cfi_adjust_cfa_offset (-8) - cfi_restore (%r12) - movq %rbp, %rsp - cfi_def_cfa_register (%rsp) - popq %rbp - cfi_adjust_cfa_offset (-8) - cfi_restore (%rbp) - ret -.endm +#include "svml_sd_wrapper_impl.h.S" diff --git a/sysdeps/x86_64/fpu/svml_s_wrapper_impl.h.S b/sysdeps/x86_64/fpu/svml_s_wrapper_impl.h.S index cecf6c8384..958d1be243 100644 --- a/sysdeps/x86_64/fpu/svml_s_wrapper_impl.h.S +++ b/sysdeps/x86_64/fpu/svml_s_wrapper_impl.h.S @@ -18,61 +18,66 @@ /* SSE2 ISA version as wrapper to scalar. */ .macro WRAPPER_IMPL_SSE2 callee - subq $40, %rsp - cfi_adjust_cfa_offset (40) + push %rbx + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbx, 0) + subq $16, %rsp + cfi_adjust_cfa_offset (16) movaps %xmm0, (%rsp) call JUMPTARGET(\callee) - movss %xmm0, 16(%rsp) + movss %xmm0, (%rsp) movss 4(%rsp), %xmm0 call JUMPTARGET(\callee) - movss %xmm0, 20(%rsp) + movss %xmm0, 4(%rsp) movss 8(%rsp), %xmm0 call JUMPTARGET(\callee) - movss %xmm0, 24(%rsp) + movd %xmm0, %ebx movss 12(%rsp), %xmm0 call JUMPTARGET(\callee) - movss 16(%rsp), %xmm3 - movss 20(%rsp), %xmm2 - movss 24(%rsp), %xmm1 - movss %xmm0, 28(%rsp) - unpcklps %xmm1, %xmm3 - unpcklps %xmm0, %xmm2 - unpcklps %xmm2, %xmm3 - movaps %xmm3, %xmm0 - addq $40, %rsp - cfi_adjust_cfa_offset (-40) + movd %ebx, %xmm1 + unpcklps %xmm0, %xmm1 + movsd (%rsp), %xmm0 + unpcklpd %xmm1, %xmm0 + addq $16, %rsp + cfi_adjust_cfa_offset (-16) + pop %rbx + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbx) ret .endm /* 2 argument SSE2 ISA version as wrapper to scalar. */ .macro WRAPPER_IMPL_SSE2_ff callee - subq $56, %rsp - cfi_adjust_cfa_offset (56) + push %rbx + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbx, 0) + subq $32, %rsp + cfi_adjust_cfa_offset (40) movaps %xmm0, (%rsp) movaps %xmm1, 16(%rsp) call JUMPTARGET(\callee) - movss %xmm0, 32(%rsp) - movss 4(%rsp), %xmm0 movss 20(%rsp), %xmm1 + movss %xmm0, 0(%rsp) + movss 4(%rsp), %xmm0 call JUMPTARGET(\callee) - movss %xmm0, 36(%rsp) - movss 8(%rsp), %xmm0 movss 24(%rsp), %xmm1 + movss %xmm0, 4(%rsp) + movss 8(%rsp), %xmm0 call JUMPTARGET(\callee) - movss %xmm0, 40(%rsp) - movss 12(%rsp), %xmm0 movss 28(%rsp), %xmm1 + movd %xmm0, %ebx + movss 12(%rsp), %xmm0 call JUMPTARGET(\callee) - movss 32(%rsp), %xmm3 - movss 36(%rsp), %xmm2 - movss 40(%rsp), %xmm1 - movss %xmm0, 44(%rsp) - unpcklps %xmm1, %xmm3 - unpcklps %xmm0, %xmm2 - unpcklps %xmm2, %xmm3 - movaps %xmm3, %xmm0 - addq $56, %rsp - cfi_adjust_cfa_offset (-56) + /* merge 4x results into xmm0. */ + movd %ebx, %xmm1 + unpcklps %xmm0, %xmm1 + movsd (%rsp), %xmm0 + unpcklpd %xmm1, %xmm0 + addq $32, %rsp + cfi_adjust_cfa_offset (-32) + pop %rbx + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbx) ret .endm @@ -86,48 +91,24 @@ cfi_rel_offset (%rbx, 0) movq %rdi, %rbp movq %rsi, %rbx - subq $40, %rsp - cfi_adjust_cfa_offset (40) - leaq 24(%rsp), %rsi - leaq 28(%rsp), %rdi + subq $24, %rsp + cfi_adjust_cfa_offset (24) movaps %xmm0, (%rsp) call JUMPTARGET(\callee) - leaq 24(%rsp), %rsi - leaq 28(%rsp), %rdi - movss 28(%rsp), %xmm0 - movss %xmm0, 0(%rbp) - movaps (%rsp), %xmm1 - movss 24(%rsp), %xmm0 - movss %xmm0, (%rbx) - movaps %xmm1, %xmm0 - shufps $85, %xmm1, %xmm0 + movss 4(%rsp), %xmm0 + leaq 4(%rbp), %rdi + leaq 4(%rbx), %rsi call JUMPTARGET(\callee) - movss 28(%rsp), %xmm0 - leaq 24(%rsp), %rsi - movss %xmm0, 4(%rbp) - leaq 28(%rsp), %rdi - movaps (%rsp), %xmm1 - movss 24(%rsp), %xmm0 - movss %xmm0, 4(%rbx) - movaps %xmm1, %xmm0 - unpckhps %xmm1, %xmm0 + movss 8(%rsp), %xmm0 + leaq 8(%rbp), %rdi + leaq 8(%rbx), %rsi call JUMPTARGET(\callee) - movaps (%rsp), %xmm1 - leaq 24(%rsp), %rsi - leaq 28(%rsp), %rdi - movss 28(%rsp), %xmm0 - shufps $255, %xmm1, %xmm1 - movss %xmm0, 8(%rbp) - movss 24(%rsp), %xmm0 - movss %xmm0, 8(%rbx) - movaps %xmm1, %xmm0 + movss 12(%rsp), %xmm0 + leaq 12(%rbp), %rdi + leaq 12(%rbx), %rsi call JUMPTARGET(\callee) - movss 28(%rsp), %xmm0 - movss %xmm0, 12(%rbp) - movss 24(%rsp), %xmm0 - movss %xmm0, 12(%rbx) - addq $40, %rsp - cfi_adjust_cfa_offset (-40) + addq $24, %rsp + cfi_adjust_cfa_offset (-24) popq %rbx cfi_adjust_cfa_offset (-8) cfi_restore (%rbx) @@ -137,190 +118,4 @@ ret .endm -/* AVX/AVX2 ISA version as wrapper to SSE ISA version. */ -.macro WRAPPER_IMPL_AVX callee - pushq %rbp - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%rbp, 0) - movq %rsp, %rbp - cfi_def_cfa_register (%rbp) - andq $-32, %rsp - subq $32, %rsp - vextractf128 $1, %ymm0, (%rsp) - vzeroupper - call HIDDEN_JUMPTARGET(\callee) - vmovaps %xmm0, 16(%rsp) - vmovaps (%rsp), %xmm0 - call HIDDEN_JUMPTARGET(\callee) - vmovaps %xmm0, %xmm1 - vmovaps 16(%rsp), %xmm0 - vinsertf128 $1, %xmm1, %ymm0, %ymm0 - movq %rbp, %rsp - cfi_def_cfa_register (%rsp) - popq %rbp - cfi_adjust_cfa_offset (-8) - cfi_restore (%rbp) - ret -.endm - -/* 2 argument AVX/AVX2 ISA version as wrapper to SSE ISA version. */ -.macro WRAPPER_IMPL_AVX_ff callee - pushq %rbp - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%rbp, 0) - movq %rsp, %rbp - cfi_def_cfa_register (%rbp) - andq $-32, %rsp - subq $64, %rsp - vextractf128 $1, %ymm0, 16(%rsp) - vextractf128 $1, %ymm1, (%rsp) - vzeroupper - call HIDDEN_JUMPTARGET(\callee) - vmovaps %xmm0, 32(%rsp) - vmovaps 16(%rsp), %xmm0 - vmovaps (%rsp), %xmm1 - call HIDDEN_JUMPTARGET(\callee) - vmovaps %xmm0, %xmm1 - vmovaps 32(%rsp), %xmm0 - vinsertf128 $1, %xmm1, %ymm0, %ymm0 - movq %rbp, %rsp - cfi_def_cfa_register (%rsp) - popq %rbp - cfi_adjust_cfa_offset (-8) - cfi_restore (%rbp) - ret -.endm - -/* 3 argument AVX/AVX2 ISA version as wrapper to SSE ISA version. */ -.macro WRAPPER_IMPL_AVX_fFF callee - pushq %rbp - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%rbp, 0) - movq %rsp, %rbp - cfi_def_cfa_register (%rbp) - andq $-32, %rsp - pushq %r13 - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%r13, 0) - pushq %r14 - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%r14, 0) - subq $48, %rsp - movq %rsi, %r14 - vmovaps %ymm0, (%rsp) - movq %rdi, %r13 - vmovaps 16(%rsp), %xmm1 - vmovaps %xmm1, 32(%rsp) - vzeroupper - vmovaps (%rsp), %xmm0 - call HIDDEN_JUMPTARGET(\callee) - vmovaps 32(%rsp), %xmm0 - lea (%rsp), %rdi - lea 16(%rsp), %rsi - call HIDDEN_JUMPTARGET(\callee) - vmovaps (%rsp), %xmm0 - vmovaps 16(%rsp), %xmm1 - vmovaps %xmm0, 16(%r13) - vmovaps %xmm1, 16(%r14) - addq $48, %rsp - popq %r14 - cfi_adjust_cfa_offset (-8) - cfi_restore (%r14) - popq %r13 - cfi_adjust_cfa_offset (-8) - cfi_restore (%r13) - movq %rbp, %rsp - cfi_def_cfa_register (%rsp) - popq %rbp - cfi_adjust_cfa_offset (-8) - cfi_restore (%rbp) - ret -.endm - -/* AVX512 ISA version as wrapper to AVX2 ISA version. */ -.macro WRAPPER_IMPL_AVX512 callee - pushq %rbp - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%rbp, 0) - movq %rsp, %rbp - cfi_def_cfa_register (%rbp) - andq $-64, %rsp - subq $128, %rsp - vmovups %zmm0, (%rsp) - vmovupd (%rsp), %ymm0 - call HIDDEN_JUMPTARGET(\callee) - vmovupd %ymm0, 64(%rsp) - vmovupd 32(%rsp), %ymm0 - call HIDDEN_JUMPTARGET(\callee) - vmovupd %ymm0, 96(%rsp) - vmovups 64(%rsp), %zmm0 - movq %rbp, %rsp - cfi_def_cfa_register (%rsp) - popq %rbp - cfi_adjust_cfa_offset (-8) - cfi_restore (%rbp) - ret -.endm - -/* 2 argument AVX512 ISA version as wrapper to AVX2 ISA version. */ -.macro WRAPPER_IMPL_AVX512_ff callee - pushq %rbp - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%rbp, 0) - movq %rsp, %rbp - cfi_def_cfa_register (%rbp) - andq $-64, %rsp - subq $192, %rsp - vmovups %zmm0, (%rsp) - vmovups %zmm1, 64(%rsp) - vmovups (%rsp), %ymm0 - vmovups 64(%rsp), %ymm1 - call HIDDEN_JUMPTARGET(\callee) - vmovups %ymm0, 128(%rsp) - vmovups 32(%rsp), %ymm0 - vmovups 96(%rsp), %ymm1 - call HIDDEN_JUMPTARGET(\callee) - vmovups %ymm0, 160(%rsp) - vmovups 128(%rsp), %zmm0 - movq %rbp, %rsp - cfi_def_cfa_register (%rsp) - popq %rbp - cfi_adjust_cfa_offset (-8) - cfi_restore (%rbp) - ret -.endm - -/* 3 argument AVX512 ISA version as wrapper to AVX2 ISA version. */ -.macro WRAPPER_IMPL_AVX512_fFF callee - pushq %rbp - cfi_adjust_cfa_offset (8) - cfi_rel_offset (%rbp, 0) - movq %rsp, %rbp - cfi_def_cfa_register (%rbp) - andq $-64, %rsp - pushq %r12 - pushq %r13 - subq $176, %rsp - movq %rsi, %r13 - vmovaps %zmm0, (%rsp) - movq %rdi, %r12 - vmovaps (%rsp), %ymm0 - call HIDDEN_JUMPTARGET(\callee) - vmovaps 32(%rsp), %ymm0 - lea 64(%rsp), %rdi - lea 96(%rsp), %rsi - call HIDDEN_JUMPTARGET(\callee) - vmovaps 64(%rsp), %ymm0 - vmovaps 96(%rsp), %ymm1 - vmovaps %ymm0, 32(%r12) - vmovaps %ymm1, 32(%r13) - addq $176, %rsp - popq %r13 - popq %r12 - movq %rbp, %rsp - cfi_def_cfa_register (%rsp) - popq %rbp - cfi_adjust_cfa_offset (-8) - cfi_restore (%rbp) - ret -.endm +#include "svml_sd_wrapper_impl.h.S" diff --git a/sysdeps/x86_64/fpu/svml_sd_wrapper_impl.h.S b/sysdeps/x86_64/fpu/svml_sd_wrapper_impl.h.S new file mode 100644 index 0000000000..ba5b2932af --- /dev/null +++ b/sysdeps/x86_64/fpu/svml_sd_wrapper_impl.h.S @@ -0,0 +1,186 @@ +/* Common float/double wrapper implementations of vector math + functions. + Copyright (C) 2022 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +/* AVX/AVX2 ISA version as wrapper to SSE ISA version. */ +.macro WRAPPER_IMPL_AVX callee + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-32, %rsp + subq $32, %rsp + vmovaps %ymm0, (%rsp) + vzeroupper + call HIDDEN_JUMPTARGET(\callee) + vmovaps %xmm0, (%rsp) + vmovaps 16(%rsp), %xmm0 + call HIDDEN_JUMPTARGET(\callee) + /* combine xmm0 (return of second call) with result of first + call (saved on stack). Might be worth exploring logic that + uses `vpblend` and reads in ymm1 using -16(rsp). */ + vmovaps (%rsp), %xmm1 + vinsertf128 $1, %xmm0, %ymm1, %ymm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret +.endm + +/* 2 argument AVX/AVX2 ISA version as wrapper to SSE ISA version. */ +.macro WRAPPER_IMPL_AVX_ff callee + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-32, %rsp + subq $64, %rsp + vmovaps %ymm0, (%rsp) + vmovaps %ymm1, 32(%rsp) + vzeroupper + call HIDDEN_JUMPTARGET(\callee) + vmovaps 48(%rsp), %xmm1 + vmovaps %xmm0, (%rsp) + vmovaps 16(%rsp), %xmm0 + call HIDDEN_JUMPTARGET(\callee) + /* combine xmm0 (return of second call) with result of first + call (saved on stack). Might be worth exploring logic that + uses `vpblend` and reads in ymm1 using -16(rsp). */ + vmovaps (%rsp), %xmm1 + vinsertf128 $1, %xmm0, %ymm1, %ymm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret +.endm + +/* 3 argument AVX/AVX2 ISA version as wrapper to SSE ISA version. */ +.macro WRAPPER_IMPL_AVX_fFF callee + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + andq $-32, %rsp + subq $48, %rsp + vmovaps %ymm0, 16(%rsp) + movq %rdi, (%rsp) + movq %rsi, 8(%rsp) + vzeroupper + call HIDDEN_JUMPTARGET(\callee) + vmovaps 32(%rsp), %xmm0 + movq (%rsp), %rdi + movq 8(%rsp), %rsi + addq $16, %rdi + addq $16, %rsi + call HIDDEN_JUMPTARGET(\callee) + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret +.endm + +/* AVX512 ISA version as wrapper to AVX2 ISA version. */ +.macro WRAPPER_IMPL_AVX512 callee + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $64, %rsp + vmovups %zmm0, (%rsp) + call HIDDEN_JUMPTARGET(\callee) + vmovupd %ymm0, (%rsp) + vmovupd 32(%rsp), %ymm0 + call HIDDEN_JUMPTARGET(\callee) + /* combine ymm0 (return of second call) with result of first + call (saved on stack). */ + vmovaps (%rsp), %ymm1 + vinserti64x4 $0x1, %ymm0, %zmm1, %zmm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret +.endm + +/* 2 argument AVX512 ISA version as wrapper to AVX2 ISA version. */ +.macro WRAPPER_IMPL_AVX512_ff callee + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + addq $-128, %rsp + vmovups %zmm0, (%rsp) + vmovups %zmm1, 64(%rsp) + /* ymm0 and ymm1 are already set. */ + call HIDDEN_JUMPTARGET(\callee) + vmovups 96(%rsp), %ymm1 + vmovaps %ymm0, (%rsp) + vmovups 32(%rsp), %ymm0 + call HIDDEN_JUMPTARGET(\callee) + /* combine ymm0 (return of second call) with result of first + call (saved on stack). */ + vmovaps (%rsp), %ymm1 + vinserti64x4 $0x1, %ymm0, %zmm1, %zmm0 + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret +.endm + +/* 3 argument AVX512 ISA version as wrapper to AVX2 ISA version. */ +.macro WRAPPER_IMPL_AVX512_fFF callee + pushq %rbp + cfi_adjust_cfa_offset (8) + cfi_rel_offset (%rbp, 0) + movq %rsp, %rbp + cfi_def_cfa_register (%rbp) + andq $-64, %rsp + subq $80, %rsp + vmovaps %zmm0, 16(%rsp) + movq %rdi, (%rsp) + movq %rsi, 8(%rsp) + /* ymm0 is already set. */ + call HIDDEN_JUMPTARGET(\callee) + vmovaps 48(%rsp), %ymm0 + movq (%rsp), %rdi + movq 8(%rsp), %rsi + addq $32, %rdi + addq $32, %rsi + call HIDDEN_JUMPTARGET(\callee) + movq %rbp, %rsp + cfi_def_cfa_register (%rsp) + popq %rbp + cfi_adjust_cfa_offset (-8) + cfi_restore (%rbp) + ret +.endm