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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT008.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR08MB7328 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andrea Corallo via Gcc-patches From: Andrea Corallo Reply-To: Andrea Corallo Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vcreateq_f16.c: Improve test. * gcc.target/arm/mve/intrinsics/vcreateq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcreateq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcreateq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcreateq_s64.c: Likewise. * gcc.target/arm/mve/intrinsics/vcreateq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcreateq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcreateq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcreateq_u64.c: Likewise. * gcc.target/arm/mve/intrinsics/vcreateq_u8.c: Likewise. --- .../arm/mve/intrinsics/vcreateq_f16.c | 23 ++++++++++++++++++- .../arm/mve/intrinsics/vcreateq_f32.c | 23 ++++++++++++++++++- .../arm/mve/intrinsics/vcreateq_s16.c | 23 ++++++++++++++++++- .../arm/mve/intrinsics/vcreateq_s32.c | 23 ++++++++++++++++++- .../arm/mve/intrinsics/vcreateq_s64.c | 23 ++++++++++++++++++- .../arm/mve/intrinsics/vcreateq_s8.c | 23 ++++++++++++++++++- .../arm/mve/intrinsics/vcreateq_u16.c | 23 ++++++++++++++++++- .../arm/mve/intrinsics/vcreateq_u32.c | 23 ++++++++++++++++++- .../arm/mve/intrinsics/vcreateq_u64.c | 23 ++++++++++++++++++- .../arm/mve/intrinsics/vcreateq_u8.c | 23 ++++++++++++++++++- 10 files changed, 220 insertions(+), 10 deletions(-) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f16.c index fb3601edb94..c39303daa03 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f16.c @@ -1,13 +1,34 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+] +** vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+] +** ... +*/ float16x8_t foo (uint64_t a, uint64_t b) { return vcreateq_f16 (a, b); } -/* { dg-final { scan-assembler "vmov" } } */ +/* +**foo1: +** ... +** vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+] +** vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+] +** ... +*/ +float16x8_t +foo1 () +{ + return vcreateq_f16 (1, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f32.c index 4f4da62eed7..ad66f4407cd 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_f32.c @@ -1,13 +1,34 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+] +** vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+] +** ... +*/ float32x4_t foo (uint64_t a, uint64_t b) { return vcreateq_f32 (a, b); } -/* { dg-final { scan-assembler "vmov" } } */ +/* +**foo1: +** ... +** vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+] +** vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+] +** ... +*/ +float32x4_t +foo1 () +{ + return vcreateq_f32 (1, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c index 103be6310bd..7e70a486513 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s16.c @@ -1,13 +1,34 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+] +** vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+] +** ... +*/ int16x8_t foo (uint64_t a, uint64_t b) { return vcreateq_s16 (a, b); } -/* { dg-final { scan-assembler "vmov" } } */ +/* +**foo1: +** ... +** vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+] +** vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+] +** ... +*/ +int16x8_t +foo1 () +{ + return vcreateq_s16 (1, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c index 96f7a972d93..ffcfc80ff40 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s32.c @@ -1,13 +1,34 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+] +** vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+] +** ... +*/ int32x4_t foo (uint64_t a, uint64_t b) { return vcreateq_s32 (a, b); } -/* { dg-final { scan-assembler "vmov" } } */ +/* +**foo1: +** ... +** vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+] +** vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+] +** ... +*/ +int32x4_t +foo1 () +{ + return vcreateq_s32 (1, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c index 74c554506c0..26642f9cd68 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c @@ -1,13 +1,34 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+] +** vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+] +** ... +*/ int64x2_t foo (uint64_t a, uint64_t b) { return vcreateq_s64 (a, b); } -/* { dg-final { scan-assembler "vmov" } } */ +/* +**foo1: +** ... +** vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+] +** vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+] +** ... +*/ +int64x2_t +foo1 () +{ + return vcreateq_s64 (1, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c index 03c50a0928a..7e7e4d5948d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c @@ -1,13 +1,34 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+] +** vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+] +** ... +*/ int8x16_t foo (uint64_t a, uint64_t b) { return vcreateq_s8 (a, b); } -/* { dg-final { scan-assembler "vmov" } } */ +/* +**foo1: +** ... +** vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+] +** vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+] +** ... +*/ +int8x16_t +foo1 () +{ + return vcreateq_s8 (1, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c index 411cec8471e..858a3a4546f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c @@ -1,13 +1,34 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+] +** vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+] +** ... +*/ uint16x8_t foo (uint64_t a, uint64_t b) { return vcreateq_u16 (a, b); } -/* { dg-final { scan-assembler "vmov" } } */ +/* +**foo1: +** ... +** vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+] +** vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+] +** ... +*/ +uint16x8_t +foo1 () +{ + return vcreateq_u16 (1, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c index 8bc8f60640e..5f27cf68845 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c @@ -1,13 +1,34 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+] +** vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+] +** ... +*/ uint32x4_t foo (uint64_t a, uint64_t b) { return vcreateq_u32 (a, b); } -/* { dg-final { scan-assembler "vmov" } } */ +/* +**foo1: +** ... +** vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+] +** vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+] +** ... +*/ +uint32x4_t +foo1 () +{ + return vcreateq_u32 (1, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c index e74641c32f3..78553dec701 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c @@ -1,13 +1,34 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+] +** vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+] +** ... +*/ uint64x2_t foo (uint64_t a, uint64_t b) { return vcreateq_u64 (a, b); } -/* { dg-final { scan-assembler "vmov" } } */ +/* +**foo1: +** ... +** vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+] +** vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+] +** ... +*/ +uint64x2_t +foo1 () +{ + return vcreateq_u64 (1, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c index de79f471d63..4a8ab61f865 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c @@ -1,13 +1,34 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+] +** vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+] +** ... +*/ uint8x16_t foo (uint64_t a, uint64_t b) { return vcreateq_u8 (a, b); } -/* { dg-final { scan-assembler "vmov" } } */ +/* +**foo1: +** ... +** vmov q[0-9+]\[2\], q[0-9+]\[0\], r[0-9+], r[0-9+] +** vmov q[0-9+]\[3\], q[0-9+]\[1\], r[0-9+], r[0-9+] +** ... +*/ +uint8x16_t +foo1 () +{ + return vcreateq_u8 (1, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file From patchwork Thu Nov 17 16:37:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Corallo X-Patchwork-Id: 60753 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3F98C3AA9C63 for ; Thu, 17 Nov 2022 16:39:16 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3F98C3AA9C63 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1668703156; bh=tnhUrkRYTpH5OYL3oJK+ciaJ4OKVC4dFwWbC6b1nYPA=; h=To:CC:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; 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Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VI1EUR03FT025.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB8338 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andrea Corallo via Gcc-patches From: Andrea Corallo Reply-To: Andrea Corallo Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" gcc/ChangeLog: * config/arm/vfp.md (*thumb2_movhi_vfp, *thumb2_movhi_fp16): Fix 'vmsr' spacing and reg capitalization. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c: Update test. * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c: Likewise. --- gcc/config/arm/vfp.md | 8 ++++---- .../arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c | 2 +- .../arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c | 2 +- .../arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index d0f423cc3c5..932e4b7447e 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -105,9 +105,9 @@ (define_insn "*thumb2_movhi_vfp" case 8: return "vmov%?.f32\t%0, %1\t%@ int"; case 9: - return "vmsr%?\t P0, %1\t@ movhi"; + return "vmsr%?\tp0, %1\t@ movhi"; case 10: - return "vmrs%?\t %0, P0\t@ movhi"; + return "vmrs%?\t%0, p0\t@ movhi"; default: gcc_unreachable (); } @@ -209,9 +209,9 @@ (define_insn "*thumb2_movhi_fp16" case 8: return "vmov%?.f32\t%0, %1\t%@ int"; case 9: - return "vmsr%?\t P0, %1\t%@ movhi"; + return "vmsr%?\tp0, %1\t%@ movhi"; case 10: - return "vmrs%?\t%0, P0\t%@ movhi"; + return "vmrs%?\t%0, p0\t%@ movhi"; default: gcc_unreachable (); } diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c index f3219e2e825..1e57ca40739 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_f32.c @@ -11,7 +11,7 @@ foo (uint32x4_t * addr, mve_pred16_t p) } /* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ -/* { dg-final { scan-assembler "vmsr\t P0, r\[0-9\]+.*" } } */ +/* { dg-final { scan-assembler "vmsr\tp0, r\[0-9\]+.*" } } */ /* { dg-final { scan-assembler "vpst" } } */ /* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ /* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c index 4d093d243fe..f8d77fdfd5b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_s32.c @@ -11,7 +11,7 @@ foo (uint32x4_t * addr, mve_pred16_t p) } /* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ -/* { dg-final { scan-assembler "vmsr\t P0, r\[0-9\]+.*" } } */ +/* { dg-final { scan-assembler "vmsr\tp0, r\[0-9\]+.*" } } */ /* { dg-final { scan-assembler "vpst" } } */ /* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ /* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c index e796522a49c..8a0e109c70c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_wb_z_u32.c @@ -11,7 +11,7 @@ foo (uint32x4_t * addr, mve_pred16_t p) } /* { dg-final { scan-assembler "vldrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ -/* { dg-final { scan-assembler "vmsr\t P0, r\[0-9\]+.*" } } */ +/* { dg-final { scan-assembler "vmsr\tp0, r\[0-9\]+.*" } } */ /* { dg-final { scan-assembler "vpst" } } */ /* { dg-final { scan-assembler "vldrwt.u32\tq\[0-9\]+, \\\[q\[0-9\]+, #\[0-9\]+\\\]!" } } */ /* { dg-final { scan-assembler "vstrw.32\tq\[0-9\]+, \\\[r\[0-9\]+\\\]" } } */ From patchwork Thu Nov 17 16:37:37 2022 Content-Type: text/plain; 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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT052.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM7PR08MB5479 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andrea Corallo via Gcc-patches From: Andrea Corallo Reply-To: Andrea Corallo Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" gcc/ChangeLog: * config/arm/mve.md (mve_vddupq_u_insn): Fix 'vddup.u' spacing. (mve_vddupq_m_wb_u_insn): Likewise. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c: Improve test. * gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c : Likewise. * gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c : Likewise. * gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c : Likewise. * gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c : Likewise. * gcc.target/arm/mve/intrinsics/vddupq_n_u16.c : Likewise. * gcc.target/arm/mve/intrinsics/vddupq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vddupq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c : Likewise. * gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c : Likewise. * gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c : Likewise. * gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c : Likewise. * gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c : Likewise. * gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c : Likewise. --- gcc/config/arm/mve.md | 4 +- .../arm/mve/intrinsics/vddupq_m_n_u16.c | 42 +++++++++++++-- .../arm/mve/intrinsics/vddupq_m_n_u32.c | 46 +++++++++++++--- .../arm/mve/intrinsics/vddupq_m_n_u8.c | 46 +++++++++++++--- .../arm/mve/intrinsics/vddupq_m_wb_u16.c | 42 +++++++++++++-- .../arm/mve/intrinsics/vddupq_m_wb_u32.c | 46 +++++++++++++--- .../arm/mve/intrinsics/vddupq_m_wb_u8.c | 46 +++++++++++++--- .../arm/mve/intrinsics/vddupq_n_u16.c | 32 ++++++++++-- .../arm/mve/intrinsics/vddupq_n_u32.c | 28 +++++++++- .../arm/mve/intrinsics/vddupq_n_u8.c | 28 +++++++++- .../arm/mve/intrinsics/vddupq_wb_u16.c | 32 ++++++++++-- .../arm/mve/intrinsics/vddupq_wb_u32.c | 28 +++++++++- .../arm/mve/intrinsics/vddupq_wb_u8.c | 28 +++++++++- .../arm/mve/intrinsics/vddupq_x_n_u16.c | 42 +++++++++++++-- .../arm/mve/intrinsics/vddupq_x_n_u32.c | 46 +++++++++++++--- .../arm/mve/intrinsics/vddupq_x_n_u8.c | 46 +++++++++++++--- .../arm/mve/intrinsics/vddupq_x_wb_u16.c | 52 +++++++++++++++---- .../arm/mve/intrinsics/vddupq_x_wb_u32.c | 52 +++++++++++++++---- .../arm/mve/intrinsics/vddupq_x_wb_u8.c | 52 +++++++++++++++---- 19 files changed, 642 insertions(+), 96 deletions(-) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 62186f124da..1215f845388 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -9043,7 +9043,7 @@ (define_insn "mve_vddupq_u_insn" (minus:SI (match_dup 2) (match_operand:SI 4 "immediate_operand" "i")))] "TARGET_HAVE_MVE" - "vddup.u%# %q0, %1, %3") + "vddup.u%#\t%q0, %1, %3") ;; ;; [vddupq_m_n_u]) @@ -9079,7 +9079,7 @@ (define_insn "mve_vddupq_m_wb_u_insn" (minus:SI (match_dup 3) (match_operand:SI 6 "immediate_operand" "i")))] "TARGET_HAVE_MVE" - "vpst\;\tvddupt.u%#\t%q0, %2, %4" + "vpst\;vddupt.u%#\t%q0, %2, %4" [(set_attr "length""8")]) ;; diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c index 7332711f6a7..7c8b0152763 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint16x8_t inactive, uint32_t a, mve_pred16_t p) { return vddupq_m_n_u16 (inactive, a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vddupt.u16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint16x8_t inactive, uint32_t a, mve_pred16_t p) { return vddupq_m (inactive, a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vddupt.u16" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint16x8_t +foo2 (uint16x8_t inactive, mve_pred16_t p) +{ + return vddupq_m (inactive, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c index 54ad91f2803..810a1a7e21b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32x4_t inactive, uint32_t a, mve_pred16_t p) { - return vddupq_m_n_u32 (inactive, a, 4, p); + return vddupq_m_n_u32 (inactive, a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vddupt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32x4_t inactive, uint32_t a, mve_pred16_t p) { - return vddupq_m (inactive, a, 4, p); + return vddupq_m (inactive, a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vddupt.u32" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint32x4_t +foo2 (uint32x4_t inactive, mve_pred16_t p) +{ + return vddupq_m (inactive, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c index 3746b5db6e5..6642b9f4b88 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint8x16_t inactive, uint32_t a, mve_pred16_t p) { - return vddupq_m_n_u8 (inactive, a, 4, p); + return vddupq_m_n_u8 (inactive, a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vddupt.u8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint8x16_t inactive, uint32_t a, mve_pred16_t p) { - return vddupq_m (inactive, a, 4, p); + return vddupq_m (inactive, a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vddupt.u8" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint8x16_t +foo2 (uint8x16_t inactive, mve_pred16_t p) +{ + return vddupq_m (inactive, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c index 8b5d9e86469..cc6a19516d9 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint16x8_t inactive, uint32_t *a, mve_pred16_t p) { return vddupq_m_wb_u16 (inactive, a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vddupt.u16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint16x8_t inactive, uint32_t *a, mve_pred16_t p) { return vddupq_m (inactive, a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vddupt.u16" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint16x8_t +foo2 (uint16x8_t inactive, mve_pred16_t p) +{ + return vddupq_m (inactive, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c index 7a8c363ac70..cd6c6f86eea 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32x4_t inactive, uint32_t *a, mve_pred16_t p) { - return vddupq_m_wb_u32 (inactive, a, 4, p); + return vddupq_m_wb_u32 (inactive, a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vddupt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32x4_t inactive, uint32_t *a, mve_pred16_t p) { - return vddupq_m (inactive, a, 4, p); + return vddupq_m (inactive, a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vddupt.u32" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint32x4_t +foo2 (uint32x4_t inactive, mve_pred16_t p) +{ + return vddupq_m (inactive, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c index 45784a5c9cd..fe186e743da 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint8x16_t inactive, uint32_t *a, mve_pred16_t p) { - return vddupq_m_wb_u8 (inactive, a, 4, p); + return vddupq_m_wb_u8 (inactive, a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vddupt.u8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint8x16_t inactive, uint32_t *a, mve_pred16_t p) { - return vddupq_m (inactive, a, 4, p); + return vddupq_m (inactive, a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vddupt.u8" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint8x16_t +foo2 (uint8x16_t inactive, mve_pred16_t p) +{ + return vddupq_m (inactive, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u16.c index 4684e2af553..2dba2d74b61 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u16.c @@ -1,21 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vddup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint32_t a) { - return vddupq_n_u16 (a, 4); + return vddupq_n_u16 (a, 1); } -/* { dg-final { scan-assembler "vddup.u16" } } */ +/* +**foo1: +** ... +** vddup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint32_t a) { - return vddupq_u16 (a, 4); + return vddupq_u16 (a, 1); } -/* { dg-final { scan-assembler "vddup.u16" } } */ +/* +**foo2: +** ... +** vddup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint16x8_t +foo2 () +{ + return vddupq_u16 (1, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u32.c index aeaa83eb6bc..6b5cf6c75b0 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u32.c @@ -1,21 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vddup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32_t a) { return vddupq_n_u32 (a, 1); } -/* { dg-final { scan-assembler "vddup.u32" } } */ +/* +**foo1: +** ... +** vddup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32_t a) { return vddupq_u32 (a, 1); } -/* { dg-final { scan-assembler "vddup.u32" } } */ +/* +**foo2: +** ... +** vddup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint32x4_t +foo2 () +{ + return vddupq_u32 (1, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u8.c index 255a9f80b6b..174e422f4ef 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u8.c @@ -1,21 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vddup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint32_t a) { return vddupq_n_u8 (a, 1); } -/* { dg-final { scan-assembler "vddup.u8" } } */ +/* +**foo1: +** ... +** vddup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint32_t a) { return vddupq_u8 (a, 1); } -/* { dg-final { scan-assembler "vddup.u8" } } */ +/* +**foo2: +** ... +** vddup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint8x16_t +foo2 () +{ + return vddupq_u8 (1, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c index 40fc6cf2197..6a471a7f72f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c @@ -1,21 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vddup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint32_t *a) { - return vddupq_wb_u16 (a, 4); + return vddupq_wb_u16 (a, 1); } -/* { dg-final { scan-assembler "vddup.u16" } } */ +/* +**foo1: +** ... +** vddup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint32_t *a) { - return vddupq_u16 (a, 4); + return vddupq_u16 (a, 1); } -/* { dg-final { scan-assembler "vddup.u16" } } */ +/* +**foo2: +** ... +** vddup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint16x8_t +foo2 () +{ + return vddupq_u16 (1, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c index 09b5b1f2f80..debf420d3e8 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c @@ -1,21 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vddup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32_t *a) { return vddupq_wb_u32 (a, 1); } -/* { dg-final { scan-assembler "vddup.u32" } } */ +/* +**foo1: +** ... +** vddup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32_t *a) { return vddupq_u32 (a, 1); } -/* { dg-final { scan-assembler "vddup.u32" } } */ +/* +**foo2: +** ... +** vddup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint32x4_t +foo2 () +{ + return vddupq_u32 (1, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c index 00dfa906748..8e6ef8adccd 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c @@ -1,21 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vddup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint32_t *a) { return vddupq_wb_u8 (a, 1); } -/* { dg-final { scan-assembler "vddup.u8" } } */ +/* +**foo1: +** ... +** vddup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint32_t *a) { return vddupq_u8 (a, 1); } -/* { dg-final { scan-assembler "vddup.u8" } } */ +/* +**foo2: +** ... +** vddup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint8x16_t +foo2 () +{ + return vddupq_u8 (1, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c index 5b0fc0b6340..1aafaf87b82 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint32_t a, mve_pred16_t p) { return vddupq_x_n_u16 (a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vddupt.u16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint32_t a, mve_pred16_t p) { return vddupq_x_u16 (a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vddupt.u16" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint16x8_t +foo2 (mve_pred16_t p) +{ + return vddupq_x_u16 (1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c index 66def991b65..2e3e268dbee 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32_t a, mve_pred16_t p) { - return vddupq_x_n_u32 (a, 4, p); + return vddupq_x_n_u32 (a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vddupt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32_t a, mve_pred16_t p) { - return vddupq_x_u32 (a, 4, p); + return vddupq_x_u32 (a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vddupt.u32" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint32x4_t +foo2 (mve_pred16_t p) +{ + return vddupq_x_u32 (1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c index 8ac322ed52d..bdf563a8074 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint32_t a, mve_pred16_t p) { - return vddupq_x_n_u8 (a, 4, p); + return vddupq_x_n_u8 (a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vddupt.u8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint32_t a, mve_pred16_t p) { - return vddupq_x_u8 (a, 4, p); + return vddupq_x_u8 (a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vddupt.u8" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint8x16_t +foo2 (mve_pred16_t p) +{ + return vddupq_x_u8 (1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c index 030048f840a..713d8b731c8 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c @@ -1,25 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" -uint32_t *a; - +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t -foo (mve_pred16_t p) +foo (uint32_t *a, mve_pred16_t p) { - return vddupq_x_wb_u16 (a, 2, p); + return vddupq_x_wb_u16 (a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vddupt.u16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint16x8_t +foo1 (uint32_t *a, mve_pred16_t p) +{ + return vddupq_x_u16 (a, 1, p); +} + +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t -foo1 (mve_pred16_t p) +foo2 (mve_pred16_t p) { - return vddupq_x_u16 (a, 2, p); + return vddupq_x_u16 (1, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vddupt.u16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c index 95bf28e4052..9f484b3b8fb 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c @@ -1,25 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" -uint32_t *a; - +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t -foo (mve_pred16_t p) +foo (uint32_t *a, mve_pred16_t p) { - return vddupq_x_wb_u32 (a, 8, p); + return vddupq_x_wb_u32 (a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vddupt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint32x4_t +foo1 (uint32_t *a, mve_pred16_t p) +{ + return vddupq_x_u32 (a, 1, p); +} + +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t -foo1 (mve_pred16_t p) +foo2 (mve_pred16_t p) { - return vddupq_x_u32 (a, 8, p); + return vddupq_x_u32 (1, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vddupt.u32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c index 2fe81dded55..aa83bfed125 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c @@ -1,25 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" -uint32_t *a; - +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t -foo (mve_pred16_t p) +foo (uint32_t *a, mve_pred16_t p) { - return vddupq_x_wb_u8 (a, 8, p); + return vddupq_x_wb_u8 (a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vddupt.u8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint8x16_t +foo1 (uint32_t *a, mve_pred16_t p) +{ + return vddupq_x_u8 (a, 1, p); +} + +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vddupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t -foo1 (mve_pred16_t p) +foo2 (mve_pred16_t p) { - return vddupq_x_u8 (a, 8, p); + return vddupq_x_u8 (1, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vddupt.u8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file From patchwork Thu Nov 17 16:37:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Corallo X-Patchwork-Id: 60755 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id AE90A3AA980A for ; Thu, 17 Nov 2022 16:39:33 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org AE90A3AA980A DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1668703173; bh=PJ80kCTQW88ozTLEkMSxIjwzoYxUAoD316wdWW2UXiQ=; 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VI1EUR03FT045.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR08MB10088 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andrea Corallo via Gcc-patches From: Andrea Corallo Reply-To: Andrea Corallo Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" gcc/ChangeLog: * config/arm/mve.md (mve_vdwdupq_m_wb_u_insn): Fix spacing. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c : Improve test. * gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c : Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c : Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c : Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c : Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c : Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c : Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c : Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c : Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c : Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c : Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c : Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c : Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c : Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c : Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c : Likewise. * gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c : Likewise. --- gcc/config/arm/mve.md | 2 +- .../arm/mve/intrinsics/vdwdupq_m_n_u16.c | 44 ++++++++++++++-- .../arm/mve/intrinsics/vdwdupq_m_n_u32.c | 46 ++++++++++++++--- .../arm/mve/intrinsics/vdwdupq_m_n_u8.c | 46 ++++++++++++++--- .../arm/mve/intrinsics/vdwdupq_m_wb_u16.c | 50 ++++++++++++++++--- .../arm/mve/intrinsics/vdwdupq_m_wb_u32.c | 48 +++++++++++++++--- .../arm/mve/intrinsics/vdwdupq_m_wb_u8.c | 50 ++++++++++++++++--- .../arm/mve/intrinsics/vdwdupq_n_u16.c | 32 ++++++++++-- .../arm/mve/intrinsics/vdwdupq_n_u32.c | 32 ++++++++++-- .../arm/mve/intrinsics/vdwdupq_n_u8.c | 32 ++++++++++-- .../arm/mve/intrinsics/vdwdupq_wb_u16.c | 32 ++++++++++-- .../arm/mve/intrinsics/vdwdupq_wb_u32.c | 32 ++++++++++-- .../arm/mve/intrinsics/vdwdupq_wb_u8.c | 32 ++++++++++-- .../arm/mve/intrinsics/vdwdupq_x_n_u16.c | 42 ++++++++++++++-- .../arm/mve/intrinsics/vdwdupq_x_n_u32.c | 46 ++++++++++++++--- .../arm/mve/intrinsics/vdwdupq_x_n_u8.c | 46 ++++++++++++++--- .../arm/mve/intrinsics/vdwdupq_x_wb_u16.c | 50 ++++++++++++++++--- .../arm/mve/intrinsics/vdwdupq_x_wb_u32.c | 46 ++++++++++++++--- .../arm/mve/intrinsics/vdwdupq_x_wb_u8.c | 50 ++++++++++++++++--- 19 files changed, 655 insertions(+), 103 deletions(-) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 1215f845388..58ffe03c499 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -9195,7 +9195,7 @@ (define_insn "mve_vdwdupq_m_wb_u_insn" VDWDUPQ_M)) ] "TARGET_HAVE_MVE" - "vpst\;\tvdwdupt.u%#\t%q2, %3, %R4, %5" + "vpst\;vdwdupt.u%#\t%q2, %3, %R4, %5" [(set_attr "type" "mve_move") (set_attr "length""8")]) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c index 5303fd7d361..8f53f5ef0cb 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint16x8_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) { - return vdwdupq_m (inactive, a, b, 1, p); + return vdwdupq_m_n_u16 (inactive, a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint16x8_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) { return vdwdupq_m (inactive, a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u16" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint16x8_t +foo2 (uint16x8_t inactive, mve_pred16_t p) +{ + return vdwdupq_m (inactive, 1, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c index 9f22bd7f852..30e971fb733 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32x4_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) { - return vdwdupq_m (inactive, a, b, 4, p); + return vdwdupq_m_n_u32 (inactive, a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32x4_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) { - return vdwdupq_m (inactive, a, b, 4, p); + return vdwdupq_m (inactive, a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u32" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint32x4_t +foo2 (uint32x4_t inactive, mve_pred16_t p) +{ + return vdwdupq_m (inactive, 1, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c index 0591e731958..0abc19a2318 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint8x16_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) { - return vdwdupq_m (inactive, a, b, 4, p); + return vdwdupq_m_n_u8 (inactive, a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint8x16_t inactive, uint32_t a, uint32_t b, mve_pred16_t p) { - return vdwdupq_m (inactive, a, b, 4, p); + return vdwdupq_m (inactive, a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u8" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint8x16_t +foo2 (uint8x16_t inactive, mve_pred16_t p) +{ + return vdwdupq_m (inactive, 1, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c index e4e7b47e082..b3e6affbf8f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t -foo (uint16x8_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p) +foo (uint16x8_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p) { - return vdwdupq_m (inactive, a, b, 8, p); + return vdwdupq_m_wb_u16 (inactive, a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t -foo1 (uint16x8_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p) +foo1 (uint16x8_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p) { - return vdwdupq_m (inactive, a, b, 8, p); + return vdwdupq_m (inactive, a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u16" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint16x8_t +foo2 (uint16x8_t inactive, mve_pred16_t p) +{ + return vdwdupq_m (inactive, 1, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c index 42917dc9886..60c52b0d850 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t -foo (uint32x4_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p) +foo (uint32x4_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p) { - return vdwdupq_m (inactive, a, b, 1, p); + return vdwdupq_m_wb_u32 (inactive, a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t -foo1 (uint32x4_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p) +foo1 (uint32x4_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p) { return vdwdupq_m (inactive, a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u32" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint32x4_t +foo2 (uint32x4_t inactive, mve_pred16_t p) +{ + return vdwdupq_m (inactive, 1, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c index 32c3153ffb3..459321a7984 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t -foo (uint8x16_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p) +foo (uint8x16_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p) { - return vdwdupq_m (inactive, a, b, 2, p); + return vdwdupq_m_wb_u8 (inactive, a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t -foo1 (uint8x16_t inactive, uint32_t * a, uint32_t b, mve_pred16_t p) +foo1 (uint8x16_t inactive, uint32_t *a, uint32_t b, mve_pred16_t p) { - return vdwdupq_m (inactive, a, b, 2, p); + return vdwdupq_m (inactive, a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u8" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint8x16_t +foo2 (uint8x16_t inactive, mve_pred16_t p) +{ + return vdwdupq_m (inactive, 1, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c index 725a6e4bc0e..9f76dbf35eb 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c @@ -1,21 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vdwdup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint32_t a, uint32_t b) { - return vdwdupq_n_u16 (a, b, 2); + return vdwdupq_n_u16 (a, b, 1); } -/* { dg-final { scan-assembler "vdwdup.u16" } } */ +/* +**foo1: +** ... +** vdwdup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint32_t a, uint32_t b) { - return vdwdupq_u16 (a, b, 2); + return vdwdupq_u16 (a, b, 1); } -/* { dg-final { scan-assembler "vdwdup.u16" } } */ +/* +**foo2: +** ... +** vdwdup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint16x8_t +foo2 () +{ + return vdwdupq_u16 (1, 1, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c index 6ceaadb984d..962f766b496 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c @@ -1,21 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vdwdup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32_t a, uint32_t b) { - return vdwdupq_n_u32 (a, b, 8); + return vdwdupq_n_u32 (a, b, 1); } -/* { dg-final { scan-assembler "vdwdup.u32" } } */ +/* +**foo1: +** ... +** vdwdup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32_t a, uint32_t b) { - return vdwdupq_u32 (a, b, 8); + return vdwdupq_u32 (a, b, 1); } -/* { dg-final { scan-assembler "vdwdup.u32" } } */ +/* +**foo2: +** ... +** vdwdup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint32x4_t +foo2 () +{ + return vdwdupq_u32 (1, 1, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c index a1712e418be..c73b1b69661 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c @@ -1,21 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vdwdup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint32_t a, uint32_t b) { - return vdwdupq_n_u8 (a, b, 4); + return vdwdupq_n_u8 (a, b, 1); } -/* { dg-final { scan-assembler "vdwdup.u8" } } */ +/* +**foo1: +** ... +** vdwdup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint32_t a, uint32_t b) { - return vdwdupq_u8 (a, b, 4); + return vdwdupq_u8 (a, b, 1); } -/* { dg-final { scan-assembler "vdwdup.u8" } } */ +/* +**foo2: +** ... +** vdwdup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint8x16_t +foo2 () +{ + return vdwdupq_u8 (1, 1, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c index 0164ea9502c..3b1968d78aa 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c @@ -1,21 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vdwdup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint32_t *a, uint32_t b) { - return vdwdupq_wb_u16 (a, b, 2); + return vdwdupq_wb_u16 (a, b, 1); } -/* { dg-final { scan-assembler "vdwdup.u16" } } */ +/* +**foo1: +** ... +** vdwdup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint32_t *a, uint32_t b) { - return vdwdupq_u16 (a, b, 2); + return vdwdupq_u16 (a, b, 1); } -/* { dg-final { scan-assembler "vdwdup.u16" } } */ +/* +**foo2: +** ... +** vdwdup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint16x8_t +foo2 () +{ + return vdwdupq_u16 (1, 1, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c index 7681371b016..8554f62ee6b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c @@ -1,21 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vdwdup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32_t *a, uint32_t b) { - return vdwdupq_wb_u32 (a, b, 8); + return vdwdupq_wb_u32 (a, b, 1); } -/* { dg-final { scan-assembler "vdwdup.u32" } } */ +/* +**foo1: +** ... +** vdwdup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32_t *a, uint32_t b) { - return vdwdupq_u32 (a, b, 8); + return vdwdupq_u32 (a, b, 1); } -/* { dg-final { scan-assembler "vdwdup.u32" } } */ +/* +**foo2: +** ... +** vdwdup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint32x4_t +foo2 () +{ + return vdwdupq_u32 (1, 1, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c index 6f60bb09b24..eb91a80daf5 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c @@ -1,21 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vdwdup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint32_t *a, uint32_t b) { - return vdwdupq_wb_u8 (a, b, 4); + return vdwdupq_wb_u8 (a, b, 1); } -/* { dg-final { scan-assembler "vdwdup.u8" } } */ +/* +**foo1: +** ... +** vdwdup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint32_t *a, uint32_t b) { - return vdwdupq_u8 (a, b, 4); + return vdwdupq_u8 (a, b, 1); } -/* { dg-final { scan-assembler "vdwdup.u8" } } */ +/* +**foo2: +** ... +** vdwdup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint8x16_t +foo2 () +{ + return vdwdupq_u8 (1, 1, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c index ce975267531..9c0fd1e253c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint32_t a, uint32_t b, mve_pred16_t p) { return vdwdupq_x_n_u16 (a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint32_t a, uint32_t b, mve_pred16_t p) { return vdwdupq_x_u16 (a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u16" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint16x8_t +foo2 (mve_pred16_t p) +{ + return vdwdupq_x_u16 (1, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c index 9ed75d292d8..3107e2fdbbe 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32_t a, uint32_t b, mve_pred16_t p) { - return vdwdupq_x_n_u32 (a, b, 4, p); + return vdwdupq_x_n_u32 (a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32_t a, uint32_t b, mve_pred16_t p) { - return vdwdupq_x_u32 (a, b, 4, p); + return vdwdupq_x_u32 (a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u32" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint32x4_t +foo2 (mve_pred16_t p) +{ + return vdwdupq_x_u32 (1, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c index 3705094c4df..03d01e0dd43 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint32_t a, uint32_t b, mve_pred16_t p) { - return vdwdupq_x_n_u8 (a, b, 4, p); + return vdwdupq_x_n_u8 (a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint32_t a, uint32_t b, mve_pred16_t p) { - return vdwdupq_x_u8 (a, b, 4, p); + return vdwdupq_x_u8 (a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u8" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint8x16_t +foo2 (mve_pred16_t p) +{ + return vdwdupq_x_u8 (1, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c index caf744d7255..f7dca660c03 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t -foo (uint32_t * a, uint32_t b, mve_pred16_t p) +foo (uint32_t *a, uint32_t b, mve_pred16_t p) { - return vdwdupq_x_wb_u16 (a, b, 8, p); + return vdwdupq_x_wb_u16 (a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t -foo1 (uint32_t * a, uint32_t b, mve_pred16_t p) +foo1 (uint32_t *a, uint32_t b, mve_pred16_t p) { - return vdwdupq_x_u16 (a, b, 8, p); + return vdwdupq_x_u16 (a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u16" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint16x8_t +foo2 (mve_pred16_t p) +{ + return vdwdupq_x_u16 (1, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c index 8c8be86bce6..032ae94e8c3 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t -foo (uint32_t * a, uint32_t b, mve_pred16_t p) +foo (uint32_t *a, uint32_t b, mve_pred16_t p) { return vdwdupq_x_wb_u32 (a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t -foo1 (uint32_t * a, uint32_t b, mve_pred16_t p) +foo1 (uint32_t *a, uint32_t b, mve_pred16_t p) { return vdwdupq_x_u32 (a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u32" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint32x4_t +foo2 (mve_pred16_t p) +{ + return vdwdupq_x_u32 (1, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c index 1c6ef4ed33f..5d238a7a865 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t -foo (uint32_t * a, uint32_t b, mve_pred16_t p) +foo (uint32_t *a, uint32_t b, mve_pred16_t p) { - return vdwdupq_x_wb_u8 (a, b, 2, p); + return vdwdupq_x_wb_u8 (a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t -foo1 (uint32_t * a, uint32_t b, mve_pred16_t p) +foo1 (uint32_t *a, uint32_t b, mve_pred16_t p) { - return vdwdupq_x_u8 (a, b, 2, p); + return vdwdupq_x_u8 (a, b, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdwdupt.u8" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdwdupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint8x16_t +foo2 (mve_pred16_t p) +{ + return vdwdupq_x_u8 (1, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file From patchwork Thu Nov 17 16:37:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Corallo X-Patchwork-Id: 60757 Return-Path: X-Original-To: patchwork@sourceware.org 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DBAEUR03FT012.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR08MB9689 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andrea Corallo via Gcc-patches From: Andrea Corallo Reply-To: Andrea Corallo Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c: Improve tests. * gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c: Likewise. --- .../arm/mve/intrinsics/vidupq_m_n_u16.c | 46 +++++++++++++--- .../arm/mve/intrinsics/vidupq_m_n_u32.c | 42 +++++++++++++-- .../arm/mve/intrinsics/vidupq_m_n_u8.c | 42 +++++++++++++-- .../arm/mve/intrinsics/vidupq_m_wb_u16.c | 46 +++++++++++++--- .../arm/mve/intrinsics/vidupq_m_wb_u32.c | 42 +++++++++++++-- .../arm/mve/intrinsics/vidupq_m_wb_u8.c | 42 +++++++++++++-- .../arm/mve/intrinsics/vidupq_n_u16.c | 32 ++++++++++-- .../arm/mve/intrinsics/vidupq_n_u32.c | 28 +++++++++- .../arm/mve/intrinsics/vidupq_n_u8.c | 28 +++++++++- .../arm/mve/intrinsics/vidupq_wb_u16.c | 32 ++++++++++-- .../arm/mve/intrinsics/vidupq_wb_u32.c | 28 +++++++++- .../arm/mve/intrinsics/vidupq_wb_u8.c | 28 +++++++++- .../arm/mve/intrinsics/vidupq_x_n_u16.c | 46 +++++++++++++--- .../arm/mve/intrinsics/vidupq_x_n_u32.c | 42 +++++++++++++-- .../arm/mve/intrinsics/vidupq_x_n_u8.c | 42 +++++++++++++-- .../arm/mve/intrinsics/vidupq_x_wb_u16.c | 52 +++++++++++++++---- .../arm/mve/intrinsics/vidupq_x_wb_u32.c | 52 +++++++++++++++---- .../arm/mve/intrinsics/vidupq_x_wb_u8.c | 52 +++++++++++++++---- 18 files changed, 634 insertions(+), 88 deletions(-) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c index 822d41197e6..b4ee7af36e3 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint16x8_t inactive, uint32_t a, mve_pred16_t p) { - return vidupq_m_n_u16 (inactive, a, 4, p); + return vidupq_m_n_u16 (inactive, a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vidupt.u16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint16x8_t inactive, uint32_t a, mve_pred16_t p) { - return vidupq_m (inactive, a, 4, p); + return vidupq_m (inactive, a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vidupt.u16" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint16x8_t +foo2 (uint16x8_t inactive, mve_pred16_t p) +{ + return vidupq_m (inactive, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c index c01826e15dc..b13a7a80dcb 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32x4_t inactive, uint32_t a, mve_pred16_t p) { return vidupq_m_n_u32 (inactive, a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vidupt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32x4_t inactive, uint32_t a, mve_pred16_t p) { return vidupq_m (inactive, a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vidupt.u32" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint32x4_t +foo2 (uint32x4_t inactive, mve_pred16_t p) +{ + return vidupq_m (inactive, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c index e269665813c..b731002724a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint8x16_t inactive, uint32_t a, mve_pred16_t p) { return vidupq_m_n_u8 (inactive, a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vidupt.u8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint8x16_t inactive, uint32_t a, mve_pred16_t p) { return vidupq_m (inactive, a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vidupt.u8" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint8x16_t +foo2 (uint8x16_t inactive, mve_pred16_t p) +{ + return vidupq_m (inactive, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c index 8d21bc7db80..0e2ad6a2b55 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint16x8_t inactive, uint32_t *a, mve_pred16_t p) { - return vidupq_m_wb_u16 (inactive, a, 4, p); + return vidupq_m_wb_u16 (inactive, a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vidupt.u16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint16x8_t inactive, uint32_t *a, mve_pred16_t p) { - return vidupq_m (inactive, a, 4, p); + return vidupq_m (inactive, a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vidupt.u16" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint16x8_t +foo2 (uint16x8_t inactive, mve_pred16_t p) +{ + return vidupq_m (inactive, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c index e7bc06cd826..786a05eee35 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32x4_t inactive, uint32_t *a, mve_pred16_t p) { return vidupq_m_wb_u32 (inactive, a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vidupt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32x4_t inactive, uint32_t *a, mve_pred16_t p) { return vidupq_m (inactive, a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vidupt.u32" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint32x4_t +foo2 (uint32x4_t inactive, mve_pred16_t p) +{ + return vidupq_m (inactive, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c index a8a2f9a1c49..3fcc3ba0d67 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint8x16_t inactive, uint32_t *a, mve_pred16_t p) { return vidupq_m_wb_u8 (inactive, a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vidupt.u8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint8x16_t inactive, uint32_t *a, mve_pred16_t p) { return vidupq_m (inactive, a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vidupt.u8" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint8x16_t +foo2 (uint8x16_t inactive, mve_pred16_t p) +{ + return vidupq_m (inactive, 1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u16.c index c59ca1ebf74..a6ffdc05ce5 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u16.c @@ -1,21 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vidup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint32_t a) { - return vidupq_n_u16 (a, 4); + return vidupq_n_u16 (a, 1); } -/* { dg-final { scan-assembler "vidup.u16" } } */ +/* +**foo1: +** ... +** vidup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint32_t a) { - return vidupq_u16 (a, 4); + return vidupq_u16 (a, 1); } -/* { dg-final { scan-assembler "vidup.u16" } } */ +/* +**foo2: +** ... +** vidup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint16x8_t +foo2 () +{ + return vidupq_u16 (1, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u32.c index 7e835e0868c..8cd43e38255 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u32.c @@ -1,21 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vidup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32_t a) { return vidupq_n_u32 (a, 1); } -/* { dg-final { scan-assembler "vidup.u32" } } */ +/* +**foo1: +** ... +** vidup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32_t a) { return vidupq_u32 (a, 1); } -/* { dg-final { scan-assembler "vidup.u32" } } */ +/* +**foo2: +** ... +** vidup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint32x4_t +foo2 () +{ + return vidupq_u32 (1, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u8.c index 06d1a1a1480..4005eabb45d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u8.c @@ -1,21 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vidup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint32_t a) { return vidupq_n_u8 (a, 1); } -/* { dg-final { scan-assembler "vidup.u8" } } */ +/* +**foo1: +** ... +** vidup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint32_t a) { return vidupq_u8 (a, 1); } -/* { dg-final { scan-assembler "vidup.u8" } } */ +/* +**foo2: +** ... +** vidup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint8x16_t +foo2 () +{ + return vidupq_u8 (1, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c index 1cb0ded198f..3ad89c0536c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c @@ -1,21 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vidup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint32_t *a) { - return vidupq_wb_u16 (a, 4); + return vidupq_wb_u16 (a, 1); } -/* { dg-final { scan-assembler "vidup.u16" } } */ +/* +**foo1: +** ... +** vidup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint32_t *a) { - return vidupq_u16 (a, 4); + return vidupq_u16 (a, 1); } -/* { dg-final { scan-assembler "vidup.u16" } } */ +/* +**foo2: +** ... +** vidup.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint16x8_t +foo2 () +{ + return vidupq_u16 (1, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c index e5d9c5327fb..45eb1b09a5b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c @@ -1,21 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vidup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32_t *a) { return vidupq_wb_u32 (a, 1); } -/* { dg-final { scan-assembler "vidup.u32" } } */ +/* +**foo1: +** ... +** vidup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32_t *a) { return vidupq_u32 (a, 1); } -/* { dg-final { scan-assembler "vidup.u32" } } */ +/* +**foo2: +** ... +** vidup.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint32x4_t +foo2 () +{ + return vidupq_u32 (1, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c index 57e1bb46776..beb0aae67a9 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c @@ -1,21 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vidup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint32_t *a) { return vidupq_wb_u8 (a, 1); } -/* { dg-final { scan-assembler "vidup.u8" } } */ +/* +**foo1: +** ... +** vidup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint32_t *a) { return vidupq_u8 (a, 1); } -/* { dg-final { scan-assembler "vidup.u8" } } */ +/* +**foo2: +** ... +** vidup.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint8x16_t +foo2 () +{ + return vidupq_u8 (1, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c index bdf8ec2b047..74cd4310213 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint32_t a, mve_pred16_t p) { - return vidupq_x_n_u16 (a, 4, p); + return vidupq_x_n_u16 (a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vidupt.u16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint32_t a, mve_pred16_t p) { - return vidupq_x_u16 (a, 4, p); + return vidupq_x_u16 (a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vidupt.u16" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint16x8_t +foo2 (mve_pred16_t p) +{ + return vidupq_x_u16 (1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c index 8be549cb446..3111b1a54e6 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32_t a, mve_pred16_t p) { return vidupq_x_n_u32 (a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vidupt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32_t a, mve_pred16_t p) { return vidupq_x_u32 (a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vidupt.u32" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint32x4_t +foo2 (mve_pred16_t p) +{ + return vidupq_x_u32 (1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c index 1e1975017de..5bedb4f9e79 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c @@ -1,23 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint32_t a, mve_pred16_t p) { return vidupq_x_n_u8 (a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vidupt.u8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint32_t a, mve_pred16_t p) { return vidupq_x_u8 (a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vidupt.u8" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint8x16_t +foo2 (mve_pred16_t p) +{ + return vidupq_x_u8 (1, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c index 31197a76cfa..caf334fa32f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c @@ -1,25 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" -uint32_t *a; - +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t -foo (mve_pred16_t p) +foo (uint32_t *a, mve_pred16_t p) { - return vidupq_x_wb_u16 (a, 8, p); + return vidupq_x_wb_u16 (a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vidupt.u16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint16x8_t +foo1 (uint32_t *a, mve_pred16_t p) +{ + return vidupq_x_u16 (a, 1, p); +} + +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u16 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint16x8_t -foo1 (mve_pred16_t p) +foo2 (mve_pred16_t p) { - return vidupq_x_u16 (a, 8, p); + return vidupq_x_u16 (1, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vidupt.u16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c index cef56f133e8..11895e303cf 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c @@ -1,25 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" -uint32_t *a; - +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t -foo (mve_pred16_t p) +foo (uint32_t *a, mve_pred16_t p) { - return vidupq_x_wb_u32 (a, 2, p); + return vidupq_x_wb_u32 (a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vidupt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint32x4_t +foo1 (uint32_t *a, mve_pred16_t p) +{ + return vidupq_x_u32 (a, 1, p); +} + +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u32 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint32x4_t -foo1 (mve_pred16_t p) +foo2 (mve_pred16_t p) { - return vidupq_x_u32 (a, 2, p); + return vidupq_x_u32 (1, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vidupt.u32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c index 0403ba1174c..b951d4cfe94 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c @@ -1,25 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" -uint32_t * a; - +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t -foo (mve_pred16_t p) +foo (uint32_t *a, mve_pred16_t p) { - return vidupq_x_wb_u8 (a, 2, p); + return vidupq_x_wb_u8 (a, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vidupt.u8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ +uint8x16_t +foo1 (uint32_t *a, mve_pred16_t p) +{ + return vidupq_x_u8 (a, 1, p); +} + +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vidupt.u8 q[0-9]+, (?:ip|fp|r[0-9]+), #[0-9]+(?: @.*|) +** ... +*/ uint8x16_t -foo1 (mve_pred16_t p) +foo2 (mve_pred16_t p) { - return vidupq_x_u8 (a, 2, p); + return vidupq_x_u8 (1, 1, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vidupt.u8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file From patchwork Thu Nov 17 16:37:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Corallo X-Patchwork-Id: 60758 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B192D3AA940D for ; Thu, 17 Nov 2022 16:40:39 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org B192D3AA940D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1668703239; bh=keRL8pWjhNP5BgAVQUNO4AAaCXzbvx9POGnPq6gnKYg=; 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VI1EUR03FT021.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB8386 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andrea Corallo via Gcc-patches From: Andrea Corallo Reply-To: Andrea Corallo Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" gcc/ChangeLog: * config/arm/mve.md (mve_vdupq_n_f) (mve_vdupq_n_, mve_vdupq_m_n_) (mve_vdupq_m_n_f): Fix spacing. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c: Improve test. * gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c: Likewise. --- gcc/config/arm/mve.md | 8 ++-- .../arm/mve/intrinsics/vdupq_m_n_f16.c | 41 +++++++++++++++++-- .../arm/mve/intrinsics/vdupq_m_n_f32.c | 41 +++++++++++++++++-- .../arm/mve/intrinsics/vdupq_m_n_s16.c | 25 +++++++++-- .../arm/mve/intrinsics/vdupq_m_n_s32.c | 25 +++++++++-- .../arm/mve/intrinsics/vdupq_m_n_s8.c | 25 +++++++++-- .../arm/mve/intrinsics/vdupq_m_n_u16.c | 41 +++++++++++++++++-- .../arm/mve/intrinsics/vdupq_m_n_u32.c | 41 +++++++++++++++++-- .../arm/mve/intrinsics/vdupq_m_n_u8.c | 41 +++++++++++++++++-- .../arm/mve/intrinsics/vdupq_n_f16.c | 21 +++++++++- .../arm/mve/intrinsics/vdupq_n_f32.c | 21 +++++++++- .../arm/mve/intrinsics/vdupq_n_s16.c | 13 ++++-- .../arm/mve/intrinsics/vdupq_n_s32.c | 13 ++++-- .../arm/mve/intrinsics/vdupq_n_s8.c | 9 +++- .../arm/mve/intrinsics/vdupq_n_u16.c | 23 ++++++++++- .../arm/mve/intrinsics/vdupq_n_u32.c | 23 ++++++++++- .../arm/mve/intrinsics/vdupq_n_u8.c | 23 ++++++++++- .../arm/mve/intrinsics/vdupq_x_n_f16.c | 30 +++++++++++++- .../arm/mve/intrinsics/vdupq_x_n_f32.c | 30 +++++++++++++- .../arm/mve/intrinsics/vdupq_x_n_s16.c | 14 ++++++- .../arm/mve/intrinsics/vdupq_x_n_s32.c | 14 ++++++- .../arm/mve/intrinsics/vdupq_x_n_s8.c | 14 ++++++- .../arm/mve/intrinsics/vdupq_x_n_u16.c | 30 +++++++++++++- .../arm/mve/intrinsics/vdupq_x_n_u32.c | 30 +++++++++++++- .../arm/mve/intrinsics/vdupq_x_n_u8.c | 30 +++++++++++++- 25 files changed, 567 insertions(+), 59 deletions(-) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 58ffe03c499..6d5270281ec 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -266,7 +266,7 @@ (define_insn "mve_vdupq_n_f" VDUPQ_N_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vdup.%# %q0, %1" + "vdup.%#\t%q0, %1" [(set_attr "type" "mve_move") ]) @@ -435,7 +435,7 @@ (define_insn "mve_vdupq_n_" VDUPQ_N)) ] "TARGET_HAVE_MVE" - "vdup.%# %q0, %1" + "vdup.%#\t%q0, %1" [(set_attr "type" "mve_move") ]) @@ -3046,7 +3046,7 @@ (define_insn "mve_vdupq_m_n_" VDUPQ_M_N)) ] "TARGET_HAVE_MVE" - "vpst\;vdupt.%# %q0, %2" + "vpst\;vdupt.%#\t%q0, %2" [(set_attr "type" "mve_move") (set_attr "length""8")]) @@ -3991,7 +3991,7 @@ (define_insn "mve_vdupq_m_n_f" VDUPQ_M_N_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vpst\;vdupt.%# %q0, %2" + "vpst\;vdupt.%#\t%q0, %2" [(set_attr "type" "mve_move") (set_attr "length""8")]) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c index 0b749be3527..bfa471bcb31 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c @@ -1,22 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t inactive, float16_t a, mve_pred16_t p) { return vdupq_m_n_f16 (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdupt.16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t inactive, float16_t a, mve_pred16_t p) { return vdupq_m (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ +float16x8_t +foo2 (float16x8_t inactive, mve_pred16_t p) +{ + return vdupq_m (inactive, 1.1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c index 9cca5310c7a..e1dd8f58ad0 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c @@ -1,22 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t inactive, float32_t a, mve_pred16_t p) { return vdupq_m_n_f32 (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdupt.32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t inactive, float32_t a, mve_pred16_t p) { return vdupq_m (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ +float32x4_t +foo2 (float32x4_t inactive, mve_pred16_t p) +{ + return vdupq_m (inactive, 1.1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c index b521f13e94f..52304ace03a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ int16x8_t foo (int16x8_t inactive, int16_t a, mve_pred16_t p) { return vdupq_m_n_s16 (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdupt.16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ int16x8_t foo1 (int16x8_t inactive, int16_t a, mve_pred16_t p) { return vdupq_m (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c index 96aa195dc18..44a80c5d5bc 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ int32x4_t foo (int32x4_t inactive, int32_t a, mve_pred16_t p) { return vdupq_m_n_s32 (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdupt.32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ int32x4_t foo1 (int32x4_t inactive, int32_t a, mve_pred16_t p) { return vdupq_m (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c index f1d222000c1..1630a3b9234 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdupt.8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ int8x16_t foo (int8x16_t inactive, int8_t a, mve_pred16_t p) { return vdupq_m_n_s8 (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdupt.8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdupt.8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ int8x16_t foo1 (int8x16_t inactive, int8_t a, mve_pred16_t p) { return vdupq_m (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c index 39d0c9f502d..d3df8b69248 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c @@ -1,22 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ uint16x8_t foo (uint16x8_t inactive, uint16_t a, mve_pred16_t p) { return vdupq_m_n_u16 (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdupt.16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint16x8_t inactive, uint16_t a, mve_pred16_t p) { return vdupq_m (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ +uint16x8_t +foo2 (uint16x8_t inactive, mve_pred16_t p) +{ + return vdupq_m (inactive, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c index fc107172e16..e6bb0cc2c38 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c @@ -1,22 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ uint32x4_t foo (uint32x4_t inactive, uint32_t a, mve_pred16_t p) { return vdupq_m_n_u32 (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdupt.32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32x4_t inactive, uint32_t a, mve_pred16_t p) { return vdupq_m (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ +uint32x4_t +foo2 (uint32x4_t inactive, mve_pred16_t p) +{ + return vdupq_m (inactive, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c index 9fd3bc443cb..ad6f6d04ae3 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c @@ -1,22 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdupt.8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ uint8x16_t foo (uint8x16_t inactive, uint8_t a, mve_pred16_t p) { return vdupq_m_n_u8 (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdupt.8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdupt.8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint8x16_t inactive, uint8_t a, mve_pred16_t p) { return vdupq_m (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdupt.8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ +uint8x16_t +foo2 (uint8x16_t inactive, mve_pred16_t p) +{ + return vdupq_m (inactive, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c index 62bfc194533..fc5a7933653 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c @@ -1,13 +1,32 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vdup.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ float16x8_t foo (float16_t a) { return vdupq_n_f16 (a); } -/* { dg-final { scan-assembler "vdup.16" } } */ +/* +**foo1: +** ... +** vdup.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ +float16x8_t +foo1 () +{ + return vdupq_n_f16 (1.1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c index f5ad2286d8d..a6be82e5927 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c @@ -1,13 +1,32 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vdup.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ float32x4_t foo (float32_t a) { return vdupq_n_f32 (a); } -/* { dg-final { scan-assembler "vdup.32" } } */ +/* +**foo1: +** ... +** vdup.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ +float32x4_t +foo1 () +{ + return vdupq_n_f32 (1.1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c index 1378522a18e..f842b96c3b1 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c @@ -1,13 +1,20 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vdup.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ int16x8_t foo (int16_t a) { return vdupq_n_s16 (a); } -/* { dg-final { scan-assembler "vdup.16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c index 43affe856c0..05cbff8fdae 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c @@ -1,13 +1,20 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vdup.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ int32x4_t foo (int32_t a) { return vdupq_n_s32 (a); } -/* { dg-final { scan-assembler "vdup.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s8.c index 3f934dc5d59..1d141161604 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s8.c @@ -1,13 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vdup.8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ int8x16_t foo (int8_t a) { return vdupq_n_s8 (a); } -/* { dg-final { scan-assembler "vdup.8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u16.c index 93268643fec..4839d427e65 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u16.c @@ -1,13 +1,32 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vdup.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ uint16x8_t foo (uint16_t a) { - return vdupq_n_u16 (a); + return vdupq_n_u16 (a); } -/* { dg-final { scan-assembler "vdup.16" } } */ +/* +**foo1: +** ... +** vdup.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ +uint16x8_t +foo1 () +{ + return vdupq_n_u16 (1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u32.c index 276e9ddc67f..f0069eb7280 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u32.c @@ -1,13 +1,32 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vdup.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ uint32x4_t foo (uint32_t a) { - return vdupq_n_u32 (a); + return vdupq_n_u32 (a); } -/* { dg-final { scan-assembler "vdup.32" } } */ +/* +**foo1: +** ... +** vdup.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ +uint32x4_t +foo1 () +{ + return vdupq_n_u32 (1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u8.c index d0361c15047..fe26687ae45 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_u8.c @@ -1,13 +1,32 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vdup.8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ uint8x16_t foo (uint8_t a) { - return vdupq_n_u8 (a); + return vdupq_n_u8 (a); } -/* { dg-final { scan-assembler "vdup.8" } } */ +/* +**foo1: +** ... +** vdup.8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ +uint8x16_t +foo1 () +{ + return vdupq_n_u8 (1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c index c91ee62791c..11ebb47f94f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c @@ -1,14 +1,40 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ float16x8_t foo (float16_t a, mve_pred16_t p) { return vdupq_x_n_f16 (a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdupt.16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ +float16x8_t +foo1 (mve_pred16_t p) +{ + return vdupq_x_n_f16 (1.1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c index c2b39051f5b..4e79bd54f71 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c @@ -1,14 +1,40 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ float32x4_t foo (float32_t a, mve_pred16_t p) { return vdupq_x_n_f32 (a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdupt.32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ +float32x4_t +foo1 (mve_pred16_t p) +{ + return vdupq_x_n_f32 (1.1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c index cc8a5bfeca1..90288777df7 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c @@ -1,14 +1,24 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ int16x8_t foo (int16_t a, mve_pred16_t p) { return vdupq_x_n_s16 (a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdupt.16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c index b3ed3eb68e8..c4c906e0682 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c @@ -1,14 +1,24 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ int32x4_t foo (int32_t a, mve_pred16_t p) { return vdupq_x_n_s32 (a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdupt.32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c index 3be865dcc84..6234730827e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c @@ -1,14 +1,24 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdupt.8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ int8x16_t foo (int8_t a, mve_pred16_t p) { return vdupq_x_n_s8 (a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdupt.8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c index d01338aeb91..821fcddcab1 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c @@ -1,14 +1,40 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ uint16x8_t foo (uint16_t a, mve_pred16_t p) { return vdupq_x_n_u16 (a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdupt.16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdupt.16 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ +uint16x8_t +foo1 (mve_pred16_t p) +{ + return vdupq_x_n_u16 (1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c index 8fa7d4552bc..20125df6226 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c @@ -1,14 +1,40 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ uint32x4_t foo (uint32_t a, mve_pred16_t p) { return vdupq_x_n_u32 (a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdupt.32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdupt.32 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ +uint32x4_t +foo1 (mve_pred16_t p) +{ + return vdupq_x_n_u32 (1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c index 96ad899c9c2..defaaeebfcf 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c @@ -1,14 +1,40 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdupt.8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ uint8x16_t foo (uint8_t a, mve_pred16_t p) { return vdupq_x_n_u8 (a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vdupt.8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vdupt.8 q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +*/ +uint8x16_t +foo1 (mve_pred16_t p) +{ + return vdupq_x_n_u8 (1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file From patchwork Thu Nov 17 16:37:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Corallo X-Patchwork-Id: 60779 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: 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VI1EUR03FT018.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB8063 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andrea Corallo via Gcc-patches From: Andrea Corallo Reply-To: Andrea Corallo Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" gcc/ChangeLog: * config/arm/mve.md (@mve_vcmpq_): Fix spacing. * config/arm/arm_mve.h (__arm_vcmpgtq_m, __arm_vcmpleq_m) (__arm_vcmpltq_m, __arm_vcmpneq_m): Add missing defines. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c: Improve test. * gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmphiq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmphiq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmphiq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpleq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpltq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vcmpneq_u8.c: Likewise. --- gcc/config/arm/arm_mve.h | 47 +++++++++++++++++++ gcc/config/arm/mve.md | 2 +- .../arm/mve/intrinsics/vcmpcsq_m_n_u16.c | 47 +++++++++++++++++-- .../arm/mve/intrinsics/vcmpcsq_m_n_u32.c | 47 +++++++++++++++++-- .../arm/mve/intrinsics/vcmpcsq_m_n_u8.c | 47 +++++++++++++++++-- .../arm/mve/intrinsics/vcmpcsq_m_u16.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpcsq_m_u32.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpcsq_m_u8.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpcsq_n_u16.c | 34 +++++++++++++- .../arm/mve/intrinsics/vcmpcsq_n_u32.c | 34 +++++++++++++- .../arm/mve/intrinsics/vcmpcsq_n_u8.c | 34 +++++++++++++- .../arm/mve/intrinsics/vcmpcsq_u16.c | 20 +++++++- .../arm/mve/intrinsics/vcmpcsq_u32.c | 20 +++++++- .../arm/mve/intrinsics/vcmpcsq_u8.c | 20 +++++++- .../arm/mve/intrinsics/vcmpeqq_f16.c | 20 +++++++- .../arm/mve/intrinsics/vcmpeqq_f32.c | 20 +++++++- .../arm/mve/intrinsics/vcmpeqq_m_f16.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpeqq_m_f32.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpeqq_m_n_f16.c | 47 +++++++++++++++++-- .../arm/mve/intrinsics/vcmpeqq_m_n_f32.c | 47 +++++++++++++++++-- .../arm/mve/intrinsics/vcmpeqq_m_n_s16.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpeqq_m_n_s32.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpeqq_m_n_s8.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpeqq_m_n_u16.c | 47 +++++++++++++++++-- .../arm/mve/intrinsics/vcmpeqq_m_n_u32.c | 47 +++++++++++++++++-- .../arm/mve/intrinsics/vcmpeqq_m_n_u8.c | 47 +++++++++++++++++-- .../arm/mve/intrinsics/vcmpeqq_m_s16.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpeqq_m_s32.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpeqq_m_s8.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpeqq_m_u16.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpeqq_m_u32.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpeqq_m_u8.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpeqq_n_f16.c | 34 +++++++++++++- .../arm/mve/intrinsics/vcmpeqq_n_f32.c | 34 +++++++++++++- .../arm/mve/intrinsics/vcmpeqq_n_s16.c | 20 +++++++- .../arm/mve/intrinsics/vcmpeqq_n_s32.c | 20 +++++++- .../arm/mve/intrinsics/vcmpeqq_n_s8.c | 20 +++++++- .../arm/mve/intrinsics/vcmpeqq_n_u16.c | 34 +++++++++++++- .../arm/mve/intrinsics/vcmpeqq_n_u32.c | 34 +++++++++++++- .../arm/mve/intrinsics/vcmpeqq_n_u8.c | 34 +++++++++++++- .../arm/mve/intrinsics/vcmpeqq_s16.c | 20 +++++++- .../arm/mve/intrinsics/vcmpeqq_s32.c | 20 +++++++- .../arm/mve/intrinsics/vcmpeqq_s8.c | 20 +++++++- .../arm/mve/intrinsics/vcmpeqq_u16.c | 20 +++++++- .../arm/mve/intrinsics/vcmpeqq_u32.c | 20 +++++++- .../arm/mve/intrinsics/vcmpeqq_u8.c | 20 +++++++- .../arm/mve/intrinsics/vcmpgeq_f16.c | 20 +++++++- .../arm/mve/intrinsics/vcmpgeq_f32.c | 20 +++++++- .../arm/mve/intrinsics/vcmpgeq_m_f16.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpgeq_m_f32.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpgeq_m_n_f16.c | 47 +++++++++++++++++-- .../arm/mve/intrinsics/vcmpgeq_m_n_f32.c | 47 +++++++++++++++++-- .../arm/mve/intrinsics/vcmpgeq_m_n_s16.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpgeq_m_n_s32.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpgeq_m_n_s8.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpgeq_m_s16.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpgeq_m_s32.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpgeq_m_s8.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpgeq_n_f16.c | 34 +++++++++++++- .../arm/mve/intrinsics/vcmpgeq_n_f32.c | 34 +++++++++++++- .../arm/mve/intrinsics/vcmpgeq_n_s16.c | 20 +++++++- .../arm/mve/intrinsics/vcmpgeq_n_s32.c | 20 +++++++- .../arm/mve/intrinsics/vcmpgeq_n_s8.c | 20 +++++++- .../arm/mve/intrinsics/vcmpgeq_s16.c | 20 +++++++- .../arm/mve/intrinsics/vcmpgeq_s32.c | 20 +++++++- .../arm/mve/intrinsics/vcmpgeq_s8.c | 20 +++++++- .../arm/mve/intrinsics/vcmpgtq_f16.c | 20 +++++++- .../arm/mve/intrinsics/vcmpgtq_f32.c | 20 +++++++- .../arm/mve/intrinsics/vcmpgtq_m_f16.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpgtq_m_f32.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpgtq_m_n_f16.c | 47 +++++++++++++++++-- .../arm/mve/intrinsics/vcmpgtq_m_n_f32.c | 47 +++++++++++++++++-- .../arm/mve/intrinsics/vcmpgtq_m_n_s16.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpgtq_m_n_s32.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpgtq_m_n_s8.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpgtq_m_s16.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpgtq_m_s32.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpgtq_m_s8.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpgtq_n_f16.c | 34 +++++++++++++- .../arm/mve/intrinsics/vcmpgtq_n_f32.c | 34 +++++++++++++- .../arm/mve/intrinsics/vcmpgtq_n_s16.c | 20 +++++++- .../arm/mve/intrinsics/vcmpgtq_n_s32.c | 20 +++++++- .../arm/mve/intrinsics/vcmpgtq_n_s8.c | 20 +++++++- .../arm/mve/intrinsics/vcmpgtq_s16.c | 20 +++++++- .../arm/mve/intrinsics/vcmpgtq_s32.c | 20 +++++++- .../arm/mve/intrinsics/vcmpgtq_s8.c | 20 +++++++- .../arm/mve/intrinsics/vcmphiq_m_n_u16.c | 47 +++++++++++++++++-- .../arm/mve/intrinsics/vcmphiq_m_n_u32.c | 47 +++++++++++++++++-- .../arm/mve/intrinsics/vcmphiq_m_n_u8.c | 47 +++++++++++++++++-- .../arm/mve/intrinsics/vcmphiq_m_u16.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmphiq_m_u32.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmphiq_m_u8.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmphiq_n_u16.c | 34 +++++++++++++- .../arm/mve/intrinsics/vcmphiq_n_u32.c | 34 +++++++++++++- .../arm/mve/intrinsics/vcmphiq_n_u8.c | 34 +++++++++++++- .../arm/mve/intrinsics/vcmphiq_u16.c | 20 +++++++- .../arm/mve/intrinsics/vcmphiq_u32.c | 20 +++++++- .../arm/mve/intrinsics/vcmphiq_u8.c | 20 +++++++- .../arm/mve/intrinsics/vcmpleq_f16.c | 20 +++++++- .../arm/mve/intrinsics/vcmpleq_f32.c | 20 +++++++- .../arm/mve/intrinsics/vcmpleq_m_f16.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpleq_m_f32.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpleq_m_n_f16.c | 47 +++++++++++++++++-- .../arm/mve/intrinsics/vcmpleq_m_n_f32.c | 47 +++++++++++++++++-- .../arm/mve/intrinsics/vcmpleq_m_n_s16.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpleq_m_n_s32.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpleq_m_n_s8.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpleq_m_s16.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpleq_m_s32.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpleq_m_s8.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpleq_n_f16.c | 34 +++++++++++++- .../arm/mve/intrinsics/vcmpleq_n_f32.c | 34 +++++++++++++- .../arm/mve/intrinsics/vcmpleq_n_s16.c | 20 +++++++- .../arm/mve/intrinsics/vcmpleq_n_s32.c | 20 +++++++- .../arm/mve/intrinsics/vcmpleq_n_s8.c | 20 +++++++- .../arm/mve/intrinsics/vcmpleq_s16.c | 20 +++++++- .../arm/mve/intrinsics/vcmpleq_s32.c | 20 +++++++- .../arm/mve/intrinsics/vcmpleq_s8.c | 20 +++++++- .../arm/mve/intrinsics/vcmpltq_f16.c | 20 +++++++- .../arm/mve/intrinsics/vcmpltq_f32.c | 20 +++++++- .../arm/mve/intrinsics/vcmpltq_m_f16.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpltq_m_f32.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpltq_m_n_f16.c | 47 +++++++++++++++++-- .../arm/mve/intrinsics/vcmpltq_m_n_f32.c | 47 +++++++++++++++++-- .../arm/mve/intrinsics/vcmpltq_m_n_s16.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpltq_m_n_s32.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpltq_m_n_s8.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpltq_m_s16.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpltq_m_s32.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpltq_m_s8.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpltq_n_f16.c | 34 +++++++++++++- .../arm/mve/intrinsics/vcmpltq_n_f32.c | 34 +++++++++++++- .../arm/mve/intrinsics/vcmpltq_n_s16.c | 20 +++++++- .../arm/mve/intrinsics/vcmpltq_n_s32.c | 20 +++++++- .../arm/mve/intrinsics/vcmpltq_n_s8.c | 20 +++++++- .../arm/mve/intrinsics/vcmpltq_s16.c | 20 +++++++- .../arm/mve/intrinsics/vcmpltq_s32.c | 20 +++++++- .../arm/mve/intrinsics/vcmpltq_s8.c | 20 +++++++- .../arm/mve/intrinsics/vcmpneq_f16.c | 20 +++++++- .../arm/mve/intrinsics/vcmpneq_f32.c | 20 +++++++- .../arm/mve/intrinsics/vcmpneq_m_f16.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpneq_m_f32.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpneq_m_n_f16.c | 47 +++++++++++++++++-- .../arm/mve/intrinsics/vcmpneq_m_n_f32.c | 47 +++++++++++++++++-- .../arm/mve/intrinsics/vcmpneq_m_n_s16.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpneq_m_n_s32.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpneq_m_n_s8.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpneq_m_n_u16.c | 47 +++++++++++++++++-- .../arm/mve/intrinsics/vcmpneq_m_n_u32.c | 47 +++++++++++++++++-- .../arm/mve/intrinsics/vcmpneq_m_n_u8.c | 47 +++++++++++++++++-- .../arm/mve/intrinsics/vcmpneq_m_s16.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpneq_m_s32.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpneq_m_s8.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpneq_m_u16.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpneq_m_u32.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpneq_m_u8.c | 29 ++++++++++-- .../arm/mve/intrinsics/vcmpneq_n_f16.c | 34 +++++++++++++- .../arm/mve/intrinsics/vcmpneq_n_f32.c | 34 +++++++++++++- .../arm/mve/intrinsics/vcmpneq_n_s16.c | 20 +++++++- .../arm/mve/intrinsics/vcmpneq_n_s32.c | 20 +++++++- .../arm/mve/intrinsics/vcmpneq_n_s8.c | 20 +++++++- .../arm/mve/intrinsics/vcmpneq_n_u16.c | 34 +++++++++++++- .../arm/mve/intrinsics/vcmpneq_n_u32.c | 34 +++++++++++++- .../arm/mve/intrinsics/vcmpneq_n_u8.c | 34 +++++++++++++- .../arm/mve/intrinsics/vcmpneq_s16.c | 20 +++++++- .../arm/mve/intrinsics/vcmpneq_s32.c | 20 +++++++- .../arm/mve/intrinsics/vcmpneq_s8.c | 20 +++++++- .../arm/mve/intrinsics/vcmpneq_u16.c | 20 +++++++- .../arm/mve/intrinsics/vcmpneq_u32.c | 20 +++++++- .../arm/mve/intrinsics/vcmpneq_u8.c | 20 +++++++- 170 files changed, 4512 insertions(+), 421 deletions(-) diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 073e3711623..684f997520f 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -39229,6 +39229,53 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2));}) + +#define __arm_vcmpgtq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2));}) + +#define __arm_vcmpleq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpleq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpleq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2));}) + +#define __arm_vcmpltq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpltq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpltq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2));}) + +#define __arm_vcmpneq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ + __typeof(p1) __p1 = (p1); \ + _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpneq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpneq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpneq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpneq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpneq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpneq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2));}) + #define __arm_vdupq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 6d5270281ec..3330a220aea 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -831,7 +831,7 @@ (define_insn "@mve_vcmpq_" (match_operand:MVE_2 2 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE" - "vcmp.%# , %q1, %q2" + "vcmp.%#\t, %q1, %q2" [(set_attr "type" "mve_move") ]) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c index a1640133012..de9fe5e7d01 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u16.c @@ -1,22 +1,63 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.u16 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint16x8_t a, uint16_t b, mve_pred16_t p) { return vcmpcsq_m_n_u16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.u16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.u16 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p) { return vcmpcsq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.u16 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (uint16x8_t a, mve_pred16_t p) +{ + return vcmpcsq_m (a, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c index d269ec7e3ab..04df1b2dc61 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u32.c @@ -1,22 +1,63 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.u32 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint32x4_t a, uint32_t b, mve_pred16_t p) { return vcmpcsq_m_n_u32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.u32 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p) { return vcmpcsq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.u32 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (uint32x4_t a, mve_pred16_t p) +{ + return vcmpcsq_m (a, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c index 52c16b3e70f..34ebadca248 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c @@ -1,22 +1,63 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.u8 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint8x16_t a, uint8_t b, mve_pred16_t p) { return vcmpcsq_m_n_u8 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.u8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.u8 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p) { return vcmpcsq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.u8 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (uint8x16_t a, mve_pred16_t p) +{ + return vcmpcsq_m (a, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c index e68afa316a9..bc03bf687de 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.u16 cs, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) { return vcmpcsq_m_u16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.u16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.u16 cs, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) { return vcmpcsq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c index 05d1b21b279..8e216d49a02 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.u32 cs, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) { return vcmpcsq_m_u32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.u32 cs, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) { return vcmpcsq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c index 4c8a9d0aa2c..ac4196a2e48 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.u8 cs, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) { return vcmpcsq_m_u8 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.u8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.u8 cs, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) { return vcmpcsq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c index 4124036003e..6038f4c8c65 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c @@ -1,21 +1,51 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.u16 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint16x8_t a, uint16_t b) { return vcmpcsq_n_u16 (a, b); } -/* { dg-final { scan-assembler "vcmp.u16" } } */ +/* +**foo1: +** ... +** vcmp.u16 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint16x8_t a, uint16_t b) { return vcmpcsq (a, b); } -/* { dg-final { scan-assembler "vcmp.u16" } } */ +/* +**foo2: +** ... +** vcmp.u16 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (uint16x8_t a) +{ + return vcmpcsq (a, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c index 463c1ee12b4..9f39aa761c8 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c @@ -1,21 +1,51 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.u32 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint32x4_t a, uint32_t b) { return vcmpcsq_n_u32 (a, b); } -/* { dg-final { scan-assembler "vcmp.u32" } } */ +/* +**foo1: +** ... +** vcmp.u32 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint32x4_t a, uint32_t b) { return vcmpcsq (a, b); } -/* { dg-final { scan-assembler "vcmp.u32" } } */ +/* +**foo2: +** ... +** vcmp.u32 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (uint32x4_t a) +{ + return vcmpcsq (a, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c index 92bc44a4bb6..0ce2cd13a7b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c @@ -1,21 +1,51 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.u8 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint8x16_t a, uint8_t b) { return vcmpcsq_n_u8 (a, b); } -/* { dg-final { scan-assembler "vcmp.u8" } } */ +/* +**foo1: +** ... +** vcmp.u8 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint8x16_t a, uint8_t b) { return vcmpcsq (a, b); } -/* { dg-final { scan-assembler "vcmp.u8" } } */ +/* +**foo2: +** ... +** vcmp.u8 cs, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (uint8x16_t a) +{ + return vcmpcsq (a, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c index 26c7d750cef..5598d06875c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.u16 cs, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint16x8_t a, uint16x8_t b) { return vcmpcsq_u16 (a, b); } -/* { dg-final { scan-assembler "vcmp.u16" } } */ +/* +**foo1: +** ... +** vcmp.u16 cs, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint16x8_t a, uint16x8_t b) { return vcmpcsq (a, b); } -/* { dg-final { scan-assembler "vcmp.u16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c index c91b0e1c2e3..99b232b05dd 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.u32 cs, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint32x4_t a, uint32x4_t b) { return vcmpcsq_u32 (a, b); } -/* { dg-final { scan-assembler "vcmp.u32" } } */ +/* +**foo1: +** ... +** vcmp.u32 cs, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint32x4_t a, uint32x4_t b) { return vcmpcsq (a, b); } -/* { dg-final { scan-assembler "vcmp.u32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c index 51ddab91500..571e57135ab 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.u8 cs, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint8x16_t a, uint8x16_t b) { return vcmpcsq_u8 (a, b); } -/* { dg-final { scan-assembler "vcmp.u8" } } */ +/* +**foo1: +** ... +** vcmp.u8 cs, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint8x16_t a, uint8x16_t b) { return vcmpcsq (a, b); } -/* { dg-final { scan-assembler "vcmp.u8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c index 556351f4984..57b276a1d4c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.f16 eq, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float16x8_t a, float16x8_t b) { return vcmpeqq_f16 (a, b); } -/* { dg-final { scan-assembler "vcmp.f16" } } */ +/* +**foo1: +** ... +** vcmp.f16 eq, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float16x8_t a, float16x8_t b) { return vcmpeqq (a, b); } -/* { dg-final { scan-assembler "vcmp.f16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c index 65b2f240520..ab1b25e2888 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.f32 eq, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float32x4_t a, float32x4_t b) { return vcmpeqq_f32 (a, b); } -/* { dg-final { scan-assembler "vcmp.f32" } } */ +/* +**foo1: +** ... +** vcmp.f32 eq, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float32x4_t a, float32x4_t b) { return vcmpeqq (a, b); } -/* { dg-final { scan-assembler "vcmp.f32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c index 91b0ffa0afd..c5587884d0e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f16 eq, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmpeqq_m_f16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f16 eq, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmpeqq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c index d66e9c8be34..4e9675fff51 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f32 eq, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmpeqq_m_f32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f32 eq, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmpeqq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c index 46b3f4499d3..a3cae828e79 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f16.c @@ -1,22 +1,63 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float16x8_t a, float16_t b, mve_pred16_t p) { return vcmpeqq_m_n_f16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float16x8_t a, float16_t b, mve_pred16_t p) { return vcmpeqq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (float16x8_t a, mve_pred16_t p) +{ + return vcmpeqq_m (a, 1.1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c index 7d672c129db..a7ce9e0c7e3 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_f32.c @@ -1,22 +1,63 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float32x4_t a, float32_t b, mve_pred16_t p) { return vcmpeqq_m_n_f32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float32x4_t a, float32_t b, mve_pred16_t p) { return vcmpeqq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (float32x4_t a, mve_pred16_t p) +{ + return vcmpeqq_m (a, 1.1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c index 912d4ad893d..7ba481e169f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s16.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int16x8_t a, int16_t b, mve_pred16_t p) { return vcmpeqq_m_n_s16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.i16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int16x8_t a, int16_t b, mve_pred16_t p) { return vcmpeqq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c index 947c331622d..13c88eaabb5 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s32.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int32x4_t a, int32_t b, mve_pred16_t p) { return vcmpeqq_m_n_s32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.i32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int32x4_t a, int32_t b, mve_pred16_t p) { return vcmpeqq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c index e215d655ea2..dcf276dee44 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i8 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int8x16_t a, int8_t b, mve_pred16_t p) { return vcmpeqq_m_n_s8 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.i8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i8 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int8x16_t a, int8_t b, mve_pred16_t p) { return vcmpeqq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c index ea4716c450e..d59d5149a30 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u16.c @@ -1,22 +1,63 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint16x8_t a, uint16_t b, mve_pred16_t p) { return vcmpeqq_m_n_u16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.i16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p) { return vcmpeqq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (uint16x8_t a, mve_pred16_t p) +{ + return vcmpeqq_m (a, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c index 489c6ec0cb3..1fbf385d030 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u32.c @@ -1,22 +1,63 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint32x4_t a, uint32_t b, mve_pred16_t p) { return vcmpeqq_m_n_u32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.i32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p) { return vcmpeqq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (uint32x4_t a, mve_pred16_t p) +{ + return vcmpeqq_m (a, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c index e8dfce432d1..92758c98c9a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c @@ -1,22 +1,63 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i8 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint8x16_t a, uint8_t b, mve_pred16_t p) { return vcmpeqq_m_n_u8 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.i8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i8 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p) { return vcmpeqq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i8 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (uint8x16_t a, mve_pred16_t p) +{ + return vcmpeqq_m (a, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c index 7e4c141e5d2..1ea35ed924b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i16 eq, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int16x8_t a, int16x8_t b, mve_pred16_t p) { return vcmpeqq_m_s16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.i16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i16 eq, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) { return vcmpeqq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c index 904cfb6fe37..a9bc9733842 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i32 eq, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int32x4_t a, int32x4_t b, mve_pred16_t p) { return vcmpeqq_m_s32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.i32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i32 eq, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) { return vcmpeqq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c index a7e12164e32..a9fe771a101 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i8 eq, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int8x16_t a, int8x16_t b, mve_pred16_t p) { return vcmpeqq_m_s8 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.i8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i8 eq, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) { return vcmpeqq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c index 283e1fd036e..826901874d7 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i16 eq, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) { return vcmpeqq_m_u16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.i16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i16 eq, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) { return vcmpeqq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c index ad1739bd609..512b7f9c889 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i32 eq, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) { return vcmpeqq_m_u32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.i32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i32 eq, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) { return vcmpeqq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c index 595142e9cda..01b4507ba63 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i8 eq, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) { return vcmpeqq_m_u8 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.i8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i8 eq, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) { return vcmpeqq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c index f97209d2322..cf2812558ff 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c @@ -1,21 +1,51 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.f16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float16x8_t a, float16_t b) { return vcmpeqq_n_f16 (a, b); } -/* { dg-final { scan-assembler "vcmp.f16" } } */ +/* +**foo1: +** ... +** vcmp.f16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float16x8_t a, float16_t b) { return vcmpeqq (a, b); } -/* { dg-final { scan-assembler "vcmp.f16" } } */ +/* +**foo2: +** ... +** vcmp.f16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (float16x8_t a) +{ + return vcmpeqq (a, 1.1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c index c80843288b2..13817174282 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c @@ -1,21 +1,51 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.f32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float32x4_t a, float32_t b) { return vcmpeqq_n_f32 (a, b); } -/* { dg-final { scan-assembler "vcmp.f32" } } */ +/* +**foo1: +** ... +** vcmp.f32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float32x4_t a, float32_t b) { return vcmpeqq (a, b); } -/* { dg-final { scan-assembler "vcmp.f32" } } */ +/* +**foo2: +** ... +** vcmp.f32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (float32x4_t a) +{ + return vcmpeqq (a, 1.1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c index 69f1f531af4..bd29828492e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.i16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int16x8_t a, int16_t b) { return vcmpeqq_n_s16 (a, b); } -/* { dg-final { scan-assembler "vcmp.i16" } } */ +/* +**foo1: +** ... +** vcmp.i16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int16x8_t a, int16_t b) { return vcmpeqq (a, b); } -/* { dg-final { scan-assembler "vcmp.i16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c index 06032dbcc20..2a0d84e9b51 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.i32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int32x4_t a, int32_t b) { return vcmpeqq_n_s32 (a, b); } -/* { dg-final { scan-assembler "vcmp.i32" } } */ +/* +**foo1: +** ... +** vcmp.i32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int32x4_t a, int32_t b) { return vcmpeqq (a, b); } -/* { dg-final { scan-assembler "vcmp.i32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c index 3ebd88be85b..524bbe9f3cb 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.i8 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int8x16_t a, int8_t b) { return vcmpeqq_n_s8 (a, b); } -/* { dg-final { scan-assembler "vcmp.i8" } } */ +/* +**foo1: +** ... +** vcmp.i8 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int8x16_t a, int8_t b) { return vcmpeqq (a, b); } -/* { dg-final { scan-assembler "vcmp.i8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c index 2f6c53a525e..3eeaa49aa97 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c @@ -1,21 +1,51 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.i16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint16x8_t a, uint16_t b) { return vcmpeqq_n_u16 (a, b); } -/* { dg-final { scan-assembler "vcmp.i16" } } */ +/* +**foo1: +** ... +** vcmp.i16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint16x8_t a, uint16_t b) { return vcmpeqq (a, b); } -/* { dg-final { scan-assembler "vcmp.i16" } } */ +/* +**foo2: +** ... +** vcmp.i16 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (uint16x8_t a) +{ + return vcmpeqq (a, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c index 22fb5be97c5..a881bb841af 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c @@ -1,21 +1,51 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.i32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint32x4_t a, uint32_t b) { return vcmpeqq_n_u32 (a, b); } -/* { dg-final { scan-assembler "vcmp.i32" } } */ +/* +**foo1: +** ... +** vcmp.i32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint32x4_t a, uint32_t b) { return vcmpeqq (a, b); } -/* { dg-final { scan-assembler "vcmp.i32" } } */ +/* +**foo2: +** ... +** vcmp.i32 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (uint32x4_t a) +{ + return vcmpeqq (a, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c index 79eaeed6950..429b2e35eb7 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c @@ -1,21 +1,51 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.i8 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint8x16_t a, uint8_t b) { return vcmpeqq_n_u8 (a, b); } -/* { dg-final { scan-assembler "vcmp.i8" } } */ +/* +**foo1: +** ... +** vcmp.i8 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint8x16_t a, uint8_t b) { return vcmpeqq (a, b); } -/* { dg-final { scan-assembler "vcmp.i8" } } */ +/* +**foo2: +** ... +** vcmp.i8 eq, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (uint8x16_t a) +{ + return vcmpeqq (a, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c index 7951ead8a31..92a87c08773 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.i16 eq, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int16x8_t a, int16x8_t b) { return vcmpeqq_s16 (a, b); } -/* { dg-final { scan-assembler "vcmp.i16" } } */ +/* +**foo1: +** ... +** vcmp.i16 eq, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int16x8_t a, int16x8_t b) { return vcmpeqq (a, b); } -/* { dg-final { scan-assembler "vcmp.i16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c index 659ccb4ac14..d3b87d59bfa 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.i32 eq, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int32x4_t a, int32x4_t b) { return vcmpeqq_s32 (a, b); } -/* { dg-final { scan-assembler "vcmp.i32" } } */ +/* +**foo1: +** ... +** vcmp.i32 eq, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int32x4_t a, int32x4_t b) { return vcmpeqq (a, b); } -/* { dg-final { scan-assembler "vcmp.i32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c index 9282ec2a97a..2b71bbf75f6 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.i8 eq, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int8x16_t a, int8x16_t b) { return vcmpeqq_s8 (a, b); } -/* { dg-final { scan-assembler "vcmp.i8" } } */ +/* +**foo1: +** ... +** vcmp.i8 eq, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int8x16_t a, int8x16_t b) { return vcmpeqq (a, b); } -/* { dg-final { scan-assembler "vcmp.i8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c index 318b7aa9306..1830b667bb6 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.i16 eq, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint16x8_t a, uint16x8_t b) { return vcmpeqq_u16 (a, b); } -/* { dg-final { scan-assembler "vcmp.i16" } } */ +/* +**foo1: +** ... +** vcmp.i16 eq, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint16x8_t a, uint16x8_t b) { return vcmpeqq (a, b); } -/* { dg-final { scan-assembler "vcmp.i16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c index 88e015f1fa3..2b2a5f920f3 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.i32 eq, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint32x4_t a, uint32x4_t b) { return vcmpeqq_u32 (a, b); } -/* { dg-final { scan-assembler "vcmp.i32" } } */ +/* +**foo1: +** ... +** vcmp.i32 eq, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint32x4_t a, uint32x4_t b) { return vcmpeqq (a, b); } -/* { dg-final { scan-assembler "vcmp.i32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c index 990a96f7b3f..9450c203394 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.i8 eq, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint8x16_t a, uint8x16_t b) { return vcmpeqq_u8 (a, b); } -/* { dg-final { scan-assembler "vcmp.i8" } } */ +/* +**foo1: +** ... +** vcmp.i8 eq, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint8x16_t a, uint8x16_t b) { return vcmpeqq (a, b); } -/* { dg-final { scan-assembler "vcmp.i8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c index eea63a2fe50..fd8bcab4f25 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.f16 ge, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float16x8_t a, float16x8_t b) { return vcmpgeq_f16 (a, b); } -/* { dg-final { scan-assembler "vcmp.f16" } } */ +/* +**foo1: +** ... +** vcmp.f16 ge, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float16x8_t a, float16x8_t b) { return vcmpgeq (a, b); } -/* { dg-final { scan-assembler "vcmp.f16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c index 64243fe3e8c..a2d50b580e7 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.f32 ge, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float32x4_t a, float32x4_t b) { return vcmpgeq_f32 (a, b); } -/* { dg-final { scan-assembler "vcmp.f32" } } */ +/* +**foo1: +** ... +** vcmp.f32 ge, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float32x4_t a, float32x4_t b) { return vcmpgeq (a, b); } -/* { dg-final { scan-assembler "vcmp.f32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c index 3588b0a536f..a631825fadd 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f16 ge, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmpgeq_m_f16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f16 ge, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmpgeq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c index 8ed1d22e919..b94e0738ef0 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f32 ge, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmpgeq_m_f32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f32 ge, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmpgeq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c index d106af8f53b..9f4903d9cfd 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f16.c @@ -1,22 +1,63 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f16 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float16x8_t a, float16_t b, mve_pred16_t p) { return vcmpgeq_m_n_f16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f16 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float16x8_t a, float16_t b, mve_pred16_t p) { return vcmpgeq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f16 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (float16x8_t a, mve_pred16_t p) +{ + return vcmpgeq_m (a, 1.1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c index 1feef8adb7f..679e644f165 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_f32.c @@ -1,22 +1,63 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f32 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float32x4_t a, float32_t b, mve_pred16_t p) { return vcmpgeq_m_n_f32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f32 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float32x4_t a, float32_t b, mve_pred16_t p) { return vcmpgeq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f32 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (float32x4_t a, mve_pred16_t p) +{ + return vcmpgeq_m (a, 1.1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c index c0ad38f6c6f..45e26d0a77b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s16.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s16 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int16x8_t a, int16_t b, mve_pred16_t p) { return vcmpgeq_m_n_s16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.s16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s16 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int16x8_t a, int16_t b, mve_pred16_t p) { return vcmpgeq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c index 8974ce4d11a..3a6cad921f2 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s32.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s32 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int32x4_t a, int32_t b, mve_pred16_t p) { return vcmpgeq_m_n_s32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.s32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s32 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int32x4_t a, int32_t b, mve_pred16_t p) { return vcmpgeq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c index 981aa1b516c..ce1ca30d6ea 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s8 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int8x16_t a, int8_t b, mve_pred16_t p) { return vcmpgeq_m_n_s8 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.s8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s8 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int8x16_t a, int8_t b, mve_pred16_t p) { return vcmpgeq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c index 587432a6af1..51587a38b72 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s16 ge, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int16x8_t a, int16x8_t b, mve_pred16_t p) { return vcmpgeq_m_s16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.s16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s16 ge, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) { return vcmpgeq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c index e460a8dcafc..3ff0aaaa414 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s32 ge, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int32x4_t a, int32x4_t b, mve_pred16_t p) { return vcmpgeq_m_s32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.s32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s32 ge, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) { return vcmpgeq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c index cde28a314b9..df71ee57945 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s8 ge, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int8x16_t a, int8x16_t b, mve_pred16_t p) { return vcmpgeq_m_s8 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.s8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s8 ge, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) { return vcmpgeq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c index 907fa5d50f6..2ca1b9d6684 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c @@ -1,21 +1,51 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.f16 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float16x8_t a, float16_t b) { return vcmpgeq_n_f16 (a, b); } -/* { dg-final { scan-assembler "vcmp.f16" } } */ +/* +**foo1: +** ... +** vcmp.f16 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float16x8_t a, float16_t b) { return vcmpgeq (a, b); } -/* { dg-final { scan-assembler "vcmp.f16" } } */ +/* +**foo2: +** ... +** vcmp.f16 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (float16x8_t a) +{ + return vcmpgeq (a, 1.1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c index e4d1406c049..3af110bd2b2 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c @@ -1,21 +1,51 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.f32 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float32x4_t a, float32_t b) { return vcmpgeq_n_f32 (a, b); } -/* { dg-final { scan-assembler "vcmp.f32" } } */ +/* +**foo1: +** ... +** vcmp.f32 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float32x4_t a, float32_t b) { return vcmpgeq (a, b); } -/* { dg-final { scan-assembler "vcmp.f32" } } */ +/* +**foo2: +** ... +** vcmp.f32 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (float32x4_t a) +{ + return vcmpgeq (a, 1.1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c index f4aad09e783..3c1af8a93ab 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.s16 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int16x8_t a, int16_t b) { return vcmpgeq_n_s16 (a, b); } -/* { dg-final { scan-assembler "vcmp.s16" } } */ +/* +**foo1: +** ... +** vcmp.s16 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int16x8_t a, int16_t b) { return vcmpgeq (a, b); } -/* { dg-final { scan-assembler "vcmp.s16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c index 2baa5204819..8b4e0f426e5 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.s32 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int32x4_t a, int32_t b) { return vcmpgeq_n_s32 (a, b); } -/* { dg-final { scan-assembler "vcmp.s32" } } */ +/* +**foo1: +** ... +** vcmp.s32 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int32x4_t a, int32_t b) { return vcmpgeq (a, b); } -/* { dg-final { scan-assembler "vcmp.s32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c index 1dcffcc3050..c1669bcdd90 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.s8 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int8x16_t a, int8_t b) { return vcmpgeq_n_s8 (a, b); } -/* { dg-final { scan-assembler "vcmp.s8" } } */ +/* +**foo1: +** ... +** vcmp.s8 ge, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int8x16_t a, int8_t b) { return vcmpgeq (a, b); } -/* { dg-final { scan-assembler "vcmp.s8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c index 817ffb2d8ac..593c7410dcb 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.s16 ge, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int16x8_t a, int16x8_t b) { return vcmpgeq_s16 (a, b); } -/* { dg-final { scan-assembler "vcmp.s16" } } */ +/* +**foo1: +** ... +** vcmp.s16 ge, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int16x8_t a, int16x8_t b) { return vcmpgeq (a, b); } -/* { dg-final { scan-assembler "vcmp.s16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c index d608b7fc9cf..9e26ea9938a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.s32 ge, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int32x4_t a, int32x4_t b) { return vcmpgeq_s32 (a, b); } -/* { dg-final { scan-assembler "vcmp.s32" } } */ +/* +**foo1: +** ... +** vcmp.s32 ge, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int32x4_t a, int32x4_t b) { return vcmpgeq (a, b); } -/* { dg-final { scan-assembler "vcmp.s32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c index 506e6cede95..3cb2832e159 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.s8 ge, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int8x16_t a, int8x16_t b) { return vcmpgeq_s8 (a, b); } -/* { dg-final { scan-assembler "vcmp.s8" } } */ +/* +**foo1: +** ... +** vcmp.s8 ge, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int8x16_t a, int8x16_t b) { return vcmpgeq (a, b); } -/* { dg-final { scan-assembler "vcmp.s8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c index e2bfd7ed156..8835fe08dba 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.f16 gt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float16x8_t a, float16x8_t b) { return vcmpgtq_f16 (a, b); } -/* { dg-final { scan-assembler "vcmp.f16" } } */ +/* +**foo1: +** ... +** vcmp.f16 gt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float16x8_t a, float16x8_t b) { return vcmpgtq (a, b); } -/* { dg-final { scan-assembler "vcmp.f16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c index 1b4433f0e76..e1470884708 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.f32 gt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float32x4_t a, float32x4_t b) { return vcmpgtq_f32 (a, b); } -/* { dg-final { scan-assembler "vcmp.f32" } } */ +/* +**foo1: +** ... +** vcmp.f32 gt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float32x4_t a, float32x4_t b) { return vcmpgtq (a, b); } -/* { dg-final { scan-assembler "vcmp.f32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c index def3f90a79d..cb9d5f4036f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f16 gt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmpgtq_m_f16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f16 gt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmpgtq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c index 41a11563f36..b249b831782 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f32 gt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmpgtq_m_f32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f32 gt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmpgtq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c index 80c86f65825..b375983f01e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f16.c @@ -1,22 +1,63 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f16 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float16x8_t a, float16_t b, mve_pred16_t p) { return vcmpgtq_m_n_f16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f16 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float16x8_t a, float16_t b, mve_pred16_t p) { return vcmpgtq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f16 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (float16x8_t a, mve_pred16_t p) +{ + return vcmpgtq_m (a, 1.1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c index 9b7aaadfe71..208a285cb39 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_f32.c @@ -1,22 +1,63 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f32 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float32x4_t a, float32_t b, mve_pred16_t p) { return vcmpgtq_m_n_f32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f32 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float32x4_t a, float32_t b, mve_pred16_t p) { return vcmpgtq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f32 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (float32x4_t a, mve_pred16_t p) +{ + return vcmpgtq_m (a, 1.1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c index c0719d0110c..248e3093d2a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s16.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s16 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int16x8_t a, int16_t b, mve_pred16_t p) { return vcmpgtq_m_n_s16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.s16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s16 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int16x8_t a, int16_t b, mve_pred16_t p) { return vcmpgtq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c index 26df8cea9fc..9843288296e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s32.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s32 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int32x4_t a, int32_t b, mve_pred16_t p) { return vcmpgtq_m_n_s32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.s32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s32 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int32x4_t a, int32_t b, mve_pred16_t p) { return vcmpgtq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c index f20c50d69c1..80f1aa9ead0 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s8 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int8x16_t a, int8_t b, mve_pred16_t p) { return vcmpgtq_m_n_s8 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.s8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s8 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int8x16_t a, int8_t b, mve_pred16_t p) { return vcmpgtq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c index da97abceb2e..9289c00b5af 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s16 gt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int16x8_t a, int16x8_t b, mve_pred16_t p) { return vcmpgtq_m_s16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.s16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s16 gt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) { return vcmpgtq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c index ab7c218c7af..8a3d7606bb7 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s32 gt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int32x4_t a, int32x4_t b, mve_pred16_t p) { return vcmpgtq_m_s32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.s32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s32 gt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) { return vcmpgtq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c index 13520d1067b..2760795eb86 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s8 gt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int8x16_t a, int8x16_t b, mve_pred16_t p) { return vcmpgtq_m_s8 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.s8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s8 gt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) { return vcmpgtq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c index 98e152cd999..9f2a4be319a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c @@ -1,21 +1,51 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.f16 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float16x8_t a, float16_t b) { return vcmpgtq_n_f16 (a, b); } -/* { dg-final { scan-assembler "vcmp.f16" } } */ +/* +**foo1: +** ... +** vcmp.f16 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float16x8_t a, float16_t b) { return vcmpgtq (a, b); } -/* { dg-final { scan-assembler "vcmp.f16" } } */ +/* +**foo2: +** ... +** vcmp.f16 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (float16x8_t a) +{ + return vcmpgtq (a, 1.1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c index 5691e2f9d35..bbf18ebe6e7 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c @@ -1,21 +1,51 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.f32 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float32x4_t a, float32_t b) { return vcmpgtq_n_f32 (a, b); } -/* { dg-final { scan-assembler "vcmp.f32" } } */ +/* +**foo1: +** ... +** vcmp.f32 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float32x4_t a, float32_t b) { return vcmpgtq (a, b); } -/* { dg-final { scan-assembler "vcmp.f32" } } */ +/* +**foo2: +** ... +** vcmp.f32 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (float32x4_t a) +{ + return vcmpgtq (a, 1.1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c index bc3bdbae2da..d833cb6f58e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.s16 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int16x8_t a, int16_t b) { return vcmpgtq_n_s16 (a, b); } -/* { dg-final { scan-assembler "vcmp.s16" } } */ +/* +**foo1: +** ... +** vcmp.s16 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int16x8_t a, int16_t b) { return vcmpgtq (a, b); } -/* { dg-final { scan-assembler "vcmp.s16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c index 409a3f9d808..28cd51b9582 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.s32 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int32x4_t a, int32_t b) { return vcmpgtq_n_s32 (a, b); } -/* { dg-final { scan-assembler "vcmp.s32" } } */ +/* +**foo1: +** ... +** vcmp.s32 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int32x4_t a, int32_t b) { return vcmpgtq (a, b); } -/* { dg-final { scan-assembler "vcmp.s32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c index 2624307be9d..5a953ca55f4 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.s8 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int8x16_t a, int8_t b) { return vcmpgtq_n_s8 (a, b); } -/* { dg-final { scan-assembler "vcmp.s8" } } */ +/* +**foo1: +** ... +** vcmp.s8 gt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int8x16_t a, int8_t b) { return vcmpgtq (a, b); } -/* { dg-final { scan-assembler "vcmp.s8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c index be19e19f09f..b9c9da486f5 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.s16 gt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int16x8_t a, int16x8_t b) { return vcmpgtq_s16 (a, b); } -/* { dg-final { scan-assembler "vcmp.s16" } } */ +/* +**foo1: +** ... +** vcmp.s16 gt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int16x8_t a, int16x8_t b) { return vcmpgtq (a, b); } -/* { dg-final { scan-assembler "vcmp.s16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c index 95f6c703b9d..0f79385358e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.s32 gt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int32x4_t a, int32x4_t b) { return vcmpgtq_s32 (a, b); } -/* { dg-final { scan-assembler "vcmp.s32" } } */ +/* +**foo1: +** ... +** vcmp.s32 gt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int32x4_t a, int32x4_t b) { return vcmpgtq (a, b); } -/* { dg-final { scan-assembler "vcmp.s32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c index 8ba180d8e39..f59dad94a57 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.s8 gt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int8x16_t a, int8x16_t b) { return vcmpgtq_s8 (a, b); } -/* { dg-final { scan-assembler "vcmp.s8" } } */ +/* +**foo1: +** ... +** vcmp.s8 gt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int8x16_t a, int8x16_t b) { return vcmpgtq (a, b); } -/* { dg-final { scan-assembler "vcmp.s8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c index 26e5fe3f900..136a2e44259 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u16.c @@ -1,22 +1,63 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.u16 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint16x8_t a, uint16_t b, mve_pred16_t p) { return vcmphiq_m_n_u16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.u16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.u16 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p) { return vcmphiq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.u16 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (uint16x8_t a, mve_pred16_t p) +{ + return vcmphiq_m (a, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c index 51396b8d0cd..5640b97afaf 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u32.c @@ -1,22 +1,63 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.u32 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint32x4_t a, uint32_t b, mve_pred16_t p) { return vcmphiq_m_n_u32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.u32 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p) { return vcmphiq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.u32 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (uint32x4_t a, mve_pred16_t p) +{ + return vcmphiq_m (a, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c index 475f2e82345..e6474e45487 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c @@ -1,22 +1,63 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.u8 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint8x16_t a, uint8_t b, mve_pred16_t p) { return vcmphiq_m_n_u8 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.u8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.u8 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p) { return vcmphiq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.u8 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (uint8x16_t a, mve_pred16_t p) +{ + return vcmphiq_m (a, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c index 98ba895fde0..38b9b90c803 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.u16 hi, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) { return vcmphiq_m_u16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.u16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.u16 hi, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) { return vcmphiq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c index ee561b02d0c..97c8c1dfe05 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.u32 hi, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) { return vcmphiq_m_u32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.u32 hi, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) { return vcmphiq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c index 0c5b29e2673..e2024ccda25 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.u8 hi, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) { return vcmphiq_m_u8 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.u8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.u8 hi, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) { return vcmphiq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c index d39b755441d..36107fc7b8d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c @@ -1,21 +1,51 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.u16 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint16x8_t a, uint16_t b) { return vcmphiq_n_u16 (a, b); } -/* { dg-final { scan-assembler "vcmp.u16" } } */ +/* +**foo1: +** ... +** vcmp.u16 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint16x8_t a, uint16_t b) { return vcmphiq (a, b); } -/* { dg-final { scan-assembler "vcmp.u16" } } */ +/* +**foo2: +** ... +** vcmp.u16 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (uint16x8_t a) +{ + return vcmphiq (a, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c index dbedea9b078..d34de8f65c7 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c @@ -1,21 +1,51 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.u32 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint32x4_t a, uint32_t b) { return vcmphiq_n_u32 (a, b); } -/* { dg-final { scan-assembler "vcmp.u32" } } */ +/* +**foo1: +** ... +** vcmp.u32 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint32x4_t a, uint32_t b) { return vcmphiq (a, b); } -/* { dg-final { scan-assembler "vcmp.u32" } } */ +/* +**foo2: +** ... +** vcmp.u32 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (uint32x4_t a) +{ + return vcmphiq (a, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c index 967bb206886..93a05b1a857 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c @@ -1,21 +1,51 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.u8 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint8x16_t a, uint8_t b) { return vcmphiq_n_u8 (a, b); } -/* { dg-final { scan-assembler "vcmp.u8" } } */ +/* +**foo1: +** ... +** vcmp.u8 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint8x16_t a, uint8_t b) { return vcmphiq (a, b); } -/* { dg-final { scan-assembler "vcmp.u8" } } */ +/* +**foo2: +** ... +** vcmp.u8 hi, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (uint8x16_t a) +{ + return vcmphiq (a, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u16.c index f9399498a99..40e65dc52f4 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u16.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.u16 hi, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint16x8_t a, uint16x8_t b) { return vcmphiq_u16 (a, b); } -/* { dg-final { scan-assembler "vcmp.u16" } } */ +/* +**foo1: +** ... +** vcmp.u16 hi, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint16x8_t a, uint16x8_t b) { return vcmphiq (a, b); } -/* { dg-final { scan-assembler "vcmp.u16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u32.c index becdef0696a..d87a4185762 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u32.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.u32 hi, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint32x4_t a, uint32x4_t b) { return vcmphiq_u32 (a, b); } -/* { dg-final { scan-assembler "vcmp.u32" } } */ +/* +**foo1: +** ... +** vcmp.u32 hi, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint32x4_t a, uint32x4_t b) { return vcmphiq (a, b); } -/* { dg-final { scan-assembler "vcmp.u32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u8.c index 933cc69507d..80fd2a40b0f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmphiq_u8.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.u8 hi, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint8x16_t a, uint8x16_t b) { return vcmphiq_u8 (a, b); } -/* { dg-final { scan-assembler "vcmp.u8" } } */ +/* +**foo1: +** ... +** vcmp.u8 hi, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint8x16_t a, uint8x16_t b) { return vcmphiq (a, b); } -/* { dg-final { scan-assembler "vcmp.u8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f16.c index c2e69a5de92..209d81096af 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f16.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.f16 le, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float16x8_t a, float16x8_t b) { return vcmpleq_f16 (a, b); } -/* { dg-final { scan-assembler "vcmp.f16" } } */ +/* +**foo1: +** ... +** vcmp.f16 le, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float16x8_t a, float16x8_t b) { return vcmpleq (a, b); } -/* { dg-final { scan-assembler "vcmp.f16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f32.c index 923aee050d3..b92c5f66fd9 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_f32.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.f32 le, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float32x4_t a, float32x4_t b) { return vcmpleq_f32 (a, b); } -/* { dg-final { scan-assembler "vcmp.f32" } } */ +/* +**foo1: +** ... +** vcmp.f32 le, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float32x4_t a, float32x4_t b) { return vcmpleq (a, b); } -/* { dg-final { scan-assembler "vcmp.f32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c index 66a37192985..e6136898ded 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f16 le, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmpleq_m_f16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f16 le, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmpleq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c index e679b338d58..2304e98d253 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f32 le, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmpleq_m_f32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f32 le, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmpleq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c index 42049fd57a4..a61db2817c1 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f16.c @@ -1,22 +1,63 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f16 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float16x8_t a, float16_t b, mve_pred16_t p) { return vcmpleq_m_n_f16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f16 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float16x8_t a, float16_t b, mve_pred16_t p) { return vcmpleq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f16 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (float16x8_t a, mve_pred16_t p) +{ + return vcmpleq_m (a, 1.1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c index c68bd4e5900..7a2cdb4059d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_f32.c @@ -1,22 +1,63 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f32 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float32x4_t a, float32_t b, mve_pred16_t p) { return vcmpleq_m_n_f32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f32 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float32x4_t a, float32_t b, mve_pred16_t p) { return vcmpleq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f32 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (float32x4_t a, mve_pred16_t p) +{ + return vcmpleq_m (a, 1.1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c index 0cdc14455a3..69fcab15b8a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s16.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s16 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int16x8_t a, int16_t b, mve_pred16_t p) { return vcmpleq_m_n_s16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.s16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s16 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int16x8_t a, int16_t b, mve_pred16_t p) { return vcmpleq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c index a955af8fa2b..617ebd6144f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s32.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s32 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int32x4_t a, int32_t b, mve_pred16_t p) { return vcmpleq_m_n_s32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.s32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s32 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int32x4_t a, int32_t b, mve_pred16_t p) { return vcmpleq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c index d9951e4a8cf..b8ee50dd55c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s8 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int8x16_t a, int8_t b, mve_pred16_t p) { return vcmpleq_m_n_s8 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.s8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s8 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int8x16_t a, int8_t b, mve_pred16_t p) { return vcmpleq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c index f16aff86ef0..fcc376d6ec3 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s16 le, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int16x8_t a, int16x8_t b, mve_pred16_t p) { return vcmpleq_m_s16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.s16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s16 le, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) { return vcmpleq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c index 2c4e659e9cf..9983e89d80c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s32 le, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int32x4_t a, int32x4_t b, mve_pred16_t p) { return vcmpleq_m_s32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.s32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s32 le, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) { return vcmpleq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c index 69b88cfb389..504e4feb5d1 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s8 le, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int8x16_t a, int8x16_t b, mve_pred16_t p) { return vcmpleq_m_s8 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.s8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s8 le, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) { return vcmpleq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c index 3fa3c5e0310..cfa6dbc07c7 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c @@ -1,21 +1,51 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.f16 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float16x8_t a, float16_t b) { return vcmpleq_n_f16 (a, b); } -/* { dg-final { scan-assembler "vcmp.f16" } } */ +/* +**foo1: +** ... +** vcmp.f16 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float16x8_t a, float16_t b) { return vcmpleq (a, b); } -/* { dg-final { scan-assembler "vcmp.f16" } } */ +/* +**foo2: +** ... +** vcmp.f16 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (float16x8_t a) +{ + return vcmpleq (a, 1.1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c index 8349de7b68c..c89558f4076 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c @@ -1,21 +1,51 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.f32 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float32x4_t a, float32_t b) { return vcmpleq_n_f32 (a, b); } -/* { dg-final { scan-assembler "vcmp.f32" } } */ +/* +**foo1: +** ... +** vcmp.f32 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float32x4_t a, float32_t b) { return vcmpleq (a, b); } -/* { dg-final { scan-assembler "vcmp.f32" } } */ +/* +**foo2: +** ... +** vcmp.f32 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (float32x4_t a) +{ + return vcmpleq (a, 1.1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c index 5ecae572227..da73fc14b77 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.s16 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int16x8_t a, int16_t b) { return vcmpleq_n_s16 (a, b); } -/* { dg-final { scan-assembler "vcmp.s16" } } */ +/* +**foo1: +** ... +** vcmp.s16 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int16x8_t a, int16_t b) { return vcmpleq (a, b); } -/* { dg-final { scan-assembler "vcmp.s16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c index 02320e7a552..0951a5c13fb 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.s32 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int32x4_t a, int32_t b) { return vcmpleq_n_s32 (a, b); } -/* { dg-final { scan-assembler "vcmp.s32" } } */ +/* +**foo1: +** ... +** vcmp.s32 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int32x4_t a, int32_t b) { return vcmpleq (a, b); } -/* { dg-final { scan-assembler "vcmp.s32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c index a0ac97328b7..e4553354681 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.s8 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int8x16_t a, int8_t b) { return vcmpleq_n_s8 (a, b); } -/* { dg-final { scan-assembler "vcmp.s8" } } */ +/* +**foo1: +** ... +** vcmp.s8 le, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int8x16_t a, int8_t b) { return vcmpleq (a, b); } -/* { dg-final { scan-assembler "vcmp.s8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s16.c index 2fb4acd3d74..68500da9ddf 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s16.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.s16 le, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int16x8_t a, int16x8_t b) { return vcmpleq_s16 (a, b); } -/* { dg-final { scan-assembler "vcmp.s16" } } */ +/* +**foo1: +** ... +** vcmp.s16 le, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int16x8_t a, int16x8_t b) { return vcmpleq (a, b); } -/* { dg-final { scan-assembler "vcmp.s16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s32.c index 2ae998efb7c..1966bcd94d3 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s32.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.s32 le, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int32x4_t a, int32x4_t b) { return vcmpleq_s32 (a, b); } -/* { dg-final { scan-assembler "vcmp.s32" } } */ +/* +**foo1: +** ... +** vcmp.s32 le, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int32x4_t a, int32x4_t b) { return vcmpleq (a, b); } -/* { dg-final { scan-assembler "vcmp.s32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s8.c index da06b019cc1..e9f6e47e5d6 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpleq_s8.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.s8 le, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int8x16_t a, int8x16_t b) { return vcmpleq_s8 (a, b); } -/* { dg-final { scan-assembler "vcmp.s8" } } */ +/* +**foo1: +** ... +** vcmp.s8 le, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int8x16_t a, int8x16_t b) { return vcmpleq (a, b); } -/* { dg-final { scan-assembler "vcmp.s8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f16.c index eab80b2ddd9..b4958816bd8 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f16.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.f16 lt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float16x8_t a, float16x8_t b) { return vcmpltq_f16 (a, b); } -/* { dg-final { scan-assembler "vcmp.f16" } } */ +/* +**foo1: +** ... +** vcmp.f16 lt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float16x8_t a, float16x8_t b) { return vcmpltq (a, b); } -/* { dg-final { scan-assembler "vcmp.f16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f32.c index f17d16482dd..752ab2b3e49 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_f32.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.f32 lt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float32x4_t a, float32x4_t b) { return vcmpltq_f32 (a, b); } -/* { dg-final { scan-assembler "vcmp.f32" } } */ +/* +**foo1: +** ... +** vcmp.f32 lt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float32x4_t a, float32x4_t b) { return vcmpltq (a, b); } -/* { dg-final { scan-assembler "vcmp.f32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c index 93c36f3a613..cbaacbe2b47 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f16 lt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmpltq_m_f16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f16 lt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmpltq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c index a17f0b02a95..96d0e7c7cc6 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f32 lt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmpltq_m_f32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f32 lt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmpltq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c index 45d0f51b4d7..1e5db53198e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f16.c @@ -1,22 +1,63 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f16 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float16x8_t a, float16_t b, mve_pred16_t p) { return vcmpltq_m_n_f16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f16 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float16x8_t a, float16_t b, mve_pred16_t p) { return vcmpltq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f16 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (float16x8_t a, mve_pred16_t p) +{ + return vcmpltq_m (a, 1.1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c index 16e37ccaf8d..77de40ade01 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_f32.c @@ -1,22 +1,63 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f32 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float32x4_t a, float32_t b, mve_pred16_t p) { return vcmpltq_m_n_f32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f32 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float32x4_t a, float32_t b, mve_pred16_t p) { return vcmpltq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f32 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (float32x4_t a, mve_pred16_t p) +{ + return vcmpltq_m (a, 1.1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c index d0e322fbede..beebe65a58f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s16.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s16 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int16x8_t a, int16_t b, mve_pred16_t p) { return vcmpltq_m_n_s16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.s16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s16 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int16x8_t a, int16_t b, mve_pred16_t p) { return vcmpltq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c index 7ec7963267a..07260c56ed3 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s32.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s32 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int32x4_t a, int32_t b, mve_pred16_t p) { return vcmpltq_m_n_s32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.s32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s32 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int32x4_t a, int32_t b, mve_pred16_t p) { return vcmpltq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c index 22434e88cd6..7d1e9e7fbde 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s8 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int8x16_t a, int8_t b, mve_pred16_t p) { return vcmpltq_m_n_s8 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.s8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s8 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int8x16_t a, int8_t b, mve_pred16_t p) { return vcmpltq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c index 359c0640784..c0f6dfc9432 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s16 lt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int16x8_t a, int16x8_t b, mve_pred16_t p) { return vcmpltq_m_s16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.s16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s16 lt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) { return vcmpltq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c index 3df7e89a6f5..b6fc4700e73 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s32 lt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int32x4_t a, int32x4_t b, mve_pred16_t p) { return vcmpltq_m_s32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.s32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s32 lt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) { return vcmpltq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c index 1055c2b661c..545b76359ad 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s8 lt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int8x16_t a, int8x16_t b, mve_pred16_t p) { return vcmpltq_m_s8 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.s8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.s8 lt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) { return vcmpltq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c index 2d55af20dd3..401ef21ba2b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c @@ -1,21 +1,51 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.f16 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float16x8_t a, float16_t b) { return vcmpltq_n_f16 (a, b); } -/* { dg-final { scan-assembler "vcmp.f16" } } */ +/* +**foo1: +** ... +** vcmp.f16 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float16x8_t a, float16_t b) { return vcmpltq (a, b); } -/* { dg-final { scan-assembler "vcmp.f16" } } */ +/* +**foo2: +** ... +** vcmp.f16 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (float16x8_t a) +{ + return vcmpltq (a, 1.1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c index 2590ca83c45..380f071e564 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c @@ -1,21 +1,51 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.f32 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float32x4_t a, float32_t b) { return vcmpltq_n_f32 (a, b); } -/* { dg-final { scan-assembler "vcmp.f32" } } */ +/* +**foo1: +** ... +** vcmp.f32 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float32x4_t a, float32_t b) { return vcmpltq (a, b); } -/* { dg-final { scan-assembler "vcmp.f32" } } */ +/* +**foo2: +** ... +** vcmp.f32 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (float32x4_t a) +{ + return vcmpltq (a, 1.1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c index 169f6ad4610..a1d12392dd2 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.s16 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int16x8_t a, int16_t b) { return vcmpltq_n_s16 (a, b); } -/* { dg-final { scan-assembler "vcmp.s16" } } */ +/* +**foo1: +** ... +** vcmp.s16 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int16x8_t a, int16_t b) { return vcmpltq (a, b); } -/* { dg-final { scan-assembler "vcmp.s16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c index 534047c2df3..6332f75f327 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.s32 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int32x4_t a, int32_t b) { return vcmpltq_n_s32 (a, b); } -/* { dg-final { scan-assembler "vcmp.s32" } } */ +/* +**foo1: +** ... +** vcmp.s32 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int32x4_t a, int32_t b) { return vcmpltq (a, b); } -/* { dg-final { scan-assembler "vcmp.s32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c index da659f1f2be..e0ac80caeb0 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.s8 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int8x16_t a, int8_t b) { return vcmpltq_n_s8 (a, b); } -/* { dg-final { scan-assembler "vcmp.s8" } } */ +/* +**foo1: +** ... +** vcmp.s8 lt, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int8x16_t a, int8_t b) { return vcmpltq (a, b); } -/* { dg-final { scan-assembler "vcmp.s8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s16.c index da4c90a07de..23843ad88f3 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s16.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.s16 lt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int16x8_t a, int16x8_t b) { return vcmpltq_s16 (a, b); } -/* { dg-final { scan-assembler "vcmp.s16" } } */ +/* +**foo1: +** ... +** vcmp.s16 lt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int16x8_t a, int16x8_t b) { return vcmpltq (a, b); } -/* { dg-final { scan-assembler "vcmp.s16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s32.c index 5dc218a5f40..aeb7a6f9896 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s32.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.s32 lt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int32x4_t a, int32x4_t b) { return vcmpltq_s32 (a, b); } -/* { dg-final { scan-assembler "vcmp.s32" } } */ +/* +**foo1: +** ... +** vcmp.s32 lt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int32x4_t a, int32x4_t b) { return vcmpltq (a, b); } -/* { dg-final { scan-assembler "vcmp.s32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s8.c index ea5853c212c..2129b56a5f7 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpltq_s8.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.s8 lt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int8x16_t a, int8x16_t b) { return vcmpltq_s8 (a, b); } -/* { dg-final { scan-assembler "vcmp.s8" } } */ +/* +**foo1: +** ... +** vcmp.s8 lt, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int8x16_t a, int8x16_t b) { return vcmpltq (a, b); } -/* { dg-final { scan-assembler "vcmp.s8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f16.c index 8d1c6096c56..c27ea2f0de8 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f16.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.f16 ne, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float16x8_t a, float16x8_t b) { return vcmpneq_f16 (a, b); } -/* { dg-final { scan-assembler "vcmp.f16" } } */ +/* +**foo1: +** ... +** vcmp.f16 ne, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float16x8_t a, float16x8_t b) { return vcmpneq (a, b); } -/* { dg-final { scan-assembler "vcmp.f16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f32.c index 860bd69c129..609de44d8e7 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_f32.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.f32 ne, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float32x4_t a, float32x4_t b) { return vcmpneq_f32 (a, b); } -/* { dg-final { scan-assembler "vcmp.f32" } } */ +/* +**foo1: +** ... +** vcmp.f32 ne, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float32x4_t a, float32x4_t b) { return vcmpneq (a, b); } -/* { dg-final { scan-assembler "vcmp.f32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c index a4e62de7272..98f22337d61 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f16 ne, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmpneq_m_f16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f16 ne, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vcmpneq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c index b18a2e5fd88..7f6e96ae47e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f32 ne, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmpneq_m_f32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f32 ne, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vcmpneq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c index c127b3a68f6..71b3476fb18 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f16.c @@ -1,22 +1,63 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float16x8_t a, float16_t b, mve_pred16_t p) { return vcmpneq_m_n_f16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float16x8_t a, float16_t b, mve_pred16_t p) { return vcmpneq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (float16x8_t a, mve_pred16_t p) +{ + return vcmpneq_m (a, 1.1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c index a8423d45708..d6dea8db865 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_f32.c @@ -1,22 +1,63 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float32x4_t a, float32_t b, mve_pred16_t p) { return vcmpneq_m_n_f32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float32x4_t a, float32_t b, mve_pred16_t p) { return vcmpneq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.f32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (float32x4_t a, mve_pred16_t p) +{ + return vcmpneq_m (a, 1.1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c index 63ee1c3bffb..e72c9b62829 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s16.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int16x8_t a, int16_t b, mve_pred16_t p) { return vcmpneq_m_n_s16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.i16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int16x8_t a, int16_t b, mve_pred16_t p) { return vcmpneq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c index 10f6d448d76..47c90e31f49 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s32.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int32x4_t a, int32_t b, mve_pred16_t p) { return vcmpneq_m_n_s32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.i32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int32x4_t a, int32_t b, mve_pred16_t p) { return vcmpneq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c index 66e5d158c51..9d9da100046 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i8 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int8x16_t a, int8_t b, mve_pred16_t p) { return vcmpneq_m_n_s8 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.i8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i8 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int8x16_t a, int8_t b, mve_pred16_t p) { return vcmpneq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c index ffe6ff919cf..ea8cf24b358 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u16.c @@ -1,22 +1,63 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint16x8_t a, uint16_t b, mve_pred16_t p) { return vcmpneq_m_n_u16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.i16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint16x8_t a, uint16_t b, mve_pred16_t p) { return vcmpneq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (uint16x8_t a, mve_pred16_t p) +{ + return vcmpneq_m (a, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c index 55e796a1138..30291dcdd9b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u32.c @@ -1,22 +1,63 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint32x4_t a, uint32_t b, mve_pred16_t p) { return vcmpneq_m_n_u32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.i32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint32x4_t a, uint32_t b, mve_pred16_t p) { return vcmpneq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (uint32x4_t a, mve_pred16_t p) +{ + return vcmpneq_m (a, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c index 3c8bd16647a..be75376a691 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c @@ -1,22 +1,63 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i8 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint8x16_t a, uint8_t b, mve_pred16_t p) { return vcmpneq_m_n_u8 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.i8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i8 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint8x16_t a, uint8_t b, mve_pred16_t p) { return vcmpneq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i8 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (uint8x16_t a, mve_pred16_t p) +{ + return vcmpneq_m (a, 1, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c index d3e1ce0e690..60e868141d0 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i16 ne, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int16x8_t a, int16x8_t b, mve_pred16_t p) { return vcmpneq_m_s16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.i16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i16 ne, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) { return vcmpneq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c index f5602ffd0da..780c544bef3 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i32 ne, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int32x4_t a, int32x4_t b, mve_pred16_t p) { return vcmpneq_m_s32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.i32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i32 ne, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) { return vcmpneq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c index 84b8b1617b0..15f6d316cba 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i8 ne, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int8x16_t a, int8x16_t b, mve_pred16_t p) { return vcmpneq_m_s8 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.i8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i8 ne, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) { return vcmpneq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c index 3c8943719bb..300852ed7b3 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i16 ne, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) { return vcmpneq_m_u16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.i16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i16 ne, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) { return vcmpneq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c index 980cc4124b2..227b5f01eca 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i32 ne, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) { return vcmpneq_m_u32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.i32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i32 ne, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) { return vcmpneq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c index 2615dcb37b9..cfcb59f49cf 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c @@ -1,22 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i8 ne, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) { return vcmpneq_m_u8 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vcmpt.i8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vcmpt.i8 ne, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) { return vcmpneq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c index e9e2a9c7b04..29e43f3fdf8 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c @@ -1,21 +1,51 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.f16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float16x8_t a, float16_t b) { return vcmpneq_n_f16 (a, b); } -/* { dg-final { scan-assembler "vcmp.f16" } } */ +/* +**foo1: +** ... +** vcmp.f16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float16x8_t a, float16_t b) { return vcmpneq (a, b); } -/* { dg-final { scan-assembler "vcmp.f16" } } */ +/* +**foo2: +** ... +** vcmp.f16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (float16x8_t a) +{ + return vcmpneq (a, 1.1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c index eb64b17969c..688e77cd044 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c @@ -1,21 +1,51 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.f32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (float32x4_t a, float32_t b) { return vcmpneq_n_f32 (a, b); } -/* { dg-final { scan-assembler "vcmp.f32" } } */ +/* +**foo1: +** ... +** vcmp.f32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (float32x4_t a, float32_t b) { return vcmpneq (a, b); } -/* { dg-final { scan-assembler "vcmp.f32" } } */ +/* +**foo2: +** ... +** vcmp.f32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (float32x4_t a) +{ + return vcmpneq (a, 1.1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c index 14689242ee4..2afc34d16e5 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.i16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int16x8_t a, int16_t b) { return vcmpneq_n_s16 (a, b); } -/* { dg-final { scan-assembler "vcmp.i16" } } */ +/* +**foo1: +** ... +** vcmp.i16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int16x8_t a, int16_t b) { return vcmpneq (a, b); } -/* { dg-final { scan-assembler "vcmp.i16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c index 53418ff3923..6c323161316 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.i32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int32x4_t a, int32_t b) { return vcmpneq_n_s32 (a, b); } -/* { dg-final { scan-assembler "vcmp.i32" } } */ +/* +**foo1: +** ... +** vcmp.i32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int32x4_t a, int32_t b) { return vcmpneq (a, b); } -/* { dg-final { scan-assembler "vcmp.i32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c index fa405c281b4..5483d6dd2fe 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.i8 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int8x16_t a, int8_t b) { return vcmpneq_n_s8 (a, b); } -/* { dg-final { scan-assembler "vcmp.i8" } } */ +/* +**foo1: +** ... +** vcmp.i8 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int8x16_t a, int8_t b) { return vcmpneq (a, b); } -/* { dg-final { scan-assembler "vcmp.i8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c index cc8540b3a6c..d8edfb0d825 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c @@ -1,21 +1,51 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.i16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint16x8_t a, uint16_t b) { return vcmpneq_n_u16 (a, b); } -/* { dg-final { scan-assembler "vcmp.i16" } } */ +/* +**foo1: +** ... +** vcmp.i16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint16x8_t a, uint16_t b) { return vcmpneq (a, b); } -/* { dg-final { scan-assembler "vcmp.i16" } } */ +/* +**foo2: +** ... +** vcmp.i16 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (uint16x8_t a) +{ + return vcmpneq (a, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c index 07c9b1ade96..2b7a6b56830 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c @@ -1,21 +1,51 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.i32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint32x4_t a, uint32_t b) { return vcmpneq_n_u32 (a, b); } -/* { dg-final { scan-assembler "vcmp.i32" } } */ +/* +**foo1: +** ... +** vcmp.i32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint32x4_t a, uint32_t b) { return vcmpneq (a, b); } -/* { dg-final { scan-assembler "vcmp.i32" } } */ +/* +**foo2: +** ... +** vcmp.i32 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (uint32x4_t a) +{ + return vcmpneq (a, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c index eac5e96384e..2dab43af331 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c @@ -1,21 +1,51 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.i8 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint8x16_t a, uint8_t b) { return vcmpneq_n_u8 (a, b); } -/* { dg-final { scan-assembler "vcmp.i8" } } */ +/* +**foo1: +** ... +** vcmp.i8 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint8x16_t a, uint8_t b) { return vcmpneq (a, b); } -/* { dg-final { scan-assembler "vcmp.i8" } } */ +/* +**foo2: +** ... +** vcmp.i8 ne, q[0-9]+, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ +mve_pred16_t +foo2 (uint8x16_t a) +{ + return vcmpneq (a, 1); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s16.c index 6b04ce70ffc..d57b607baa9 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s16.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.i16 ne, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int16x8_t a, int16x8_t b) { return vcmpneq_s16 (a, b); } -/* { dg-final { scan-assembler "vcmp.i16" } } */ +/* +**foo1: +** ... +** vcmp.i16 ne, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int16x8_t a, int16x8_t b) { return vcmpneq (a, b); } -/* { dg-final { scan-assembler "vcmp.i16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s32.c index cfb98d7e650..e02171f6686 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s32.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.i32 ne, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int32x4_t a, int32x4_t b) { return vcmpneq_s32 (a, b); } -/* { dg-final { scan-assembler "vcmp.i32" } } */ +/* +**foo1: +** ... +** vcmp.i32 ne, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int32x4_t a, int32x4_t b) { return vcmpneq (a, b); } -/* { dg-final { scan-assembler "vcmp.i32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s8.c index ae69be4ba0b..0abef8c3e00 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_s8.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.i8 ne, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (int8x16_t a, int8x16_t b) { return vcmpneq_s8 (a, b); } -/* { dg-final { scan-assembler "vcmp.i8" } } */ +/* +**foo1: +** ... +** vcmp.i8 ne, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (int8x16_t a, int8x16_t b) { return vcmpneq (a, b); } -/* { dg-final { scan-assembler "vcmp.i8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u16.c index 51059f21191..7144f3ee2fc 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u16.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.i16 ne, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint16x8_t a, uint16x8_t b) { return vcmpneq_u16 (a, b); } -/* { dg-final { scan-assembler "vcmp.i16" } } */ +/* +**foo1: +** ... +** vcmp.i16 ne, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint16x8_t a, uint16x8_t b) { return vcmpneq (a, b); } -/* { dg-final { scan-assembler "vcmp.i16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u32.c index 42e4a3f4f2d..a31134f2f1d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u32.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.i32 ne, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint32x4_t a, uint32x4_t b) { return vcmpneq_u32 (a, b); } -/* { dg-final { scan-assembler "vcmp.i32" } } */ +/* +**foo1: +** ... +** vcmp.i32 ne, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint32x4_t a, uint32x4_t b) { return vcmpneq (a, b); } -/* { dg-final { scan-assembler "vcmp.i32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u8.c index addacc15833..2801c8e3763 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmpneq_u8.c @@ -1,21 +1,37 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vcmp.i8 ne, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo (uint8x16_t a, uint8x16_t b) { return vcmpneq_u8 (a, b); } -/* { dg-final { scan-assembler "vcmp.i8" } } */ +/* +**foo1: +** ... +** vcmp.i8 ne, q[0-9]+, q[0-9]+(?: @.*|) +** ... +** vmrs (?:ip|fp|r[0-9]+), p0(?: @.*|) +** ... +*/ mve_pred16_t foo1 (uint8x16_t a, uint8x16_t b) { return vcmpneq (a, b); } -/* { dg-final { scan-assembler "vcmp.i8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file From patchwork Thu Nov 17 16:37:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit 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gcc.target/arm/mve/intrinsics/vminaq_m_s16.c: Improve test. * gcc.target/arm/mve/intrinsics/vminaq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminaq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminaq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminaq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminaq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminavq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminavq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminavq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminavq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminavq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminavq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmaq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmaq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmavq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmavq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmvq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmvq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_x_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_p_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_u8.c: Likewise. --- .../arm/mve/intrinsics/vminaq_m_s16.c | 25 +++++++++-- .../arm/mve/intrinsics/vminaq_m_s32.c | 25 +++++++++-- .../arm/mve/intrinsics/vminaq_m_s8.c | 25 +++++++++-- .../arm/mve/intrinsics/vminaq_s16.c | 16 +++++++- .../arm/mve/intrinsics/vminaq_s32.c | 16 +++++++- .../gcc.target/arm/mve/intrinsics/vminaq_s8.c | 16 +++++++- .../arm/mve/intrinsics/vminavq_p_s16.c | 41 ++++++++++++++++--- .../arm/mve/intrinsics/vminavq_p_s32.c | 41 ++++++++++++++++--- .../arm/mve/intrinsics/vminavq_p_s8.c | 41 ++++++++++++++++--- .../arm/mve/intrinsics/vminavq_s16.c | 29 ++++++++++--- .../arm/mve/intrinsics/vminavq_s32.c | 29 ++++++++++--- .../arm/mve/intrinsics/vminavq_s8.c | 29 ++++++++++--- .../arm/mve/intrinsics/vminnmaq_f16.c | 16 +++++++- .../arm/mve/intrinsics/vminnmaq_f32.c | 16 +++++++- .../arm/mve/intrinsics/vminnmaq_m_f16.c | 25 +++++++++-- .../arm/mve/intrinsics/vminnmaq_m_f32.c | 25 +++++++++-- .../arm/mve/intrinsics/vminnmavq_f16.c | 27 +++++++++--- .../arm/mve/intrinsics/vminnmavq_f32.c | 27 +++++++++--- .../arm/mve/intrinsics/vminnmavq_p_f16.c | 39 +++++++++++++++--- .../arm/mve/intrinsics/vminnmavq_p_f32.c | 39 +++++++++++++++--- .../arm/mve/intrinsics/vminnmq_f16.c | 16 +++++++- .../arm/mve/intrinsics/vminnmq_f32.c | 16 +++++++- .../arm/mve/intrinsics/vminnmq_m_f16.c | 26 ++++++++++-- .../arm/mve/intrinsics/vminnmq_m_f32.c | 26 ++++++++++-- .../arm/mve/intrinsics/vminnmq_x_f16.c | 25 +++++++++-- .../arm/mve/intrinsics/vminnmq_x_f32.c | 25 +++++++++-- .../arm/mve/intrinsics/vminnmvq_f16.c | 27 +++++++++--- .../arm/mve/intrinsics/vminnmvq_f32.c | 27 +++++++++--- .../arm/mve/intrinsics/vminnmvq_p_f16.c | 39 +++++++++++++++--- .../arm/mve/intrinsics/vminnmvq_p_f32.c | 39 +++++++++++++++--- .../arm/mve/intrinsics/vminq_m_s16.c | 26 ++++++++++-- .../arm/mve/intrinsics/vminq_m_s32.c | 26 ++++++++++-- .../arm/mve/intrinsics/vminq_m_s8.c | 26 ++++++++++-- .../arm/mve/intrinsics/vminq_m_u16.c | 26 ++++++++++-- .../arm/mve/intrinsics/vminq_m_u32.c | 26 ++++++++++-- .../arm/mve/intrinsics/vminq_m_u8.c | 26 ++++++++++-- .../gcc.target/arm/mve/intrinsics/vminq_s16.c | 16 +++++++- .../gcc.target/arm/mve/intrinsics/vminq_s32.c | 16 +++++++- .../gcc.target/arm/mve/intrinsics/vminq_s8.c | 16 +++++++- .../gcc.target/arm/mve/intrinsics/vminq_u16.c | 16 +++++++- .../gcc.target/arm/mve/intrinsics/vminq_u32.c | 16 +++++++- .../gcc.target/arm/mve/intrinsics/vminq_u8.c | 16 +++++++- .../arm/mve/intrinsics/vminq_x_s16.c | 25 +++++++++-- .../arm/mve/intrinsics/vminq_x_s32.c | 25 +++++++++-- .../arm/mve/intrinsics/vminq_x_s8.c | 25 +++++++++-- .../arm/mve/intrinsics/vminq_x_u16.c | 25 +++++++++-- .../arm/mve/intrinsics/vminq_x_u32.c | 25 +++++++++-- .../arm/mve/intrinsics/vminq_x_u8.c | 25 +++++++++-- .../arm/mve/intrinsics/vminvq_p_s16.c | 31 ++++++++++---- .../arm/mve/intrinsics/vminvq_p_s32.c | 31 ++++++++++---- .../arm/mve/intrinsics/vminvq_p_s8.c | 31 ++++++++++---- .../arm/mve/intrinsics/vminvq_p_u16.c | 39 +++++++++++++++--- .../arm/mve/intrinsics/vminvq_p_u32.c | 39 +++++++++++++++--- .../arm/mve/intrinsics/vminvq_p_u8.c | 39 +++++++++++++++--- .../arm/mve/intrinsics/vminvq_s16.c | 22 ++++++---- .../arm/mve/intrinsics/vminvq_s32.c | 22 ++++++---- .../gcc.target/arm/mve/intrinsics/vminvq_s8.c | 22 ++++++---- .../arm/mve/intrinsics/vminvq_u16.c | 29 ++++++++++--- .../arm/mve/intrinsics/vminvq_u32.c | 26 ++++++++++-- .../gcc.target/arm/mve/intrinsics/vminvq_u8.c | 29 ++++++++++--- 60 files changed, 1320 insertions(+), 255 deletions(-) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s16.c index 0324110c6a8..925b9154ca7 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s16.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminat.s16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint16x8_t a, int16x8_t b, mve_pred16_t p) { return vminaq_m_s16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vminat.s16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminat.s16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint16x8_t a, int16x8_t b, mve_pred16_t p) { return vminaq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s32.c index a2886d4f40f..296f69dfcda 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s32.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminat.s32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32x4_t a, int32x4_t b, mve_pred16_t p) { return vminaq_m_s32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vminat.s32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminat.s32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32x4_t a, int32x4_t b, mve_pred16_t p) { return vminaq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s8.c index 95eb038efc0..cf6fecc3461 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s8.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminat.s8 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint8x16_t a, int8x16_t b, mve_pred16_t p) { return vminaq_m_s8 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vminat.s8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminat.s8 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint8x16_t a, int8x16_t b, mve_pred16_t p) { return vminaq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s16.c index 3a157e00a27..63f59f8c80a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s16.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmina.s16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint16x8_t a, int16x8_t b) { return vminaq_s16 (a, b); } -/* { dg-final { scan-assembler "vmina.s16" } } */ +/* +**foo1: +** ... +** vmina.s16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint16x8_t a, int16x8_t b) { return vminaq (a, b); } -/* { dg-final { scan-assembler "vmina.s16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s32.c index 5c732c65d63..eb0a54cbe19 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s32.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmina.s32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32x4_t a, int32x4_t b) { return vminaq_s32 (a, b); } -/* { dg-final { scan-assembler "vmina.s32" } } */ +/* +**foo1: +** ... +** vmina.s32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32x4_t a, int32x4_t b) { return vminaq (a, b); } -/* { dg-final { scan-assembler "vmina.s32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s8.c index 2e4dad141ce..b875308863d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s8.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmina.s8 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint8x16_t a, int8x16_t b) { return vminaq_s8 (a, b); } -/* { dg-final { scan-assembler "vmina.s8" } } */ +/* +**foo1: +** ... +** vmina.s8 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint8x16_t a, int8x16_t b) { return vminaq (a, b); } -/* { dg-final { scan-assembler "vmina.s8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s16.c index 9303ae02e39..5d3c40fb1fc 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s16.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint16_t foo (uint16_t a, int16x8_t b, mve_pred16_t p) { @@ -11,18 +22,36 @@ foo (uint16_t a, int16x8_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint16_t foo1 (uint16_t a, int16x8_t b, mve_pred16_t p) { return vminavq_p (a, b, p); } - -int16_t -foo2 (uint8_t a, int16x8_t b, mve_pred16_t p) +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ +uint16_t +foo2 (int16x8_t b, mve_pred16_t p) { - return vminavq_p (a, b, p); + return vminavq_p (1, b, p); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminavt.s16" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s32.c index 36247f68b2c..ee4ff251d63 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s32.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo (uint32_t a, int32x4_t b, mve_pred16_t p) { @@ -11,18 +22,36 @@ foo (uint32_t a, int32x4_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo1 (uint32_t a, int32x4_t b, mve_pred16_t p) { return vminavq_p (a, b, p); } - -int32_t -foo2 (uint16_t a, int32x4_t b, mve_pred16_t p) +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ +uint32_t +foo2 (int32x4_t b, mve_pred16_t p) { - return vminavq_p (a, b, p); + return vminavq_p (1, b, p); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminavt.s32" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s8.c index d3361615dcc..14602c29719 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s8.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint8_t foo (uint8_t a, int8x16_t b, mve_pred16_t p) { @@ -11,18 +22,36 @@ foo (uint8_t a, int8x16_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint8_t foo1 (uint8_t a, int8x16_t b, mve_pred16_t p) { return vminavq_p (a, b, p); } - -int8_t -foo2 (uint32_t a, int8x16_t b, mve_pred16_t p) +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ +uint8_t +foo2 (int8x16_t b, mve_pred16_t p) { - return vminavq_p (a, b, p); + return vminavq_p (1, b, p); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminavt.s8" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s16.c index 17e4edca2f1..51f75ae1f6a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s16.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vminav.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint16_t foo (uint16_t a, int16x8_t b) { @@ -11,18 +18,28 @@ foo (uint16_t a, int16x8_t b) } +/* +**foo1: +** ... +** vminav.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint16_t foo1 (uint16_t a, int16x8_t b) { return vminavq (a, b); } - -int16_t -foo2 (uint8_t a, int16x8_t b) +/* +**foo2: +** ... +** vminav.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ +uint16_t +foo2 (int16x8_t b) { - return vminavq (a, b); + return vminavq (1, b); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminav.s16" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s32.c index 032d02b8857..d1602cebe18 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s32.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vminav.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo (uint32_t a, int32x4_t b) { @@ -11,18 +18,28 @@ foo (uint32_t a, int32x4_t b) } +/* +**foo1: +** ... +** vminav.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo1 (uint32_t a, int32x4_t b) { return vminavq (a, b); } - -int32_t -foo2 (uint16_t a, int32x4_t b) +/* +**foo2: +** ... +** vminav.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ +uint32_t +foo2 (int32x4_t b) { - return vminavq (a, b); + return vminavq (1, b); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminav.s32" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s8.c index 2a2bb3d6146..f4c9b045b90 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s8.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vminav.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint8_t foo (uint8_t a, int8x16_t b) { @@ -11,18 +18,28 @@ foo (uint8_t a, int8x16_t b) } +/* +**foo1: +** ... +** vminav.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint8_t foo1 (uint8_t a, int8x16_t b) { return vminavq (a, b); } - -int8_t -foo2 (uint32_t a, int8x16_t b) +/* +**foo2: +** ... +** vminav.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ +uint8_t +foo2 (int8x16_t b) { - return vminavq (a, b); + return vminavq (1, b); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminav.s8" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c index cf32186d642..1728d104266 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vminnma.f16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t a, float16x8_t b) { return vminnmaq_f16 (a, b); } -/* { dg-final { scan-assembler "vminnma.f16" } } */ +/* +**foo1: +** ... +** vminnma.f16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t a, float16x8_t b) { return vminnmaq (a, b); } -/* { dg-final { scan-assembler "vminnma.f16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c index 1c3f19c9e1b..42b4265d9cc 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vminnma.f32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t a, float32x4_t b) { return vminnmaq_f32 (a, b); } -/* { dg-final { scan-assembler "vminnma.f32" } } */ +/* +**foo1: +** ... +** vminnma.f32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t a, float32x4_t b) { return vminnmaq (a, b); } -/* { dg-final { scan-assembler "vminnma.f32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c index 4423903e913..51b85bd2b04 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmat.f16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vminnmaq_m_f16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vminnmat.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmat.f16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vminnmaq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c index 683f40ad3d8..2f0423ecb4f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmat.f32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vminnmaq_m_f32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vminnmat.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmat.f32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vminnmaq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c index fadb23e05c8..17e4ad16759 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vminnmav.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t foo (float16_t a, float16x8_t b) { @@ -11,18 +18,28 @@ foo (float16_t a, float16x8_t b) } +/* +**foo1: +** ... +** vminnmav.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t foo1 (float16_t a, float16x8_t b) { return vminnmavq (a, b); } - +/* +**foo2: +** ... +** vminnmav.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t -foo2 (float32_t a, float16x8_t b) +foo2 (float16x8_t b) { - return vminnmavq (a, b); + return vminnmavq (1.1, b); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminnmav.f16" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c index 84714a96b9f..2758e59666e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vminnmav.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t foo (float32_t a, float32x4_t b) { @@ -11,18 +18,28 @@ foo (float32_t a, float32x4_t b) } +/* +**foo1: +** ... +** vminnmav.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t foo1 (float32_t a, float32x4_t b) { return vminnmavq (a, b); } - +/* +**foo2: +** ... +** vminnmav.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t -foo2 (float16_t a, float32x4_t b) +foo2 (float32x4_t b) { - return vminnmavq (a, b); + return vminnmavq (1.1, b); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminnmav.f32" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c index c79fa307ae0..b60a6627aea 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmavt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t foo (float16_t a, float16x8_t b, mve_pred16_t p) { @@ -11,18 +22,36 @@ foo (float16_t a, float16x8_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmavt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t foo1 (float16_t a, float16x8_t b, mve_pred16_t p) { return vminnmavq_p (a, b, p); } - +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmavt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t -foo2 (float32_t a, float16x8_t b, mve_pred16_t p) +foo2 (float16x8_t b, mve_pred16_t p) { - return vminnmavq_p (a, b, p); + return vminnmavq_p (1.1, b, p); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminnmavt.f16" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c index bea04c7aac6..6fa97b74a65 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmavt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t foo (float32_t a, float32x4_t b, mve_pred16_t p) { @@ -11,18 +22,36 @@ foo (float32_t a, float32x4_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmavt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t foo1 (float32_t a, float32x4_t b, mve_pred16_t p) { return vminnmavq_p (a, b, p); } - +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmavt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t -foo2 (float16_t a, float32x4_t b, mve_pred16_t p) +foo2 (float32x4_t b, mve_pred16_t p) { - return vminnmavq_p (a, b, p); + return vminnmavq_p (1.1, b, p); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminnmavt.f32" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c index 18d4a4c1330..c0962b52631 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vminnm.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t a, float16x8_t b) { return vminnmq_f16 (a, b); } -/* { dg-final { scan-assembler "vminnm.f16" } } */ +/* +**foo1: +** ... +** vminnm.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t a, float16x8_t b) { return vminnmq (a, b); } -/* { dg-final { scan-assembler "vminnm.f16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c index 34144cad17f..a9c3e5f74b1 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vminnm.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t a, float32x4_t b) { return vminnmq_f32 (a, b); } -/* { dg-final { scan-assembler "vminnm.f32" } } */ +/* +**foo1: +** ... +** vminnm.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t a, float32x4_t b) { return vminnmq (a, b); } -/* { dg-final { scan-assembler "vminnm.f32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c index e5533d28035..466264249c5 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c @@ -1,23 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) { return vminnmq_m_f16 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vminnmt.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) { return vminnmq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vminnmt.f16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c index 382d16c4489..57edc8e1a80 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c @@ -1,23 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) { return vminnmq_m_f32 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vminnmt.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) { return vminnmq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vminnmt.f32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c index 04d606ce5cd..73b4ccba080 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vminnmq_x_f16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vminnmt.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vminnmq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c index 87cd970fd11..9a824566212 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vminnmq_x_f32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vminnmt.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vminnmq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c index 0eb3a4af14e..dc00d02df7d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vminnmv.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t foo (float16_t a, float16x8_t b) { @@ -11,18 +18,28 @@ foo (float16_t a, float16x8_t b) } +/* +**foo1: +** ... +** vminnmv.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t foo1 (float16_t a, float16x8_t b) { return vminnmvq (a, b); } - +/* +**foo2: +** ... +** vminnmv.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t -foo2 (float32_t a, float16x8_t b) +foo2 (float16x8_t b) { - return vminnmvq (a, b); + return vminnmvq (1.1, b); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminnmv.f16" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c index f3183508f8e..ff23c818452 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vminnmv.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t foo (float32_t a, float32x4_t b) { @@ -11,18 +18,28 @@ foo (float32_t a, float32x4_t b) } +/* +**foo1: +** ... +** vminnmv.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t foo1 (float32_t a, float32x4_t b) { return vminnmvq (a, b); } - +/* +**foo2: +** ... +** vminnmv.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t -foo2 (float16_t a, float32x4_t b) +foo2 (float32x4_t b) { - return vminnmvq (a, b); + return vminnmvq (1.1, b); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminnmv.f32" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c index 16f6ac514c8..ad99f586d11 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmvt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t foo (float16_t a, float16x8_t b, mve_pred16_t p) { @@ -11,18 +22,36 @@ foo (float16_t a, float16x8_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmvt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t foo1 (float16_t a, float16x8_t b, mve_pred16_t p) { return vminnmvq_p (a, b, p); } - +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmvt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t -foo2 (float32_t a, float16x8_t b, mve_pred16_t p) +foo2 (float16x8_t b, mve_pred16_t p) { - return vminnmvq_p (a, b, p); + return vminnmvq_p (1.1, b, p); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminnmvt.f16" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c index a8e4f9ffba7..3c7e5c07a68 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmvt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t foo (float32_t a, float32x4_t b, mve_pred16_t p) { @@ -11,18 +22,36 @@ foo (float32_t a, float32x4_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmvt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t foo1 (float32_t a, float32x4_t b, mve_pred16_t p) { return vminnmvq_p (a, b, p); } - +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmvt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t -foo2 (float16_t a, float32x4_t b, mve_pred16_t p) +foo2 (float32x4_t b, mve_pred16_t p) { - return vminnmvq_p (a, b, p); + return vminnmvq_p (1.1, b, p); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminnmvt.f32" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c index f257ddcf600..fe7368eeb38 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c @@ -1,23 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) { return vminq_m_s16 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.s16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) { return vminq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.s16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c index 957da71d0e3..a90a1db8835 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c @@ -1,23 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) { return vminq_m_s32 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.s32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) { return vminq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.s32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c index fea8bfd7994..911bd3af0dc 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c @@ -1,23 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) { return vminq_m_s8 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.s8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) { return vminq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.s8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c index 7cc19a7dd5d..f80288aaf79 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c @@ -1,23 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) { return vminq_m_u16 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.u16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) { return vminq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.u16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c index 301fbfc751f..b480089f4f3 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c @@ -1,23 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) { return vminq_m_u32 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) { return vminq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.u32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c index 7a65b3557a3..73633c9612e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c @@ -1,23 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) { return vminq_m_u8 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.u8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) { return vminq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.u8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s16.c index d46a3c4ee18..eb34dc4c41c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s16.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmin.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo (int16x8_t a, int16x8_t b) { return vminq_s16 (a, b); } -/* { dg-final { scan-assembler "vmin.s16" } } */ +/* +**foo1: +** ... +** vmin.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo1 (int16x8_t a, int16x8_t b) { return vminq (a, b); } -/* { dg-final { scan-assembler "vmin.s16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s32.c index 601e918a5bf..60d29da4e14 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s32.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmin.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo (int32x4_t a, int32x4_t b) { return vminq_s32 (a, b); } -/* { dg-final { scan-assembler "vmin.s32" } } */ +/* +**foo1: +** ... +** vmin.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo1 (int32x4_t a, int32x4_t b) { return vminq (a, b); } -/* { dg-final { scan-assembler "vmin.s32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s8.c index e2ae2341ad8..675fb8edfb1 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s8.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmin.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo (int8x16_t a, int8x16_t b) { return vminq_s8 (a, b); } -/* { dg-final { scan-assembler "vmin.s8" } } */ +/* +**foo1: +** ... +** vmin.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo1 (int8x16_t a, int8x16_t b) { return vminq (a, b); } -/* { dg-final { scan-assembler "vmin.s8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u16.c index 3cac573f6ef..50f648d5133 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u16.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmin.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint16x8_t a, uint16x8_t b) { return vminq_u16 (a, b); } -/* { dg-final { scan-assembler "vmin.u16" } } */ +/* +**foo1: +** ... +** vmin.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint16x8_t a, uint16x8_t b) { return vminq (a, b); } -/* { dg-final { scan-assembler "vmin.u16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u32.c index ca3ef245fe9..bcfead39c5a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u32.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmin.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32x4_t a, uint32x4_t b) { return vminq_u32 (a, b); } -/* { dg-final { scan-assembler "vmin.u32" } } */ +/* +**foo1: +** ... +** vmin.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32x4_t a, uint32x4_t b) { return vminq (a, b); } -/* { dg-final { scan-assembler "vmin.u32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u8.c index b7ef4db22ff..e8eacae4da8 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u8.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmin.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint8x16_t a, uint8x16_t b) { return vminq_u8 (a, b); } -/* { dg-final { scan-assembler "vmin.u8" } } */ +/* +**foo1: +** ... +** vmin.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint8x16_t a, uint8x16_t b) { return vminq (a, b); } -/* { dg-final { scan-assembler "vmin.u8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c index af93c78658e..0d8987e16b8 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo (int16x8_t a, int16x8_t b, mve_pred16_t p) { return vminq_x_s16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.s16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) { return vminq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c index 76f0831e48e..3c3595171ea 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo (int32x4_t a, int32x4_t b, mve_pred16_t p) { return vminq_x_s32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.s32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) { return vminq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c index fdd6e94497c..402c4aa121d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo (int8x16_t a, int8x16_t b, mve_pred16_t p) { return vminq_x_s8 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.s8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) { return vminq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c index 9842954c761..e27a3416e38 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) { return vminq_x_u16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.u16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) { return vminq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c index 741e4508879..d3cb29bf60c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) { return vminq_x_u32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) { return vminq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c index 13743fc87a1..3e05ef7dd13 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) { return vminq_x_u8 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.u8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) { return vminq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s16.c index 91bb63f6ba6..7c25c9d2f82 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s16.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminvt.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int16_t foo (int16_t a, int16x8_t b, mve_pred16_t p) { @@ -11,18 +22,20 @@ foo (int16_t a, int16x8_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminvt.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int16_t foo1 (int16_t a, int16x8_t b, mve_pred16_t p) { return vminvq_p (a, b, p); } - -int16_t -foo2 (int8_t a, int16x8_t b, mve_pred16_t p) -{ - return vminvq_p (a, b, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminvt.s16" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s32.c index a846701312c..d5f7418af38 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s32.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminvt.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int32_t foo (int32_t a, int32x4_t b, mve_pred16_t p) { @@ -11,18 +22,20 @@ foo (int32_t a, int32x4_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminvt.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int32_t foo1 (int32_t a, int32x4_t b, mve_pred16_t p) { return vminvq_p (a, b, p); } - -int32_t -foo2 (int16_t a, int32x4_t b, mve_pred16_t p) -{ - return vminvq_p (a, b, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminvt.s32" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c index 716d414f3a7..6a42170fc19 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminvt.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int8_t foo (int8_t a, int8x16_t b, mve_pred16_t p) { @@ -11,18 +22,20 @@ foo (int8_t a, int8x16_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminvt.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int8_t foo1 (int8_t a, int8x16_t b, mve_pred16_t p) { return vminvq_p (a, b, p); } - -int8_t -foo2 (int32_t a, int8x16_t b, mve_pred16_t p) -{ - return vminvq_p (a, b, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminvt.s8" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c index cc7f8fe8933..8f2f68fef84 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminvt.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint16_t foo (uint16_t a, uint16x8_t b, mve_pred16_t p) { @@ -11,18 +22,36 @@ foo (uint16_t a, uint16x8_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminvt.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint16_t foo1 (uint16_t a, uint16x8_t b, mve_pred16_t p) { return vminvq_p (a, b, p); } - +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminvt.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint16_t -foo2 (uint32_t a, uint16x8_t b, mve_pred16_t p) +foo2 (uint16x8_t b, mve_pred16_t p) { - return vminvq_p (a, b, p); + return vminvq_p (1, b, p); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminvt.u16" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c index 6bde0be29cc..9d14c39c1dc 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminvt.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo (uint32_t a, uint32x4_t b, mve_pred16_t p) { @@ -11,18 +22,36 @@ foo (uint32_t a, uint32x4_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminvt.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo1 (uint32_t a, uint32x4_t b, mve_pred16_t p) { return vminvq_p (a, b, p); } - +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminvt.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint32_t -foo2 (uint8_t a, uint32x4_t b, mve_pred16_t p) +foo2 (uint32x4_t b, mve_pred16_t p) { - return vminvq_p (a, b, p); + return vminvq_p (1, b, p); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminvt.u32" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c index bb894904f3c..4c1f4406852 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminvt.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint8_t foo (uint8_t a, uint8x16_t b, mve_pred16_t p) { @@ -11,18 +22,36 @@ foo (uint8_t a, uint8x16_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminvt.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint8_t foo1 (uint8_t a, uint8x16_t b, mve_pred16_t p) { return vminvq_p (a, b, p); } - +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminvt.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint8_t -foo2 (uint16_t a, uint8x16_t b, mve_pred16_t p) +foo2 (uint8x16_t b, mve_pred16_t p) { - return vminvq_p (a, b, p); + return vminvq_p (1, b, p); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminvt.u8" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c index 6d589aa4a05..e3242c0aa4d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vminv.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int16_t foo (int16_t a, int16x8_t b) { @@ -11,17 +18,16 @@ foo (int16_t a, int16x8_t b) } +/* +**foo1: +** ... +** vminv.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int16_t foo1 (int16_t a, int16x8_t b) { return vminvq (a, b); } -int16_t -foo2 (int8_t a, int16x8_t b) -{ - return vminvq (a, b); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminv.s16" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c index 7c727d6d92b..1325b38411d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vminv.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int32_t foo (int32_t a, int32x4_t b) { @@ -11,17 +18,16 @@ foo (int32_t a, int32x4_t b) } +/* +**foo1: +** ... +** vminv.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int32_t foo1 (int32_t a, int32x4_t b) { return vminvq (a, b); } -int32_t -foo2 (int8_t a, int32x4_t b) -{ - return vminvq (a, b); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminv.s32" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c index 76309482fc5..81c14a8ac6b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vminv.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int8_t foo (int8_t a, int8x16_t b) { @@ -11,17 +18,16 @@ foo (int8_t a, int8x16_t b) } +/* +**foo1: +** ... +** vminv.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int8_t foo1 (int8_t a, int8x16_t b) { return vminvq (a, b); } -int8_t -foo2 (int32_t a, int8x16_t b) -{ - return vminvq (a, b); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminv.s8" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c index 698975f456c..4372ac62388 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vminv.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint16_t foo (uint16_t a, uint16x8_t b) { @@ -11,18 +18,28 @@ foo (uint16_t a, uint16x8_t b) } +/* +**foo1: +** ... +** vminv.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint16_t foo1 (uint16_t a, uint16x8_t b) { return vminvq (a, b); } - -uint8_t -foo2 (uint32_t a, uint16x8_t b) +/* +**foo2: +** ... +** vminv.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ +uint16_t +foo2 (uint16x8_t b) { - return vminvq (a, b); + return vminvq (1, b); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminv.u16" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c index 7489f81debf..aff3679f49d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vminv.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo (uint32_t a, uint32x4_t b) { @@ -11,17 +18,28 @@ foo (uint32_t a, uint32x4_t b) } +/* +**foo1: +** ... +** vminv.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo1 (uint32_t a, uint32x4_t b) { return vminvq (a, b); } +/* +**foo2: +** ... +** vminv.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint32_t -foo2 (uint16_t a, uint32x4_t b) +foo2 (uint32x4_t b) { - return vminvq (a, b); + return vminvq (1, b); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminv.u32" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c index aa2b986d558..883e5f2d2c7 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vminv.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint8_t foo (uint8_t a, uint8x16_t b) { @@ -11,18 +18,28 @@ foo (uint8_t a, uint8x16_t b) } +/* +**foo1: +** ... +** vminv.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint8_t foo1 (uint8_t a, uint8x16_t b) { return vminvq (a, b); } - -uint16_t -foo2 (uint32_t a, uint8x16_t b) +/* +**foo2: +** ... +** vminv.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ +uint8_t +foo2 (uint8x16_t b) { - return vminvq (a, b); + return vminvq (1, b); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminv.u8" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file From patchwork Thu Nov 17 16:37:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Corallo X-Patchwork-Id: 60782 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org 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VI1EUR03FT048.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR08MB7309 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andrea Corallo via Gcc-patches From: Andrea Corallo Reply-To: Andrea Corallo Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c: Improve test. * gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxaq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxaq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxaq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxavq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxavq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxavq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vmaxvq_u8.c: Likewise. --- .../arm/mve/intrinsics/vmaxaq_m_s16.c | 25 +++++++++-- .../arm/mve/intrinsics/vmaxaq_m_s32.c | 25 +++++++++-- .../arm/mve/intrinsics/vmaxaq_m_s8.c | 25 +++++++++-- .../arm/mve/intrinsics/vmaxaq_s16.c | 16 +++++++- .../arm/mve/intrinsics/vmaxaq_s32.c | 16 +++++++- .../gcc.target/arm/mve/intrinsics/vmaxaq_s8.c | 16 +++++++- .../arm/mve/intrinsics/vmaxavq_p_s16.c | 41 ++++++++++++++++--- .../arm/mve/intrinsics/vmaxavq_p_s32.c | 41 ++++++++++++++++--- .../arm/mve/intrinsics/vmaxavq_p_s8.c | 41 ++++++++++++++++--- .../arm/mve/intrinsics/vmaxavq_s16.c | 29 ++++++++++--- .../arm/mve/intrinsics/vmaxavq_s32.c | 29 ++++++++++--- .../arm/mve/intrinsics/vmaxavq_s8.c | 29 ++++++++++--- .../arm/mve/intrinsics/vmaxnmaq_f16.c | 16 +++++++- .../arm/mve/intrinsics/vmaxnmaq_f32.c | 16 +++++++- .../arm/mve/intrinsics/vmaxnmaq_m_f16.c | 25 +++++++++-- .../arm/mve/intrinsics/vmaxnmaq_m_f32.c | 25 +++++++++-- .../arm/mve/intrinsics/vmaxnmavq_f16.c | 27 +++++++++--- .../arm/mve/intrinsics/vmaxnmavq_f32.c | 27 +++++++++--- .../arm/mve/intrinsics/vmaxnmavq_p_f16.c | 39 +++++++++++++++--- .../arm/mve/intrinsics/vmaxnmavq_p_f32.c | 39 +++++++++++++++--- .../arm/mve/intrinsics/vmaxnmq_f16.c | 16 +++++++- .../arm/mve/intrinsics/vmaxnmq_f32.c | 16 +++++++- .../arm/mve/intrinsics/vmaxnmq_m_f16.c | 26 ++++++++++-- .../arm/mve/intrinsics/vmaxnmq_m_f32.c | 26 ++++++++++-- .../arm/mve/intrinsics/vmaxnmq_x_f16.c | 25 +++++++++-- .../arm/mve/intrinsics/vmaxnmq_x_f32.c | 25 +++++++++-- .../arm/mve/intrinsics/vmaxnmvq_f16.c | 27 +++++++++--- .../arm/mve/intrinsics/vmaxnmvq_f32.c | 27 +++++++++--- .../arm/mve/intrinsics/vmaxnmvq_p_f16.c | 39 +++++++++++++++--- .../arm/mve/intrinsics/vmaxnmvq_p_f32.c | 39 +++++++++++++++--- .../arm/mve/intrinsics/vmaxq_m_s16.c | 26 ++++++++++-- .../arm/mve/intrinsics/vmaxq_m_s32.c | 26 ++++++++++-- .../arm/mve/intrinsics/vmaxq_m_s8.c | 26 ++++++++++-- .../arm/mve/intrinsics/vmaxq_m_u16.c | 26 ++++++++++-- .../arm/mve/intrinsics/vmaxq_m_u32.c | 26 ++++++++++-- .../arm/mve/intrinsics/vmaxq_m_u8.c | 26 ++++++++++-- .../gcc.target/arm/mve/intrinsics/vmaxq_s16.c | 16 +++++++- .../gcc.target/arm/mve/intrinsics/vmaxq_s32.c | 16 +++++++- .../gcc.target/arm/mve/intrinsics/vmaxq_s8.c | 16 +++++++- .../gcc.target/arm/mve/intrinsics/vmaxq_u16.c | 16 +++++++- .../gcc.target/arm/mve/intrinsics/vmaxq_u32.c | 16 +++++++- .../gcc.target/arm/mve/intrinsics/vmaxq_u8.c | 16 +++++++- .../arm/mve/intrinsics/vmaxq_x_s16.c | 25 +++++++++-- .../arm/mve/intrinsics/vmaxq_x_s32.c | 25 +++++++++-- .../arm/mve/intrinsics/vmaxq_x_s8.c | 25 +++++++++-- .../arm/mve/intrinsics/vmaxq_x_u16.c | 25 +++++++++-- .../arm/mve/intrinsics/vmaxq_x_u32.c | 25 +++++++++-- .../arm/mve/intrinsics/vmaxq_x_u8.c | 25 +++++++++-- .../arm/mve/intrinsics/vmaxvq_p_s16.c | 31 ++++++++++---- .../arm/mve/intrinsics/vmaxvq_p_s32.c | 31 ++++++++++---- .../arm/mve/intrinsics/vmaxvq_p_s8.c | 31 ++++++++++---- .../arm/mve/intrinsics/vmaxvq_p_u16.c | 39 +++++++++++++++--- .../arm/mve/intrinsics/vmaxvq_p_u32.c | 39 +++++++++++++++--- .../arm/mve/intrinsics/vmaxvq_p_u8.c | 39 +++++++++++++++--- .../arm/mve/intrinsics/vmaxvq_s16.c | 23 +++++++---- .../arm/mve/intrinsics/vmaxvq_s32.c | 23 +++++++---- .../gcc.target/arm/mve/intrinsics/vmaxvq_s8.c | 23 +++++++---- .../arm/mve/intrinsics/vmaxvq_u16.c | 27 +++++++++--- .../arm/mve/intrinsics/vmaxvq_u32.c | 27 +++++++++--- .../gcc.target/arm/mve/intrinsics/vmaxvq_u8.c | 27 +++++++++--- 60 files changed, 1318 insertions(+), 257 deletions(-) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c index 48d213277df..4c487ed7f60 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxat.s16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint16x8_t a, int16x8_t b, mve_pred16_t p) { return vmaxaq_m_s16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmaxat.s16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxat.s16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint16x8_t a, int16x8_t b, mve_pred16_t p) { return vmaxaq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c index 49273819861..5156467f0c1 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxat.s32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32x4_t a, int32x4_t b, mve_pred16_t p) { return vmaxaq_m_s32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmaxat.s32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxat.s32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32x4_t a, int32x4_t b, mve_pred16_t p) { return vmaxaq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c index 5ecdb2c19dc..6564bd88c9b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxat.s8 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint8x16_t a, int8x16_t b, mve_pred16_t p) { return vmaxaq_m_s8 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmaxat.s8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxat.s8 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint8x16_t a, int8x16_t b, mve_pred16_t p) { return vmaxaq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s16.c index f9a9f896aa2..6cabf9f723b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s16.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmaxa.s16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint16x8_t a, int16x8_t b) { return vmaxaq_s16 (a, b); } -/* { dg-final { scan-assembler "vmaxa.s16" } } */ +/* +**foo1: +** ... +** vmaxa.s16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint16x8_t a, int16x8_t b) { return vmaxaq (a, b); } -/* { dg-final { scan-assembler "vmaxa.s16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s32.c index efe2fc16ff7..d0dd3c23600 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s32.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmaxa.s32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32x4_t a, int32x4_t b) { return vmaxaq_s32 (a, b); } -/* { dg-final { scan-assembler "vmaxa.s32" } } */ +/* +**foo1: +** ... +** vmaxa.s32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32x4_t a, int32x4_t b) { return vmaxaq (a, b); } -/* { dg-final { scan-assembler "vmaxa.s32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s8.c index 5c2e35f71a6..a7344638dcf 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxaq_s8.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmaxa.s8 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint8x16_t a, int8x16_t b) { return vmaxaq_s8 (a, b); } -/* { dg-final { scan-assembler "vmaxa.s8" } } */ +/* +**foo1: +** ... +** vmaxa.s8 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint8x16_t a, int8x16_t b) { return vmaxaq (a, b); } -/* { dg-final { scan-assembler "vmaxa.s8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c index 74ffad4e726..ac81c8fd1bd 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint16_t foo (uint16_t a, int16x8_t b, mve_pred16_t p) { @@ -11,18 +22,36 @@ foo (uint16_t a, int16x8_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint16_t foo1 (uint16_t a, int16x8_t b, mve_pred16_t p) { return vmaxavq_p (a, b, p); } - -int16_t -foo2 (uint8_t a, int16x8_t b, mve_pred16_t p) +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ +uint16_t +foo2 (int16x8_t b, mve_pred16_t p) { - return vmaxavq_p (a, b, p); + return vmaxavq_p (1, b, p); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vmaxavt.s16" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c index 40800b0f12e..119c0c34c76 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo (uint32_t a, int32x4_t b, mve_pred16_t p) { @@ -11,18 +22,36 @@ foo (uint32_t a, int32x4_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo1 (uint32_t a, int32x4_t b, mve_pred16_t p) { return vmaxavq_p (a, b, p); } - -int32_t -foo2 (uint16_t a, int32x4_t b, mve_pred16_t p) +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ +uint32_t +foo2 (int32x4_t b, mve_pred16_t p) { - return vmaxavq_p (a, b, p); + return vmaxavq_p (1, b, p); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vmaxavt.s32" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c index 7638737fb84..dfd7f828ef6 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint8_t foo (uint8_t a, int8x16_t b, mve_pred16_t p) { @@ -11,18 +22,36 @@ foo (uint8_t a, int8x16_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint8_t foo1 (uint8_t a, int8x16_t b, mve_pred16_t p) { return vmaxavq_p (a, b, p); } - -int8_t -foo2 (uint32_t a, int8x16_t b, mve_pred16_t p) +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ +uint8_t +foo2 (int8x16_t b, mve_pred16_t p) { - return vmaxavq_p (a, b, p); + return vmaxavq_p (1, b, p); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vmaxavt.s8" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s16.c index 0dca149b3e8..9f59e8e4542 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s16.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmaxav.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint16_t foo (uint16_t a, int16x8_t b) { @@ -11,18 +18,28 @@ foo (uint16_t a, int16x8_t b) } +/* +**foo1: +** ... +** vmaxav.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint16_t foo1 (uint16_t a, int16x8_t b) { return vmaxavq (a, b); } - -int16_t -foo2 (uint8_t a, int16x8_t b) +/* +**foo2: +** ... +** vmaxav.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ +uint16_t +foo2 (int16x8_t b) { - return vmaxavq (a, b); + return vmaxavq (1, b); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vmaxav.s16" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s32.c index f419a771017..716b8a2a979 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s32.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmaxav.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo (uint32_t a, int32x4_t b) { @@ -11,18 +18,28 @@ foo (uint32_t a, int32x4_t b) } +/* +**foo1: +** ... +** vmaxav.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo1 (uint32_t a, int32x4_t b) { return vmaxavq (a, b); } - -int32_t -foo2 (uint16_t a, int32x4_t b) +/* +**foo2: +** ... +** vmaxav.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ +uint32_t +foo2 (int32x4_t b) { - return vmaxavq (a, b); + return vmaxavq (1, b); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vmaxav.s32" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s8.c index 214ad88f4aa..0f1a87af54b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxavq_s8.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmaxav.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint8_t foo (uint8_t a, int8x16_t b) { @@ -11,18 +18,28 @@ foo (uint8_t a, int8x16_t b) } +/* +**foo1: +** ... +** vmaxav.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint8_t foo1 (uint8_t a, int8x16_t b) { return vmaxavq (a, b); } - -int8_t -foo2 (uint32_t a, int8x16_t b) +/* +**foo2: +** ... +** vmaxav.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ +uint8_t +foo2 (int8x16_t b) { - return vmaxavq (a, b); + return vmaxavq (1, b); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vmaxav.s8" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c index f19707125db..cd4c813bf3b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmaxnma.f16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t a, float16x8_t b) { return vmaxnmaq_f16 (a, b); } -/* { dg-final { scan-assembler "vmaxnma.f16" } } */ +/* +**foo1: +** ... +** vmaxnma.f16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t a, float16x8_t b) { return vmaxnmaq (a, b); } -/* { dg-final { scan-assembler "vmaxnma.f16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c index 94fc3a2aa28..527466fc131 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmaxnma.f32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t a, float32x4_t b) { return vmaxnmaq_f32 (a, b); } -/* { dg-final { scan-assembler "vmaxnma.f32" } } */ +/* +**foo1: +** ... +** vmaxnma.f32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t a, float32x4_t b) { return vmaxnmaq (a, b); } -/* { dg-final { scan-assembler "vmaxnma.f32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c index b2e82f5464c..39c68cdc172 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxnmat.f16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vmaxnmaq_m_f16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmaxnmat.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxnmat.f16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vmaxnmaq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c index 8fa7344b054..f6f8bf07549 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxnmat.f32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vmaxnmaq_m_f32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmaxnmat.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxnmat.f32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vmaxnmaq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c index 6d8cf19a341..4c1f20be036 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmaxnmav.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t foo (float16_t a, float16x8_t b) { @@ -11,18 +18,28 @@ foo (float16_t a, float16x8_t b) } +/* +**foo1: +** ... +** vmaxnmav.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t foo1 (float16_t a, float16x8_t b) { return vmaxnmavq (a, b); } - +/* +**foo2: +** ... +** vmaxnmav.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t -foo2 (float32_t a, float16x8_t b) +foo2 (float16x8_t b) { - return vmaxnmavq (a, b); + return vmaxnmavq (1.1, b); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vmaxnmav.f16" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c index ef79030d8eb..86087335cea 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmaxnmav.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t foo (float32_t a, float32x4_t b) { @@ -11,18 +18,28 @@ foo (float32_t a, float32x4_t b) } +/* +**foo1: +** ... +** vmaxnmav.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t foo1 (float32_t a, float32x4_t b) { return vmaxnmavq (a, b); } - +/* +**foo2: +** ... +** vmaxnmav.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t -foo2 (float16_t a, float32x4_t b) +foo2 (float32x4_t b) { - return vmaxnmavq (a, b); + return vmaxnmavq (1.1, b); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vmaxnmav.f32" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c index f7f39f59dad..a4973567d5e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f16.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxnmavt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t foo (float16_t a, float16x8_t b, mve_pred16_t p) { @@ -11,18 +22,36 @@ foo (float16_t a, float16x8_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxnmavt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t foo1 (float16_t a, float16x8_t b, mve_pred16_t p) { return vmaxnmavq_p (a, b, p); } - +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxnmavt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t -foo2 (float32_t a, float16x8_t b, mve_pred16_t p) +foo2 (float16x8_t b, mve_pred16_t p) { - return vmaxnmavq_p (a, b, p); + return vmaxnmavq_p (1.1, b, p); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vmaxnmavt.f16" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c index 341f6254a5a..b229cb3a322 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmavq_p_f32.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxnmavt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t foo (float32_t a, float32x4_t b, mve_pred16_t p) { @@ -11,18 +22,36 @@ foo (float32_t a, float32x4_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxnmavt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t foo1 (float32_t a, float32x4_t b, mve_pred16_t p) { return vmaxnmavq_p (a, b, p); } - +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxnmavt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t -foo2 (float16_t a, float32x4_t b, mve_pred16_t p) +foo2 (float32x4_t b, mve_pred16_t p) { - return vmaxnmavq_p (a, b, p); + return vmaxnmavq_p (1.1, b, p); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vmaxnmavt.f32" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c index 59a8070e07b..faf968ebb21 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmaxnm.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t a, float16x8_t b) { return vmaxnmq_f16 (a, b); } -/* { dg-final { scan-assembler "vmaxnm.f16" } } */ +/* +**foo1: +** ... +** vmaxnm.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t a, float16x8_t b) { return vmaxnmq (a, b); } -/* { dg-final { scan-assembler "vmaxnm.f16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c index 5db42bd4b8c..f7ee01b1f14 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmaxnm.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t a, float32x4_t b) { return vmaxnmq_f32 (a, b); } -/* { dg-final { scan-assembler "vmaxnm.f32" } } */ +/* +**foo1: +** ... +** vmaxnm.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t a, float32x4_t b) { return vmaxnmq (a, b); } -/* { dg-final { scan-assembler "vmaxnm.f32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c index 4668fd03c9d..ee3444393ed 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c @@ -1,23 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxnmt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) { return vmaxnmq_m_f16 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmaxnmt.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxnmt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) { return vmaxnmq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmaxnmt.f16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c index 9e8ccbc84b7..5d434432856 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c @@ -1,23 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxnmt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) { return vmaxnmq_m_f32 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmaxnmt.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxnmt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) { return vmaxnmq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmaxnmt.f32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c index ecca6069d22..dad76734fd8 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxnmt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vmaxnmq_x_f16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmaxnmt.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxnmt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vmaxnmq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c index c3965dda4f1..2fe8c0d4f3d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxnmt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vmaxnmq_x_f32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmaxnmt.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxnmt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vmaxnmq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c index 80bd1d4cda1..9787cc1ba90 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmaxnmv.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t foo (float16_t a, float16x8_t b) { @@ -11,18 +18,28 @@ foo (float16_t a, float16x8_t b) } +/* +**foo1: +** ... +** vmaxnmv.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t foo1 (float16_t a, float16x8_t b) { return vmaxnmvq (a, b); } - +/* +**foo2: +** ... +** vmaxnmv.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t -foo2 (float32_t a, float16x8_t b) +foo2 (float16x8_t b) { - return vmaxnmvq (a, b); + return vmaxnmvq (1.1, b); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vmaxnmv.f16" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c index bb2fc46f88a..b1191876850 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmaxnmv.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t foo (float32_t a, float32x4_t b) { @@ -11,18 +18,28 @@ foo (float32_t a, float32x4_t b) } +/* +**foo1: +** ... +** vmaxnmv.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t foo1 (float32_t a, float32x4_t b) { return vmaxnmvq (a, b); } - +/* +**foo2: +** ... +** vmaxnmv.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t -foo2 (float16_t a, float32x4_t b) +foo2 (float32x4_t b) { - return vmaxnmvq (a, b); + return vmaxnmvq (1.1, b); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vmaxnmv.f32" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c index 3efe203007b..0b1740d5ed2 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxnmvt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t foo (float16_t a, float16x8_t b, mve_pred16_t p) { @@ -11,18 +22,36 @@ foo (float16_t a, float16x8_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxnmvt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t foo1 (float16_t a, float16x8_t b, mve_pred16_t p) { return vmaxnmvq_p (a, b, p); } - +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxnmvt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t -foo2 (float32_t a, float16x8_t b, mve_pred16_t p) +foo2 (float16x8_t b, mve_pred16_t p) { - return vmaxnmvq_p (a, b, p); + return vmaxnmvq_p (1.1, b, p); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vmaxnmvt.f16" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c index 6c13247f1f1..ca6ad91d24d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxnmvt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t foo (float32_t a, float32x4_t b, mve_pred16_t p) { @@ -11,18 +22,36 @@ foo (float32_t a, float32x4_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxnmvt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t foo1 (float32_t a, float32x4_t b, mve_pred16_t p) { return vmaxnmvq_p (a, b, p); } - +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxnmvt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t -foo2 (float16_t a, float32x4_t b, mve_pred16_t p) +foo2 (float32x4_t b, mve_pred16_t p) { - return vmaxnmvq_p (a, b, p); + return vmaxnmvq_p (1.1, b, p); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vmaxnmvt.f32" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c index 2791ed4c562..548824fc58a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c @@ -1,23 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) { return vmaxq_m_s16 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmaxt.s16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) { return vmaxq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmaxt.s16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c index 27f7d5d7b16..e935729b47d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c @@ -1,23 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) { return vmaxq_m_s32 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmaxt.s32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) { return vmaxq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmaxt.s32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c index 23b7569f720..8028fa031c7 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c @@ -1,23 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) { return vmaxq_m_s8 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmaxt.s8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) { return vmaxq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmaxt.s8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c index 61e51e3b830..e872f9e72f8 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c @@ -1,23 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) { return vmaxq_m_u16 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmaxt.u16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) { return vmaxq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmaxt.u16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c index 23df7eeaed6..76606555881 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c @@ -1,23 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) { return vmaxq_m_u32 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmaxt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) { return vmaxq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmaxt.u32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c index 138d5c87894..7ade467cafd 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c @@ -1,23 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) { return vmaxq_m_u8 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmaxt.u8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) { return vmaxq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmaxt.u8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s16.c index a42fc82a852..bf547a2420d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s16.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmax.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo (int16x8_t a, int16x8_t b) { return vmaxq_s16 (a, b); } -/* { dg-final { scan-assembler "vmax.s16" } } */ +/* +**foo1: +** ... +** vmax.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo1 (int16x8_t a, int16x8_t b) { return vmaxq (a, b); } -/* { dg-final { scan-assembler "vmax.s16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s32.c index 14c094a5d11..25bb950c0bf 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s32.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmax.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo (int32x4_t a, int32x4_t b) { return vmaxq_s32 (a, b); } -/* { dg-final { scan-assembler "vmax.s32" } } */ +/* +**foo1: +** ... +** vmax.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo1 (int32x4_t a, int32x4_t b) { return vmaxq (a, b); } -/* { dg-final { scan-assembler "vmax.s32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s8.c index 0540a27bae9..33057f1a58e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_s8.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmax.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo (int8x16_t a, int8x16_t b) { return vmaxq_s8 (a, b); } -/* { dg-final { scan-assembler "vmax.s8" } } */ +/* +**foo1: +** ... +** vmax.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo1 (int8x16_t a, int8x16_t b) { return vmaxq (a, b); } -/* { dg-final { scan-assembler "vmax.s8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u16.c index 6b9b5a73bcd..7717a9a5057 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u16.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmax.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint16x8_t a, uint16x8_t b) { return vmaxq_u16 (a, b); } -/* { dg-final { scan-assembler "vmax.u16" } } */ +/* +**foo1: +** ... +** vmax.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint16x8_t a, uint16x8_t b) { return vmaxq (a, b); } -/* { dg-final { scan-assembler "vmax.u16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u32.c index 3112302bf1a..36b5c276cfe 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u32.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmax.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32x4_t a, uint32x4_t b) { return vmaxq_u32 (a, b); } -/* { dg-final { scan-assembler "vmax.u32" } } */ +/* +**foo1: +** ... +** vmax.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32x4_t a, uint32x4_t b) { return vmaxq (a, b); } -/* { dg-final { scan-assembler "vmax.u32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u8.c index b1baa5083bd..e643e5f3e3c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_u8.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmax.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint8x16_t a, uint8x16_t b) { return vmaxq_u8 (a, b); } -/* { dg-final { scan-assembler "vmax.u8" } } */ +/* +**foo1: +** ... +** vmax.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint8x16_t a, uint8x16_t b) { return vmaxq (a, b); } -/* { dg-final { scan-assembler "vmax.u8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c index 9d92f2ccd85..a32feb0d7cd 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo (int16x8_t a, int16x8_t b, mve_pred16_t p) { return vmaxq_x_s16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmaxt.s16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) { return vmaxq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c index 200fd4b1bb1..3ac1994c4f8 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo (int32x4_t a, int32x4_t b, mve_pred16_t p) { return vmaxq_x_s32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmaxt.s32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) { return vmaxq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c index 2fe752558b9..c9ba33d1504 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo (int8x16_t a, int8x16_t b, mve_pred16_t p) { return vmaxq_x_s8 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmaxt.s8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) { return vmaxq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c index 967622e331c..954a9e2f02a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) { return vmaxq_x_u16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmaxt.u16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) { return vmaxq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c index 56b5d8fa8b8..022d418af84 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) { return vmaxq_x_u32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmaxt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) { return vmaxq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c index 1816f959dd7..7e1687a8b72 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) { return vmaxq_x_u8 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmaxt.u8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) { return vmaxq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c index 657efc51bea..a97703eb58c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxvt.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int16_t foo (int16_t a, int16x8_t b, mve_pred16_t p) { @@ -11,18 +22,20 @@ foo (int16_t a, int16x8_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxvt.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int16_t foo1 (int16_t a, int16x8_t b, mve_pred16_t p) { return vmaxvq_p (a, b, p); } - -int16_t -foo2 (int8_t a, int16x8_t b, mve_pred16_t p) -{ - return vmaxvq_p (a, b, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vmaxvt.s16" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c index 5882351c0fa..b4bddcb8312 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxvt.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int32_t foo (int32_t a, int32x4_t b, mve_pred16_t p) { @@ -11,18 +22,20 @@ foo (int32_t a, int32x4_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxvt.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int32_t foo1 (int32_t a, int32x4_t b, mve_pred16_t p) { return vmaxvq_p (a, b, p); } - -int32_t -foo2 (int16_t a, int32x4_t b, mve_pred16_t p) -{ - return vmaxvq_p (a, b, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vmaxvt.s32" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c index 3737ecd3307..ee8c3e9155f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxvt.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int8_t foo (int8_t a, int8x16_t b, mve_pred16_t p) { @@ -11,18 +22,20 @@ foo (int8_t a, int8x16_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxvt.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int8_t foo1 (int8_t a, int8x16_t b, mve_pred16_t p) { return vmaxvq_p (a, b, p); } - -int8_t -foo2 (int32_t a, int8x16_t b, mve_pred16_t p) -{ - return vmaxvq_p (a, b, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vmaxvt.s8" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c index 348cf39caa0..906adf85936 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxvt.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint16_t foo (uint16_t a, uint16x8_t b, mve_pred16_t p) { @@ -11,18 +22,36 @@ foo (uint16_t a, uint16x8_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxvt.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint16_t foo1 (uint16_t a, uint16x8_t b, mve_pred16_t p) { return vmaxvq_p (a, b, p); } - +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxvt.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint16_t -foo2 (uint32_t a, uint16x8_t b, mve_pred16_t p) +foo2 (uint16x8_t b, mve_pred16_t p) { - return vmaxvq_p (a, b, p); + return vmaxvq_p (1, b, p); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vmaxvt.u16" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c index f2e976216c5..acc5367c5a2 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxvt.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo (uint32_t a, uint32x4_t b, mve_pred16_t p) { @@ -11,18 +22,36 @@ foo (uint32_t a, uint32x4_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxvt.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo1 (uint32_t a, uint32x4_t b, mve_pred16_t p) { return vmaxvq_p (a, b, p); } - +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxvt.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint32_t -foo2 (uint8_t a, uint32x4_t b, mve_pred16_t p) +foo2 (uint32x4_t b, mve_pred16_t p) { - return vmaxvq_p (a, b, p); + return vmaxvq_p (1, b, p); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vmaxvt.u32" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c index 7df5b63c9bc..358cb40f829 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxvt.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint8_t foo (uint8_t a, uint8x16_t b, mve_pred16_t p) { @@ -11,18 +22,36 @@ foo (uint8_t a, uint8x16_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxvt.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint8_t foo1 (uint8_t a, uint8x16_t b, mve_pred16_t p) { return vmaxvq_p (a, b, p); } - +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmaxvt.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint8_t -foo2 (uint16_t a, uint8x16_t b, mve_pred16_t p) +foo2 (uint8x16_t b, mve_pred16_t p) { - return vmaxvq_p (a, b, p); + return vmaxvq_p (1, b, p); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vmaxvt.u8" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s16.c index 8412452cf33..485355a7d72 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s16.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmaxv.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int16_t foo (int16_t a, int16x8_t b) { @@ -11,18 +18,16 @@ foo (int16_t a, int16x8_t b) } +/* +**foo1: +** ... +** vmaxv.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int16_t foo1 (int16_t a, int16x8_t b) { return vmaxvq (a, b); } - -int16_t -foo2 (int8_t a, int16x8_t b) -{ - return vmaxvq (a, b); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vmaxv.s16" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s32.c index 09f4909c9a8..3b9075689a0 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s32.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmaxv.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int32_t foo (int32_t a, int32x4_t b) { @@ -11,18 +18,16 @@ foo (int32_t a, int32x4_t b) } +/* +**foo1: +** ... +** vmaxv.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int32_t foo1 (int32_t a, int32x4_t b) { return vmaxvq (a, b); } - -int32_t -foo2 (int16_t a, int32x4_t b) -{ - return vmaxvq (a, b); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vmaxv.s32" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s8.c index a087bbc6b64..f13a0168d9d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_s8.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmaxv.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int8_t foo (int8_t a, int8x16_t b) { @@ -11,18 +18,16 @@ foo (int8_t a, int8x16_t b) } +/* +**foo1: +** ... +** vmaxv.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int8_t foo1 (int8_t a, int8x16_t b) { return vmaxvq (a, b); } - -int8_t -foo2 (int32_t a, int8x16_t b) -{ - return vmaxvq (a, b); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vmaxv.s8" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u16.c index 47fe0d1cf0f..6a0fe254043 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u16.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmaxv.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint16_t foo (uint16_t a, uint16x8_t b) { @@ -11,18 +18,28 @@ foo (uint16_t a, uint16x8_t b) } +/* +**foo1: +** ... +** vmaxv.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint16_t foo1 (uint16_t a, uint16x8_t b) { return vmaxvq (a, b); } - +/* +**foo2: +** ... +** vmaxv.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint16_t -foo2 (uint32_t a, uint16x8_t b) +foo2 (uint16x8_t b) { - return vmaxvq (a, b); + return vmaxvq (1, b); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vmaxv.u16" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u32.c index aa723daf5dd..eed20046e53 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u32.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmaxv.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo (uint32_t a, uint32x4_t b) { @@ -11,18 +18,28 @@ foo (uint32_t a, uint32x4_t b) } +/* +**foo1: +** ... +** vmaxv.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo1 (uint32_t a, uint32x4_t b) { return vmaxvq (a, b); } - +/* +**foo2: +** ... +** vmaxv.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint32_t -foo2 (uint8_t a, uint32x4_t b) +foo2 (uint32x4_t b) { - return vmaxvq (a, b); + return vmaxvq (1, b); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vmaxv.u32" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u8.c index 3aae785040c..d44a6d3bb02 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxvq_u8.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmaxv.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint8_t foo (uint8_t a, uint8x16_t b) { @@ -11,18 +18,28 @@ foo (uint8_t a, uint8x16_t b) } +/* +**foo1: +** ... +** vmaxv.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint8_t foo1 (uint8_t a, uint8x16_t b) { return vmaxvq (a, b); } - +/* +**foo2: +** ... +** vmaxv.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint8_t -foo2 (uint16_t a, uint8x16_t b) +foo2 (uint8x16_t b) { - return vmaxvq (a, b); + return vmaxvq (1, b); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vmaxv.u8" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file From patchwork Thu Nov 17 16:37:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Corallo X-Patchwork-Id: 60756 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost 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gcc.target/arm/mve/intrinsics/vabavq_p_s16.c: * gcc.target/arm/mve/intrinsics/vabavq_p_s32.c: * gcc.target/arm/mve/intrinsics/vabavq_p_s8.c: * gcc.target/arm/mve/intrinsics/vabavq_p_u16.c: * gcc.target/arm/mve/intrinsics/vabavq_p_u32.c: * gcc.target/arm/mve/intrinsics/vabavq_p_u8.c: * gcc.target/arm/mve/intrinsics/vabavq_s16.c: * gcc.target/arm/mve/intrinsics/vabavq_s32.c: * gcc.target/arm/mve/intrinsics/vabavq_s8.c: * gcc.target/arm/mve/intrinsics/vabavq_u16.c: * gcc.target/arm/mve/intrinsics/vabavq_u32.c: * gcc.target/arm/mve/intrinsics/vabavq_u8.c: --- .../arm/mve/intrinsics/vabavq_p_s16.c | 40 ++++++++++++++++++- .../arm/mve/intrinsics/vabavq_p_s32.c | 40 ++++++++++++++++++- .../arm/mve/intrinsics/vabavq_p_s8.c | 40 ++++++++++++++++++- .../arm/mve/intrinsics/vabavq_p_u16.c | 40 ++++++++++++++++++- .../arm/mve/intrinsics/vabavq_p_u32.c | 40 ++++++++++++++++++- .../arm/mve/intrinsics/vabavq_p_u8.c | 40 ++++++++++++++++++- .../arm/mve/intrinsics/vabavq_s16.c | 28 ++++++++++++- .../arm/mve/intrinsics/vabavq_s32.c | 28 ++++++++++++- .../gcc.target/arm/mve/intrinsics/vabavq_s8.c | 28 ++++++++++++- .../arm/mve/intrinsics/vabavq_u16.c | 28 ++++++++++++- .../arm/mve/intrinsics/vabavq_u32.c | 28 ++++++++++++- .../gcc.target/arm/mve/intrinsics/vabavq_u8.c | 28 ++++++++++++- 12 files changed, 384 insertions(+), 24 deletions(-) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s16.c index 78ac801fa3c..843d022c418 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s16.c @@ -1,21 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo (uint32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) { return vabavq_p_s16 (a, b, c, p); } -/* { dg-final { scan-assembler "vabavt.s16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo1 (uint32_t a, int16x8_t b, int16x8_t c, mve_pred16_t p) { return vabavq_p (a, b, c, p); } -/* { dg-final { scan-assembler "vabavt.s16" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ +uint32_t +foo2 (int16x8_t b, int16x8_t c, mve_pred16_t p) +{ + return vabavq_p (1, b, c, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s32.c index af4e30b6127..6ed9b9ac1c4 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s32.c @@ -1,21 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo (uint32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) { return vabavq_p_s32 (a, b, c, p); } -/* { dg-final { scan-assembler "vabavt.s32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo1 (uint32_t a, int32x4_t b, int32x4_t c, mve_pred16_t p) { return vabavq_p (a, b, c, p); } -/* { dg-final { scan-assembler "vabavt.s32" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ +uint32_t +foo2 (int32x4_t b, int32x4_t c, mve_pred16_t p) +{ + return vabavq_p (1, b, c, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s8.c index a76b6bd4bda..ec34be92a28 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_s8.c @@ -1,21 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo (uint32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p) { return vabavq_p_s8 (a, b, c, p); } -/* { dg-final { scan-assembler "vabavt.s8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo1 (uint32_t a, int8x16_t b, int8x16_t c, mve_pred16_t p) { return vabavq_p (a, b, c, p); } -/* { dg-final { scan-assembler "vabavt.s8" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ +uint32_t +foo2 (int8x16_t b, int8x16_t c, mve_pred16_t p) +{ + return vabavq_p (1, b, c, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u16.c index 9627a00b812..440b603a18e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u16.c @@ -1,21 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabavt.u16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo (uint32_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p) { return vabavq_p_u16 (a, b, c, p); } -/* { dg-final { scan-assembler "vabavt.u16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabavt.u16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo1 (uint32_t a, uint16x8_t b, uint16x8_t c, mve_pred16_t p) { return vabavq_p (a, b, c, p); } -/* { dg-final { scan-assembler "vabavt.u16" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabavt.u16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ +uint32_t +foo2 (uint16x8_t b, uint16x8_t c, mve_pred16_t p) +{ + return vabavq_p (1, b, c, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u32.c index 298c2c38101..9500ee054b1 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u32.c @@ -1,21 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabavt.u32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo (uint32_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p) { return vabavq_p_u32 (a, b, c, p); } -/* { dg-final { scan-assembler "vabavt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabavt.u32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo1 (uint32_t a, uint32x4_t b, uint32x4_t c, mve_pred16_t p) { return vabavq_p (a, b, c, p); } -/* { dg-final { scan-assembler "vabavt.u32" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabavt.u32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ +uint32_t +foo2 (uint32x4_t b, uint32x4_t c, mve_pred16_t p) +{ + return vabavq_p (1, b, c, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u8.c index 775072225f8..40c9a51fbe4 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_p_u8.c @@ -1,21 +1,57 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabavt.u8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo (uint32_t a, uint8x16_t b, uint8x16_t c, mve_pred16_t p) { return vabavq_p_u8 (a, b, c, p); } -/* { dg-final { scan-assembler "vabavt.u8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabavt.u8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo1 (uint32_t a, uint8x16_t b, uint8x16_t c, mve_pred16_t p) { return vabavq_p (a, b, c, p); } -/* { dg-final { scan-assembler "vabavt.u8" } } */ +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabavt.u8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ +uint32_t +foo2 (uint8x16_t b, uint8x16_t c, mve_pred16_t p) +{ + return vabavq_p (1, b, c, p); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s16.c index c2383f1865b..27684fa4a88 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s16.c @@ -1,21 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vabav.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo (uint32_t a, int16x8_t b, int16x8_t c) { return vabavq_s16 (a, b, c); } -/* { dg-final { scan-assembler "vabav.s16" } } */ +/* +**foo1: +** ... +** vabav.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo1 (uint32_t a, int16x8_t b, int16x8_t c) { return vabavq (a, b, c); } -/* { dg-final { scan-assembler "vabav.s16" } } */ +/* +**foo2: +** ... +** vabav.s16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ +uint32_t +foo2 (int16x8_t b, int16x8_t c) +{ + return vabavq (1, b, c); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s32.c index 7170d013c3b..f595609a2a0 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s32.c @@ -1,21 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vabav.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo (uint32_t a, int32x4_t b, int32x4_t c) { return vabavq_s32 (a, b, c); } -/* { dg-final { scan-assembler "vabav.s32" } } */ +/* +**foo1: +** ... +** vabav.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo1 (uint32_t a, int32x4_t b, int32x4_t c) { return vabavq (a, b, c); } -/* { dg-final { scan-assembler "vabav.s32" } } */ +/* +**foo2: +** ... +** vabav.s32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ +uint32_t +foo2 (int32x4_t b, int32x4_t c) +{ + return vabavq (1, b, c); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s8.c index d75ecdbdbdf..60fa9e23b7b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_s8.c @@ -1,21 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vabav.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo (uint32_t a, int8x16_t b, int8x16_t c) { return vabavq_s8 (a, b, c); } -/* { dg-final { scan-assembler "vabav.s8" } } */ +/* +**foo1: +** ... +** vabav.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo1 (uint32_t a, int8x16_t b, int8x16_t c) { return vabavq (a, b, c); } -/* { dg-final { scan-assembler "vabav.s8" } } */ +/* +**foo2: +** ... +** vabav.s8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ +uint32_t +foo2 (int8x16_t b, int8x16_t c) +{ + return vabavq (1, b, c); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u16.c index 40ab94d9083..f3255276eda 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u16.c @@ -1,21 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vabav.u16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo (uint32_t a, uint16x8_t b, uint16x8_t c) { return vabavq_u16 (a, b, c); } -/* { dg-final { scan-assembler "vabav.u16" } } */ +/* +**foo1: +** ... +** vabav.u16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo1 (uint32_t a, uint16x8_t b, uint16x8_t c) { return vabavq (a, b, c); } -/* { dg-final { scan-assembler "vabav.u16" } } */ +/* +**foo2: +** ... +** vabav.u16 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ +uint32_t +foo2 (uint16x8_t b, uint16x8_t c) +{ + return vabavq (1, b, c); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u32.c index 4b9f5c32f3d..f41fa1f3952 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u32.c @@ -1,21 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vabav.u32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo (uint32_t a, uint32x4_t b, uint32x4_t c) { return vabavq_u32 (a, b, c); } -/* { dg-final { scan-assembler "vabav.u32" } } */ +/* +**foo1: +** ... +** vabav.u32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo1 (uint32_t a, uint32x4_t b, uint32x4_t c) { return vabavq (a, b, c); } -/* { dg-final { scan-assembler "vabav.u32" } } */ +/* +**foo2: +** ... +** vabav.u32 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ +uint32_t +foo2 (uint32x4_t b, uint32x4_t c) +{ + return vabavq (1, b, c); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u8.c index 3638e9d7106..3a2654435df 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabavq_u8.c @@ -1,21 +1,45 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vabav.u8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo (uint32_t a, uint8x16_t b, uint8x16_t c) { return vabavq_u8 (a, b, c); } -/* { dg-final { scan-assembler "vabav.u8" } } */ +/* +**foo1: +** ... +** vabav.u8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo1 (uint32_t a, uint8x16_t b, uint8x16_t c) { return vabavq (a, b, c); } -/* { dg-final { scan-assembler "vabav.u8" } } */ +/* +**foo2: +** ... +** vabav.u8 (?:ip|fp|r[0-9]+), q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ +uint32_t +foo2 (uint8x16_t b, uint8x16_t c) +{ + return vabavq (1, b, c); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file From 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DBAEUR03FT012.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAVPR08MB9818 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andrea Corallo via Gcc-patches From: Andrea Corallo Reply-To: Andrea Corallo Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vabdq_f16.c: Improve test. * gcc.target/arm/mve/intrinsics/vabdq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabdq_x_u8.c: Likewise. --- .../gcc.target/arm/mve/intrinsics/vabdq_f16.c | 16 ++++++++++-- .../gcc.target/arm/mve/intrinsics/vabdq_f32.c | 16 ++++++++++-- .../arm/mve/intrinsics/vabdq_m_f16.c | 26 ++++++++++++++++--- .../arm/mve/intrinsics/vabdq_m_f32.c | 26 ++++++++++++++++--- .../arm/mve/intrinsics/vabdq_m_s16.c | 26 ++++++++++++++++--- .../arm/mve/intrinsics/vabdq_m_s32.c | 26 ++++++++++++++++--- .../arm/mve/intrinsics/vabdq_m_s8.c | 26 ++++++++++++++++--- .../arm/mve/intrinsics/vabdq_m_u16.c | 26 ++++++++++++++++--- .../arm/mve/intrinsics/vabdq_m_u32.c | 26 ++++++++++++++++--- .../arm/mve/intrinsics/vabdq_m_u8.c | 26 ++++++++++++++++--- .../gcc.target/arm/mve/intrinsics/vabdq_s16.c | 16 ++++++++++-- .../gcc.target/arm/mve/intrinsics/vabdq_s32.c | 16 ++++++++++-- .../gcc.target/arm/mve/intrinsics/vabdq_s8.c | 16 ++++++++++-- .../gcc.target/arm/mve/intrinsics/vabdq_u16.c | 16 ++++++++++-- .../gcc.target/arm/mve/intrinsics/vabdq_u32.c | 16 ++++++++++-- .../gcc.target/arm/mve/intrinsics/vabdq_u8.c | 16 ++++++++++-- .../arm/mve/intrinsics/vabdq_x_f16.c | 25 +++++++++++++++--- .../arm/mve/intrinsics/vabdq_x_f32.c | 25 +++++++++++++++--- .../arm/mve/intrinsics/vabdq_x_s16.c | 26 ++++++++++++++++--- .../arm/mve/intrinsics/vabdq_x_s32.c | 25 +++++++++++++++--- .../arm/mve/intrinsics/vabdq_x_s8.c | 25 +++++++++++++++--- .../arm/mve/intrinsics/vabdq_x_u16.c | 25 +++++++++++++++--- .../arm/mve/intrinsics/vabdq_x_u32.c | 25 +++++++++++++++--- .../arm/mve/intrinsics/vabdq_x_u8.c | 25 +++++++++++++++--- 24 files changed, 464 insertions(+), 73 deletions(-) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f16.c index b55e826e4b6..f379b25c49e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f16.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vabd.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t a, float16x8_t b) { return vabdq_f16 (a, b); } -/* { dg-final { scan-assembler "vabd.f16" } } */ +/* +**foo1: +** ... +** vabd.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t a, float16x8_t b) { return vabdq (a, b); } -/* { dg-final { scan-assembler "vabd.f16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f32.c index f1a95b14e03..3ba808e0b4d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_f32.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vabd.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t a, float32x4_t b) { return vabdq_f32 (a, b); } -/* { dg-final { scan-assembler "vabd.f32" } } */ +/* +**foo1: +** ... +** vabd.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t a, float32x4_t b) { return vabdq (a, b); } -/* { dg-final { scan-assembler "vabd.f32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f16.c index f92e671edec..903c6dfe861 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f16.c @@ -1,23 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabdt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) { return vabdq_m_f16 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabdt.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabdt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) { return vabdq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabdt.f16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f32.c index 5e30997c997..4ddf4ee5c61 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_f32.c @@ -1,23 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabdt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) { return vabdq_m_f32 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabdt.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabdt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) { return vabdq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabdt.f32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s16.c index 35809895dea..c719a0b5e9c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s16.c @@ -1,23 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabdt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) { return vabdq_m_s16 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabdt.s16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabdt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) { return vabdq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabdt.s16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s32.c index 77d97e1db63..048554144cd 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s32.c @@ -1,23 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabdt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) { return vabdq_m_s32 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabdt.s32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabdt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) { return vabdq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabdt.s32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s8.c index a0004d9f290..458b920b5cb 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_s8.c @@ -1,23 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabdt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) { return vabdq_m_s8 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabdt.s8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabdt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) { return vabdq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabdt.s8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u16.c index c4dc9a469da..8e163edb153 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u16.c @@ -1,23 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabdt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) { return vabdq_m_u16 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabdt.u16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabdt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) { return vabdq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabdt.u16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u32.c index 18a64d3a19d..619d4706dc5 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u32.c @@ -1,23 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabdt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) { return vabdq_m_u32 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabdt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabdt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) { return vabdq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabdt.u32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u8.c index 494f39cb857..079478df08a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_m_u8.c @@ -1,23 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabdt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) { return vabdq_m_u8 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabdt.u8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabdt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) { return vabdq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabdt.u8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s16.c index 73773ac9ebc..0dce4c482ac 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s16.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vabd.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo (int16x8_t a, int16x8_t b) { return vabdq_s16 (a, b); } -/* { dg-final { scan-assembler "vabd.s16" } } */ +/* +**foo1: +** ... +** vabd.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo1 (int16x8_t a, int16x8_t b) { return vabdq (a, b); } -/* { dg-final { scan-assembler "vabd.s16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s32.c index 3c552a2969e..f5908fe81d8 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s32.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vabd.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo (int32x4_t a, int32x4_t b) { return vabdq_s32 (a, b); } -/* { dg-final { scan-assembler "vabd.s32" } } */ +/* +**foo1: +** ... +** vabd.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo1 (int32x4_t a, int32x4_t b) { return vabdq (a, b); } -/* { dg-final { scan-assembler "vabd.s32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s8.c index f7de6f707ac..3f249e1a622 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_s8.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vabd.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo (int8x16_t a, int8x16_t b) { return vabdq_s8 (a, b); } -/* { dg-final { scan-assembler "vabd.s8" } } */ +/* +**foo1: +** ... +** vabd.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo1 (int8x16_t a, int8x16_t b) { return vabdq (a, b); } -/* { dg-final { scan-assembler "vabd.s8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u16.c index 90d1c873cca..16a4b930d2c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u16.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vabd.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint16x8_t a, uint16x8_t b) { return vabdq_u16 (a, b); } -/* { dg-final { scan-assembler "vabd.u16" } } */ +/* +**foo1: +** ... +** vabd.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint16x8_t a, uint16x8_t b) { return vabdq (a, b); } -/* { dg-final { scan-assembler "vabd.u16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u32.c index 405dca51466..2b5ee12945c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u32.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vabd.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32x4_t a, uint32x4_t b) { return vabdq_u32 (a, b); } -/* { dg-final { scan-assembler "vabd.u32" } } */ +/* +**foo1: +** ... +** vabd.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32x4_t a, uint32x4_t b) { return vabdq (a, b); } -/* { dg-final { scan-assembler "vabd.u32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u8.c index 2b693c16520..50a4c162c9b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_u8.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vabd.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint8x16_t a, uint8x16_t b) { return vabdq_u8 (a, b); } -/* { dg-final { scan-assembler "vabd.u8" } } */ +/* +**foo1: +** ... +** vabd.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint8x16_t a, uint8x16_t b) { return vabdq (a, b); } -/* { dg-final { scan-assembler "vabd.u8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f16.c index 9d771a3325f..da142f4394b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f16.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabdt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vabdq_x_f16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabdt.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabdt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vabdq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f32.c index 498851348d5..1ff1bef258f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f32.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabdt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vabdq_x_f32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabdt.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabdt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vabdq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s16.c index 1fa77cc5cae..6733e2bcc14 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s16.c @@ -1,23 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabdt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo (int16x8_t a, int16x8_t b, mve_pred16_t p) { return vabdq_x_s16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabdt.s16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabdt.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) { return vabdq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabdt.s16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s32.c index 24a62702482..8d7631b9ac6 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s32.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabdt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo (int32x4_t a, int32x4_t b, mve_pred16_t p) { return vabdq_x_s32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabdt.s32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabdt.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) { return vabdq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s8.c index f96c2dfd147..90784c1d389 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s8.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabdt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo (int8x16_t a, int8x16_t b, mve_pred16_t p) { return vabdq_x_s8 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabdt.s8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabdt.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) { return vabdq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u16.c index 820b8416330..f376374564a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u16.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabdt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) { return vabdq_x_u16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabdt.u16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabdt.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) { return vabdq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u32.c index 2d81930348a..d9467a1ccd7 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u32.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabdt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) { return vabdq_x_u32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabdt.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabdt.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) { return vabdq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u8.c index 7f956850b52..1ea3713d12b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u8.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabdt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) { return vabdq_x_u8 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabdt.u8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabdt.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) { return vabdq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file From patchwork Thu Nov 17 16:37:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Corallo X-Patchwork-Id: 60761 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id AAE543902F01 for ; Thu, 17 Nov 2022 16:41:53 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org AAE543902F01 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1668703313; bh=Rv1vzaFaVC1bFnIPLnGcYltXMvaS6Ov1TENf/lA9HuM=; h=To:CC:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=tSUOSbNCHVUZW6ygtExkryOTEwV4kdx3UCr06OKHDBHRJdNUaA3OOCG9zDKBqN/BT 7Fo+a+bOsyWp7C1oYc8nwUYSgeZRl1V4P6Pf6LP/LT0ZTg0If51CdApP5nhBHUQNJ1 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VI1EUR03FT064.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAVPR08MB9841 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andrea Corallo via Gcc-patches From: Andrea Corallo Reply-To: Andrea Corallo Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" gcc/ChangeLog: * config/arm/mve.md (mve_vabsq_f): Fix spacing. gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vabsq_f16.c: Improve test. * gcc.target/arm/mve/intrinsics/vabsq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vabsq_x_s8.c: Likewise. --- gcc/config/arm/mve.md | 2 +- .../gcc.target/arm/mve/intrinsics/vabsq_f16.c | 22 +++++++++++++++- .../gcc.target/arm/mve/intrinsics/vabsq_f32.c | 22 +++++++++++++++- .../arm/mve/intrinsics/vabsq_m_f16.c | 25 ++++++++++++++++--- .../arm/mve/intrinsics/vabsq_m_f32.c | 25 ++++++++++++++++--- .../arm/mve/intrinsics/vabsq_m_s16.c | 25 ++++++++++++++++--- .../arm/mve/intrinsics/vabsq_m_s32.c | 25 ++++++++++++++++--- .../arm/mve/intrinsics/vabsq_m_s8.c | 25 ++++++++++++++++--- .../gcc.target/arm/mve/intrinsics/vabsq_s16.c | 20 ++++++++++++--- .../gcc.target/arm/mve/intrinsics/vabsq_s32.c | 20 ++++++++++++--- .../gcc.target/arm/mve/intrinsics/vabsq_s8.c | 16 ++++++++++-- .../arm/mve/intrinsics/vabsq_x_f16.c | 25 ++++++++++++++++--- .../arm/mve/intrinsics/vabsq_x_f32.c | 25 ++++++++++++++++--- .../arm/mve/intrinsics/vabsq_x_s16.c | 25 ++++++++++++++++--- .../arm/mve/intrinsics/vabsq_x_s32.c | 25 ++++++++++++++++--- .../arm/mve/intrinsics/vabsq_x_s8.c | 25 ++++++++++++++++--- 16 files changed, 309 insertions(+), 43 deletions(-) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 3330a220aea..bc4e2f2ac21 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -279,7 +279,7 @@ (define_insn "mve_vabsq_f" (abs:MVE_0 (match_operand:MVE_0 1 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vabs.f%# %q0, %q1" + "vabs.f%#\t%q0, %q1" [(set_attr "type" "mve_move") ]) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c index 08e141baedc..f29ada8c058 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f16.c @@ -1,13 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vabs.f16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t a) { return vabsq_f16 (a); } -/* { dg-final { scan-assembler "vabs.f16" } } */ + +/* +**foo1: +** ... +** vabs.f16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ +float16x8_t +foo1 (float16x8_t a) +{ + return vabsq (a); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c index 3614a44fbdc..cc24744fb26 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_f32.c @@ -1,13 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vabs.f32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t a) { return vabsq_f32 (a); } -/* { dg-final { scan-assembler "vabs.f32" } } */ + +/* +**foo1: +** ... +** vabs.f32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ +float32x4_t +foo1 (float32x4_t a) +{ + return vabsq (a); +} + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f16.c index 30c14a151af..21cf284d045 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f16.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabst.f16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t inactive, float16x8_t a, mve_pred16_t p) { return vabsq_m_f16 (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabst.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabst.f16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t inactive, float16x8_t a, mve_pred16_t p) { return vabsq_m (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f32.c index 652056aa98c..236830b3a9e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_f32.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabst.f32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t inactive, float32x4_t a, mve_pred16_t p) { return vabsq_m_f32 (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabst.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabst.f32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t inactive, float32x4_t a, mve_pred16_t p) { return vabsq_m (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s16.c index 2dcf488bd0d..22f7b37b30b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s16.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabst.s16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo (int16x8_t inactive, int16x8_t a, mve_pred16_t p) { return vabsq_m_s16 (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabst.s16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabst.s16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo1 (int16x8_t inactive, int16x8_t a, mve_pred16_t p) { return vabsq_m (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s32.c index 183909fef93..b3021edf52b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s32.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabst.s32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo (int32x4_t inactive, int32x4_t a, mve_pred16_t p) { return vabsq_m_s32 (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabst.s32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabst.s32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo1 (int32x4_t inactive, int32x4_t a, mve_pred16_t p) { return vabsq_m (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s8.c index cd17974838e..da9ff2f978a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_m_s8.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabst.s8 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo (int8x16_t inactive, int8x16_t a, mve_pred16_t p) { return vabsq_m_s8 (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabst.s8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabst.s8 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo1 (int8x16_t inactive, int8x16_t a, mve_pred16_t p) { return vabsq_m (inactive, a, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c index 243afebc38c..84906302c8a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s16.c @@ -1,21 +1,33 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vabs.s16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo (int16x8_t a) { return vabsq_s16 (a); } -/* { dg-final { scan-assembler "vabs.s16" } } */ +/* +**foo1: +** ... +** vabs.s16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo1 (int16x8_t a) { return vabsq (a); } -/* { dg-final { scan-assembler "vabs.s16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c index d9843503a48..117c787d595 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s32.c @@ -1,21 +1,33 @@ -/* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ -/* { dg-add-options arm_v8_1m_mve_fp } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vabs.s32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo (int32x4_t a) { return vabsq_s32 (a); } -/* { dg-final { scan-assembler "vabs.s32" } } */ +/* +**foo1: +** ... +** vabs.s32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo1 (int32x4_t a) { return vabsq (a); } -/* { dg-final { scan-assembler "vabs.s32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c index 93bf1520dd3..a7f1413505c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_s8.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vabs.s8 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo (int8x16_t a) { return vabsq_s8 (a); } -/* { dg-final { scan-assembler "vabs.s8" } } */ +/* +**foo1: +** ... +** vabs.s8 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo1 (int8x16_t a) { return vabsq (a); } -/* { dg-final { scan-assembler "vabs.s8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f16.c index d1fc7002ccb..f24a8cccb53 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f16.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabst.f16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t a, mve_pred16_t p) { return vabsq_x_f16 (a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabst.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabst.f16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t a, mve_pred16_t p) { return vabsq_x (a, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f32.c index 0beccac030d..fd4c2277969 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f32.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabst.f32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t a, mve_pred16_t p) { return vabsq_x_f32 (a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabst.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabst.f32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t a, mve_pred16_t p) { return vabsq_x (a, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s16.c index fd67fd5ccac..0e1d1bb94d4 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s16.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabst.s16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo (int16x8_t a, mve_pred16_t p) { return vabsq_x_s16 (a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabst.s16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabst.s16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo1 (int16x8_t a, mve_pred16_t p) { return vabsq_x (a, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s32.c index 22d561d1e46..64d0e4b574d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s32.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabst.s32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo (int32x4_t a, mve_pred16_t p) { return vabsq_x_s32 (a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabst.s32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabst.s32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo1 (int32x4_t a, mve_pred16_t p) { return vabsq_x (a, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s8.c index 6908a6ca20c..742bc701fae 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s8.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabst.s8 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo (int8x16_t a, mve_pred16_t p) { return vabsq_x_s8 (a, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vabst.s8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vabst.s8 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo1 (int8x16_t a, mve_pred16_t p) { return vabsq_x (a, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file From patchwork Thu Nov 17 16:37:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrea Corallo X-Patchwork-Id: 60787 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 686F33833B2A for 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X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB9PR08MB7447 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andrea Corallo via Gcc-patches From: Andrea Corallo Reply-To: Andrea Corallo Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Stam Markianos-Wright It was observed that in tests `vaddq_m_n_[s/u][8/16/32].c`, the _Generic resolution would fall back to the `__ARM_undef` failure state. This is a regression since `dc39db873670bea8d8e655444387ceaa53a01a79` and `6bd4ce64eb48a72eca300cb52773e6101d646004`, but it previously wasn't identified, because the tests were not checking for this kind of failure. The above commits changed the definitions of the intrinsics from using `[u]int[8/16/32]_t` types for the scalar argument to using `int`. This allowed `int` to be supported in user code through the overloaded `#defines`, but seems to have broken the `[u]int[8/16/32]_t` types The solution implemented by this patch is to explicitly use a new _Generic mapping from all the `[u]int[8/16/32]_t` types for int. With this change, both `int` and `[u]int[8/16/32]_t` parameters are supported from user code and are handled by the overloading mechanism correctly. gcc/ChangeLog: * config/arm/arm_mve.h (__arm_vaddq_m_n_s8): Change types. (__arm_vaddq_m_n_s32): Likewise. (__arm_vaddq_m_n_s16): Likewise. (__arm_vaddq_m_n_u8): Likewise. (__arm_vaddq_m_n_u32): Likewise. (__arm_vaddq_m_n_u16): Likewise. (__arm_vaddq_m): Fix Overloading. (__ARM_mve_coerce3): New. --- gcc/config/arm/arm_mve.h | 78 ++++++++++++++++++++-------------------- 1 file changed, 40 insertions(+), 38 deletions(-) diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 684f997520f..951dc25374b 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -9675,42 +9675,42 @@ __arm_vabdq_m_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pr __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vaddq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, int __b, mve_pred16_t __p) +__arm_vaddq_m_n_s8 (int8x16_t __inactive, int8x16_t __a, int8_t __b, mve_pred16_t __p) { return __builtin_mve_vaddq_m_n_sv16qi (__inactive, __a, __b, __p); } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vaddq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, int __b, mve_pred16_t __p) +__arm_vaddq_m_n_s32 (int32x4_t __inactive, int32x4_t __a, int32_t __b, mve_pred16_t __p) { return __builtin_mve_vaddq_m_n_sv4si (__inactive, __a, __b, __p); } __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vaddq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, int __b, mve_pred16_t __p) +__arm_vaddq_m_n_s16 (int16x8_t __inactive, int16x8_t __a, int16_t __b, mve_pred16_t __p) { return __builtin_mve_vaddq_m_n_sv8hi (__inactive, __a, __b, __p); } __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vaddq_m_n_u8 (uint8x16_t __inactive, uint8x16_t __a, int __b, mve_pred16_t __p) +__arm_vaddq_m_n_u8 (uint8x16_t __inactive, uint8x16_t __a, uint8_t __b, mve_pred16_t __p) { return __builtin_mve_vaddq_m_n_uv16qi (__inactive, __a, __b, __p); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vaddq_m_n_u32 (uint32x4_t __inactive, uint32x4_t __a, int __b, mve_pred16_t __p) +__arm_vaddq_m_n_u32 (uint32x4_t __inactive, uint32x4_t __a, uint32_t __b, mve_pred16_t __p) { return __builtin_mve_vaddq_m_n_uv4si (__inactive, __a, __b, __p); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vaddq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, int __b, mve_pred16_t __p) +__arm_vaddq_m_n_u16 (uint16x8_t __inactive, uint16x8_t __a, uint16_t __b, mve_pred16_t __p) { return __builtin_mve_vaddq_m_n_uv8hi (__inactive, __a, __b, __p); } @@ -26417,42 +26417,42 @@ __arm_vabdq_m (uint16x8_t __inactive, uint16x8_t __a, uint16x8_t __b, mve_pred16 __extension__ extern __inline int8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vaddq_m (int8x16_t __inactive, int8x16_t __a, int __b, mve_pred16_t __p) +__arm_vaddq_m (int8x16_t __inactive, int8x16_t __a, int8_t __b, mve_pred16_t __p) { return __arm_vaddq_m_n_s8 (__inactive, __a, __b, __p); } __extension__ extern __inline int32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vaddq_m (int32x4_t __inactive, int32x4_t __a, int __b, mve_pred16_t __p) +__arm_vaddq_m (int32x4_t __inactive, int32x4_t __a, int32_t __b, mve_pred16_t __p) { return __arm_vaddq_m_n_s32 (__inactive, __a, __b, __p); } __extension__ extern __inline int16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vaddq_m (int16x8_t __inactive, int16x8_t __a, int __b, mve_pred16_t __p) +__arm_vaddq_m (int16x8_t __inactive, int16x8_t __a, int16_t __b, mve_pred16_t __p) { return __arm_vaddq_m_n_s16 (__inactive, __a, __b, __p); } __extension__ extern __inline uint8x16_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vaddq_m (uint8x16_t __inactive, uint8x16_t __a, int __b, mve_pred16_t __p) +__arm_vaddq_m (uint8x16_t __inactive, uint8x16_t __a, uint8_t __b, mve_pred16_t __p) { return __arm_vaddq_m_n_u8 (__inactive, __a, __b, __p); } __extension__ extern __inline uint32x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vaddq_m (uint32x4_t __inactive, uint32x4_t __a, int __b, mve_pred16_t __p) +__arm_vaddq_m (uint32x4_t __inactive, uint32x4_t __a, uint32_t __b, mve_pred16_t __p) { return __arm_vaddq_m_n_u32 (__inactive, __a, __b, __p); } __extension__ extern __inline uint16x8_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__arm_vaddq_m (uint16x8_t __inactive, uint16x8_t __a, int __b, mve_pred16_t __p) +__arm_vaddq_m (uint16x8_t __inactive, uint16x8_t __a, uint16_t __b, mve_pred16_t __p) { return __arm_vaddq_m_n_u16 (__inactive, __a, __b, __p); } @@ -35657,6 +35657,8 @@ extern void *__ARM_undef; _Generic(param, type: param, const type: param, default: *(type *)__ARM_undef) #define __ARM_mve_coerce2(param, type) \ _Generic(param, type: param, float16_t: param, float32_t: param, default: *(type *)__ARM_undef) +#define __ARM_mve_coerce3(param, type) \ + _Generic(param, type: param, int8_t: param, int16_t: param, int32_t: param, int64_t: param, uint8_t: param, uint16_t: param, uint32_t: param, uint64_t: param, default: *(type *)__ARM_undef) #if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */ @@ -35871,14 +35873,14 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vaddq_f16 (__ARM_mve_coerce(p0, float16x8_t), __ARM_mve_coerce(p1, float16x8_t)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vaddq_f32 (__ARM_mve_coerce(p0, float32x4_t), __ARM_mve_coerce(p1, float32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vaddq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vaddq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)));}) @@ -37316,12 +37318,12 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vaddq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vaddq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int), p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double), p3), \ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double), p3));}) @@ -38820,12 +38822,12 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int)));}) + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));}) #define __arm_vandq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -39641,12 +39643,12 @@ extern void *__ARM_undef; __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int), p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, int), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, int), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, int), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ From patchwork Thu Nov 17 16:37:48 2022 Content-Type: text/plain; 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Thu, 17 Nov 2022 16:38:21 +0000 To: CC: , , "Stam Markianos-Wright" Subject: [PATCH 14/35] arm: propagate fixed overloading of MVE intrinsic scalar parameters Date: Thu, 17 Nov 2022 17:37:48 +0100 Message-ID: <20221117163809.1009526-15-andrea.corallo@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221117163809.1009526-1-andrea.corallo@arm.com> References: <20221117163809.1009526-1-andrea.corallo@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: DBAEUR03FT019:EE_|DU0PR08MB9512:EE_|DBAEUR03FT042:EE_|AS8PR08MB6007:EE_ X-MS-Office365-Filtering-Correlation-Id: 74cebd36-abb0-4b62-3049-08dac8ba3a1d x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: OdNHAUV72D4Xi/91xM7ohPbABI6F2/m6nTLVJChbTWAq+1WBCGs3ufhMXnQZ3iI7AEs79Ma+xPfIEvJ9EBEKe6qjzdKqlP0v7B9AYwGt4zMJnKVH685Yq6Cbqdr4U33BrZsNp6DF7PduFyiOyLmk4XTsYEHEouz1L5zUb2ve7MV9QifRydhmH4YdwgETPY9+qCyD7Zyi3bFn4zZI3MKNWsWZ/kjMI3YO55yibDu1H8WA/HSkry/5SrGUhlyQaSsmVDdCx6GrukS9X1hXOY2OcnoagPc67/jva89XOs3cMCiGRHQhn9RSh+U03vcg9LBMXk0eAx/JXDG+m3HkTA2yc9Q29+ACO5+HpVcvEaGi0Nnc1C+UPRO/JxvXQoOgaXgkgToBpGbLtVJxlpa+CysIEdnmTCv2GumN41YMOxL50eZjURj357N2SjsvvLpNC80XvllqfaStpgSjNtVFsRlsh1jZh2VxuTJ6SKt+uQ3qfFS8nnF6kY2kz7RNDq+h++T28MjEhVhuA41UWHlVXRZMtPml0pDUm0T/AnqQ2CFrks3uaIyXr0mHWOLONgy4Ddz7G6sjx/7wrfdSWeWcwLWiI3AnmzPUX/FyqKqTiTytSBY86eiG25+hD7ng2VaHH+1mfPo4taIhNaZOqNxPeNKJhzlw3hbKnYmcGuFuZMrLvY8O2I0+LPHtBU/B4srIyLXuu9d9AJ2L9o1uTCcEy4EmCKh1ohXImtFHNfLu1mCv+K0= X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; 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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT042.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB6007 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Andrea Corallo via Gcc-patches From: Andrea Corallo Reply-To: Andrea Corallo Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Stam Markianos-Wright This is a mechanical patch that propagates the change proposed in my previous patch for vaddq[_m]_n across all other polymorphic MVE intrinsic overloads of scalar types. The find and Replace patterns used were: s/__ARM_mve_coerce\(__p(\d+), [u]?int(8|16|32|64)_t\) /__ARM_mve_coerce3(p$1, int)/g s/__ARM_mve_coerce2\(__p(\d+), double\) /__ARM_mve_coerce2(p$1, double)/g gcc/ChangeLog: * config/arm/arm_mve.h (__arm_vaddq): Fix Overloading. (__arm_vmulq): Likewise. (__arm_vcmpeqq): Likewise. (__arm_vcmpneq): Likewise. (__arm_vmaxnmavq): Likewise. (__arm_vmaxnmvq): Likewise. (__arm_vminnmavq): Likewise. (__arm_vsubq): Likewise. (__arm_vminnmvq): Likewise. (__arm_vrshlq): Likewise. (__arm_vqsubq): Likewise. (__arm_vqdmulltq): Likewise. (__arm_vqdmullbq): Likewise. (__arm_vqdmulhq): Likewise. (__arm_vqaddq): Likewise. (__arm_vhaddq): Likewise. (__arm_vhsubq): Likewise. (__arm_vqdmlashq): Likewise. (__arm_vqrdmlahq): Likewise. (__arm_vmlasq): Likewise. (__arm_vqdmlahq): Likewise. (__arm_vmaxnmavq_p): Likewise. (__arm_vmaxnmvq_p): Likewise. (__arm_vminnmavq_p): Likewise. (__arm_vminnmvq_p): Likewise. (__arm_vfmasq_m): Likewise. (__arm_vsetq_lane): Likewise. (__arm_vcmpneq_m): Likewise. (__arm_vhaddq_x): Likewise. (__arm_vhsubq_x): Likewise. (__arm_vqrdmlashq_m): Likewise. (__arm_vqdmlashq_m): Likewise. (__arm_vmlaldavaxq_p): Likewise. (__arm_vmlasq_m): Likewise. (__arm_vqdmulhq_m): Likewise. (__arm_vqdmulltq_m): Likewise. (__arm_viwdupq_m): Likewise. (__arm_viwdupq_u16): Likewise. (__arm_viwdupq_u32): Likewise. (__arm_viwdupq_u8): Likewise. (__arm_vdwdupq_m): Likewise. (__arm_vdwdupq_u16): Likewise. (__arm_vdwdupq_u32): Likewise. (__arm_vdwdupq_u8): Likewise. (__arm_vaddlvaq): Likewise. (__arm_vaddlvaq_p): Likewise. (__arm_vaddvaq): Likewise. (__arm_vaddvaq_p): Likewise. (__arm_vcmphiq_m): Likewise. (__arm_vmladavaq_p): Likewise. (__arm_vmladavaxq): Likewise. (__arm_vmlaldavaxq): Likewise. (__arm_vrmlaldavhaq_p): Likewise. --- gcc/config/arm/arm_mve.h | 1106 +++++++++++++++++++------------------- 1 file changed, 553 insertions(+), 553 deletions(-) diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h index 951dc25374b..fd1876b57a0 100644 --- a/gcc/config/arm/arm_mve.h +++ b/gcc/config/arm/arm_mve.h @@ -35881,8 +35881,8 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)));}) + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)));}) #define __arm_vandq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -35927,14 +35927,14 @@ extern void *__ARM_undef; #define __arm_vmulq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ @@ -35959,14 +35959,14 @@ extern void *__ARM_undef; #define __arm_vcmpeqq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpeqq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpeqq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpeqq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ @@ -35997,16 +35997,16 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpeqq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpeqq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpeqq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2), \ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpeqq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpeqq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double), p2), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double), p2));}) + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpeqq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double), p2));}) #define __arm_vcmpgtq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -36014,13 +36014,13 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgtq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgtq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)));}) + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)));}) #define __arm_vcmpleq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -36030,11 +36030,11 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpleq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpleq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)));}) #define __arm_vcmpltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -36042,25 +36042,25 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpltq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpltq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpltq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)));}) + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)));}) #define __arm_vcmpneq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpneq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpneq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpneq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ @@ -36115,8 +36115,8 @@ extern void *__ARM_undef; #define __arm_vmaxnmavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));}) + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t)));}) #define __arm_vmaxnmq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -36127,14 +36127,14 @@ extern void *__ARM_undef; #define __arm_vmaxnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));}) + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t)));}) #define __arm_vmaxnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));}) + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t)));}) #define __arm_vminnmaq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -36145,8 +36145,8 @@ extern void *__ARM_undef; #define __arm_vminnmavq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmavq_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmavq_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));}) + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmavq_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmavq_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t)));}) #define __arm_vbrsrq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ @@ -36168,14 +36168,14 @@ extern void *__ARM_undef; #define __arm_vsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ @@ -36188,8 +36188,8 @@ extern void *__ARM_undef; #define __arm_vminnmvq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmvq_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \ - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmvq_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t)));}) + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmvq_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t)), \ + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmvq_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t)));}) #define __arm_vshlq_r(p0,p1) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ @@ -36244,12 +36244,12 @@ extern void *__ARM_undef; #define __arm_vrshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ @@ -36280,12 +36280,12 @@ extern void *__ARM_undef; #define __arm_vqsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ @@ -36336,12 +36336,12 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)));}) #define __arm_vqrdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -36349,9 +36349,9 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));}) #define __arm_vmlaldavxq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -36384,8 +36384,8 @@ extern void *__ARM_undef; #define __arm_vqdmulltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) @@ -36398,17 +36398,17 @@ extern void *__ARM_undef; #define __arm_vqdmullbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmullbq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmullbq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) #define __arm_vqdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) @@ -36416,12 +36416,12 @@ extern void *__ARM_undef; #define __arm_vqaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ @@ -36454,12 +36454,12 @@ extern void *__ARM_undef; #define __arm_vhaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ @@ -36484,12 +36484,12 @@ extern void *__ARM_undef; #define __arm_vhsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ @@ -36632,12 +36632,12 @@ extern void *__ARM_undef; __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int)));}) #define __arm_vsriq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -36716,44 +36716,44 @@ extern void *__ARM_undef; __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));}) #define __arm_vqdmlashq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));}) #define __arm_vqrdmlahq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));}) #define __arm_vmlasq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int)));}) #define __arm_vqdmlahq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));}) #define __arm_vqrdmladhxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -36943,11 +36943,11 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double), p2), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double), p2), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgtq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double), p2), \ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgtq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgtq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) @@ -36959,11 +36959,11 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpleq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpleq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double), p2), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double), p2));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpleq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double), p2));}) #define __arm_vcmpltq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -36973,11 +36973,11 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpltq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpltq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double), p2), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double), p2));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpltq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double), p2));}) #define __arm_vcmpneq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -36990,14 +36990,14 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpneq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpneq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpneq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double), p2), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double), p2));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpneq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double), p2));}) #define __arm_vcvtbq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -37051,8 +37051,8 @@ extern void *__ARM_undef; __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmaq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmaq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double)), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmaq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmaq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double)), \ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vfmaq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t)), \ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vfmaq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t)));}) @@ -37067,8 +37067,8 @@ extern void *__ARM_undef; __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmasq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmasq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double)));}) + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmasq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmasq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double)));}) #define __arm_vmaxnmaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -37091,14 +37091,14 @@ extern void *__ARM_undef; #define __arm_vmaxnmavq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_p_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \ - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_p_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmavq_p_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmavq_p_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));}) #define __arm_vmaxnmvq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_p_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \ - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_p_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vmaxnmvq_p_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vmaxnmvq_p_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));}) #define __arm_vminnmaq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -37109,14 +37109,14 @@ extern void *__ARM_undef; #define __arm_vminnmavq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmavq_p_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \ - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmavq_p_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmavq_p_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmavq_p_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));}) #define __arm_vminnmvq_p(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmvq_p_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \ - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmvq_p_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vminnmvq_p_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vminnmvq_p_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));}) #define __arm_vrndnq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -37178,13 +37178,13 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgeq_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t)), \ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgeq_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t)), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double)), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double)));}) + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double)), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double)));}) #define __arm_vrshrnbq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -37285,11 +37285,11 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(__p1, double), p2), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(__p1, double), p2), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce2(p1, double), p2), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vcmpgeq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce2(p1, double), p2), \ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vcmpgeq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), p2), \ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vcmpgeq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), p2));}) @@ -37324,8 +37324,8 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double), p3), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double), p3));}) + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));}) #define __arm_vandq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -37466,15 +37466,15 @@ extern void *__ARM_undef; _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vfmaq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vfmaq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmaq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double), p3), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmaq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double), p3));}) + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmaq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmaq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));}) #define __arm_vfmasq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmasq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double), p3), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmasq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double), p3));}) + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vfmasq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vfmasq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));}) #define __arm_vfmsq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -37509,14 +37509,14 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmulq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmulq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double), p3), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double), p3));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));}) #define __arm_vornq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -37543,14 +37543,14 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vsubq_m_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vsubq_m_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double), p3), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double), p3));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_m_n_f16 (__ARM_mve_coerce(__p0, float16x8_t), __ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_m_n_f32 (__ARM_mve_coerce(__p0, float32x4_t), __ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));}) #define __arm_vorrq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -38023,19 +38023,19 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vaddq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vaddq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vaddq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vaddq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double), p3), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double), p3));}) + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vaddq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vaddq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));}) #define __arm_vandq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ @@ -38158,19 +38158,19 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vmulq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vmulq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double), p3), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double), p3));}) + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vmulq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vmulq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));}) #define __arm_vnegq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ @@ -38258,8 +38258,8 @@ extern void *__ARM_undef; _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_float16x8_t]: __arm_vsubq_x_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce(__p2, float16x8_t), p3), \ int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_float32x4_t]: __arm_vsubq_x_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce(__p2, float32x4_t), p3), \ - int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(__p2, double), p3), \ - int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(__p2, double), p3));}) + int (*)[__ARM_mve_type_float16x8_t][__ARM_mve_type_fp_n]: __arm_vsubq_x_n_f16 (__ARM_mve_coerce(__p1, float16x8_t), __ARM_mve_coerce2(p2, double), p3), \ + int (*)[__ARM_mve_type_float32x4_t][__ARM_mve_type_fp_n]: __arm_vsubq_x_n_f32 (__ARM_mve_coerce(__p1, float32x4_t), __ARM_mve_coerce2(p2, double), p3));}) #define __arm_vcmulq_rot90_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ @@ -38283,16 +38283,16 @@ extern void *__ARM_undef; #define __arm_vsetq_lane(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vsetq_lane_s8 (__ARM_mve_coerce(__p0, int8_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vsetq_lane_s16 (__ARM_mve_coerce(__p0, int16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vsetq_lane_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]: __arm_vsetq_lane_s64 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int64x2_t), p2), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vsetq_lane_u8 (__ARM_mve_coerce(__p0, uint8_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vsetq_lane_u16 (__ARM_mve_coerce(__p0, uint16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vsetq_lane_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]: __arm_vsetq_lane_u64 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint64x2_t), p2), \ - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vsetq_lane_f16 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \ - int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vsetq_lane_f32 (__ARM_mve_coerce2(__p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));}) + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vsetq_lane_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vsetq_lane_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vsetq_lane_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]: __arm_vsetq_lane_s64 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int64x2_t), p2), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vsetq_lane_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vsetq_lane_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vsetq_lane_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]: __arm_vsetq_lane_u64 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint64x2_t), p2), \ + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float16x8_t]: __arm_vsetq_lane_f16 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float16x8_t), p2), \ + int (*)[__ARM_mve_type_fp_n][__ARM_mve_type_float32x4_t]: __arm_vsetq_lane_f32 (__ARM_mve_coerce2(p0, double), __ARM_mve_coerce(__p1, float32x4_t), p2));}) #else /* MVE Integer. */ @@ -38410,12 +38410,12 @@ extern void *__ARM_undef; #define __arm_vcmpneq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpneq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpneq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpneq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ @@ -38442,12 +38442,12 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vsubq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vsubq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vsubq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)));}) #define __arm_vshlq_r(p0,p1) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ @@ -38461,12 +38461,12 @@ extern void *__ARM_undef; #define __arm_vrshlq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vrshlq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vrshlq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vrshlq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ @@ -38497,12 +38497,12 @@ extern void *__ARM_undef; #define __arm_vqsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ @@ -38571,12 +38571,12 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrshlq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrshlq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrshlq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqrshlq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)));}) #define __arm_vqrdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -38584,16 +38584,16 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));}) #define __arm_vqdmulhq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulhq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqdmulhq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulhq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulhq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) @@ -38601,12 +38601,12 @@ extern void *__ARM_undef; #define __arm_vqaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ @@ -38637,12 +38637,12 @@ extern void *__ARM_undef; #define __arm_vmulq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ @@ -38717,12 +38717,12 @@ extern void *__ARM_undef; #define __arm_vhsubq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhsubq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhsubq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhsubq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ @@ -38747,12 +38747,12 @@ extern void *__ARM_undef; #define __arm_vhaddq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ @@ -38858,12 +38858,12 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpeqq_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t)), \ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpeqq_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t)), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpeqq_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int)));}) #define __arm_vqmovntq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -38944,16 +38944,16 @@ extern void *__ARM_undef; #define __arm_vqdmulltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmulltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmulltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmulltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) #define __arm_vqdmullbq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmullbq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqdmullbq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqdmullbq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)));}) @@ -38963,9 +38963,9 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));}) #define __arm_vcmpgtq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -38973,9 +38973,9 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));}) #define __arm_vcmpleq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -38983,9 +38983,9 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpleq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpleq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));}) #define __arm_vcmpltq(p0,p1) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -38993,20 +38993,20 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpltq_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t)), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpltq_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t)), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t)), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int)));}) #define __arm_vcmpneq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpneq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpneq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpneq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpneq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ @@ -39031,12 +39031,12 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpeqq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpeqq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpeqq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpeqq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2));}) #define __arm_vbicq_m_n(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)])0, \ @@ -39146,25 +39146,25 @@ extern void *__ARM_undef; __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));}) #define __arm_vqdmlashq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));}) #define __arm_vqrdmlahq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));}) #define __arm_vqrdmladhxq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -39227,9 +39227,9 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgeq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgeq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgeq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgeq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2));}) #define __arm_vcmpgtq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ @@ -39238,9 +39238,9 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpgtq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpgtq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpgtq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpgtq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2));}) #define __arm_vcmpleq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -39248,9 +39248,9 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpleq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpleq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpleq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpleq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2));}) #define __arm_vcmpltq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -39258,9 +39258,9 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vcmpltq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vcmpltq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vcmpltq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpltq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2));}) #define __arm_vcmpneq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -39271,12 +39271,12 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vcmpneq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vcmpneq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vcmpneq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8_t), p2), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16_t), p2), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32_t), p2), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8_t), p2), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16_t), p2), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32_t), p2));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce3(p1, int), p2), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vcmpneq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce3(p1, int), p2));}) #define __arm_vdupq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -39299,23 +39299,23 @@ extern void *__ARM_undef; __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlaq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int)));}) #define __arm_vmlasq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t)), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t)), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmlasq_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int)));}) #define __arm_vnegq_m(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -39340,9 +39340,9 @@ extern void *__ARM_undef; __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t)), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t)), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t)));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int)), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlahq_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int)));}) #define __arm_vqdmlsdhq(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -39505,12 +39505,12 @@ extern void *__ARM_undef; __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vsubq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vsubq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vsubq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ @@ -39610,12 +39610,12 @@ extern void *__ARM_undef; __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_p_s8 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_p_s16 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_p_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_p_u8 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_p_u16 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_p_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmladavaq_p_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmladavaq_p_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmladavaq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmladavaq_p_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmladavaq_p_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmladavaq_p_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) #define __arm_vornq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -39660,12 +39660,12 @@ extern void *__ARM_undef; __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ @@ -40002,15 +40002,15 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vaddq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vaddq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vaddq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vaddq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vaddq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vaddq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3));}) + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vaddq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3));}) #define __arm_vcaddq_rot270_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ @@ -40104,15 +40104,15 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vmulq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmulq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmulq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vmulq_x_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmulq_x_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmulq_x_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3));}) + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vmulq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3));}) #define __arm_vnegq_x(p1,p2) ({ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p1)])0, \ @@ -40234,14 +40234,14 @@ extern void *__ARM_undef; #define __arm_vsetq_lane(p0,p1,p2) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)])0, \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vsetq_lane_s8 (__ARM_mve_coerce(__p0, int8_t), __ARM_mve_coerce(__p1, int8x16_t), p2), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vsetq_lane_s16 (__ARM_mve_coerce(__p0, int16_t), __ARM_mve_coerce(__p1, int16x8_t), p2), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vsetq_lane_s32 (__ARM_mve_coerce(__p0, int32_t), __ARM_mve_coerce(__p1, int32x4_t), p2), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]: __arm_vsetq_lane_s64 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int64x2_t), p2), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vsetq_lane_u8 (__ARM_mve_coerce(__p0, uint8_t), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vsetq_lane_u16 (__ARM_mve_coerce(__p0, uint16_t), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vsetq_lane_u32 (__ARM_mve_coerce(__p0, uint32_t), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]: __arm_vsetq_lane_u64 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint64x2_t), p2));}) + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int8x16_t]: __arm_vsetq_lane_s8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int8x16_t), p2), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t]: __arm_vsetq_lane_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), p2), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t]: __arm_vsetq_lane_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), p2), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int64x2_t]: __arm_vsetq_lane_s64 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int64x2_t), p2), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint8x16_t]: __arm_vsetq_lane_u8 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint8x16_t), p2), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t]: __arm_vsetq_lane_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), p2), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t]: __arm_vsetq_lane_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), p2), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint64x2_t]: __arm_vsetq_lane_u64 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint64x2_t), p2));}) #endif /* MVE Integer. */ @@ -40421,12 +40421,12 @@ extern void *__ARM_undef; #define __arm_vhaddq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u8( __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u16( __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u32( __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u8( __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u16( __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_x_n_u32( __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ @@ -40451,12 +40451,12 @@ extern void *__ARM_undef; #define __arm_vhsubq_x(p1,p2,p3) ({ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u8 (__ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u16 (__ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhsubq_x_n_u32 (__ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhsubq_x_s8 (__ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhsubq_x_s16 (__ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhsubq_x_s32 (__ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ @@ -40576,25 +40576,25 @@ extern void *__ARM_undef; __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlahq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3));}) #define __arm_vqrdmlashq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmlashq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3));}) #define __arm_vqdmlashq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqdmlashq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3));}) #define __arm_vqrshlq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -40695,12 +40695,12 @@ extern void *__ARM_undef; __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vqsubq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqsubq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqsubq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqsubq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ @@ -40715,9 +40715,9 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vqrdmulhq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vqrdmulhq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vqrdmulhq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3));}) + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vqrdmulhq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3));}) #define __arm_vqrdmlsdhxq_m(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -40843,17 +40843,17 @@ extern void *__ARM_undef; __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaq_p_s16 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaq_p_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavaq_p_u16 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavaq_p_u32 (__ARM_mve_coerce(__p0, uint64_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaq_p_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vmlaldavaq_p_u16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vmlaldavaq_p_u32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3));}) #define __arm_vmlaldavaxq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaxq_p_s16 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ - int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaxq_p_s32 (__ARM_mve_coerce(__p0, int64_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vmlaldavaxq_p_s16 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ + int (*)[__ARM_mve_type_int_n][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vmlaldavaxq_p_s32 (__ARM_mve_coerce3(p0, int), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3));}) #define __arm_vmlsldavaq_p(p0,p1,p2,p3) ({ __typeof(p0) __p0 = (p0); \ __typeof(p1) __p1 = (p1); \ @@ -40992,12 +40992,12 @@ extern void *__ARM_undef; __typeof(p1) __p1 = (p1); \ __typeof(p2) __p2 = (p2); \ _Generic( (int (*)[__ARM_mve_typeid(__p0)][__ARM_mve_typeid(__p1)][__ARM_mve_typeid(__p2)])0, \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8_t), p3), \ - int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16_t), p3), \ - int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32_t), p3), \ - int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8_t), p3), \ - int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16_t), p3), \ - int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32_t), p3), \ + int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce3(p2, int), p3), \ + int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_int_n]: __arm_vhaddq_m_n_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce3(p2, int), p3), \ int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t]: __arm_vhaddq_m_s8 (__ARM_mve_coerce(__p0, int8x16_t), __ARM_mve_coerce(__p1, int8x16_t), __ARM_mve_coerce(__p2, int8x16_t), p3), \ int (*)[__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t][__ARM_mve_type_int16x8_t]: __arm_vhaddq_m_s16 (__ARM_mve_coerce(__p0, int16x8_t), __ARM_mve_coerce(__p1, int16x8_t), __ARM_mve_coerce(__p2, int16x8_t), p3), \ int (*)[__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t][__ARM_mve_type_int32x4_t]: __arm_vhaddq_m_s32 (__ARM_mve_coerce(__p0, int32x4_t), __ARM_mve_coerce(__p1, int32x4_t), __ARM_mve_coerce(__p2, int32x4_t), p3), \ @@ -41031,12 +41031,12 @@ extern void *__ARM_undef; int (*)[__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t][__ARM_mve_type_uint8x16_t]: __arm_vhsubq_m_u8 (__ARM_mve_coerce(__p0, uint8x16_t), __ARM_mve_coerce(__p1, uint8x16_t), __ARM_mve_coerce(__p2, uint8x16_t), p3), \ int (*)[__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t][__ARM_mve_type_uint16x8_t]: __arm_vhsubq_m_u16 (__ARM_mve_coerce(__p0, uint16x8_t), __ARM_mve_coerce(__p1, uint16x8_t), __ARM_mve_coerce(__p2, uint16x8_t), p3), \ int (*)[__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t][__ARM_mve_type_uint32x4_t]: __arm_vhsubq_m_u32 (__ARM_mve_coerce(__p0, uint32x4_t), __ARM_mve_coerce(__p1, uint32x4_t), __ARM_mve_coerce(__p2, uint32x4_t), p3), \ - int (*)[__ARM_mve_type_int8x16_t][__ARM_mve_type_int8x16_t][__ARM_