From patchwork Wed Nov 16 21:16:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kevin Lee X-Patchwork-Id: 60721 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 61F19396E01C for ; Wed, 16 Nov 2022 21:17:22 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pg1-x531.google.com (mail-pg1-x531.google.com [IPv6:2607:f8b0:4864:20::531]) by sourceware.org (Postfix) with ESMTPS id 8DDF1396DC1F for ; Wed, 16 Nov 2022 21:17:04 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 8DDF1396DC1F Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pg1-x531.google.com with SMTP id 130so54649pgc.5 for ; Wed, 16 Nov 2022 13:17:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=jNnDTRhki199GELI080irERMkrNIusYmQYjl387mk94=; b=vy5KNmZO8jYYFa+NjI9h3GjxjKeINxD4XTRkELJ5QisvmujMAadgWGPHoMi6xXPnfU uQJgQfSEGneG1A45SOFsk+gguY5foCOFldNuv2xQxR942yElxqN2WF2lOrxHuo15xflB LrZO8zM4CXvsx153mrzEFltSFp7BOCAaD2TA/IPSa1ia+JkVWHIXYO4bFXVNRqIUYseD 0xuWEP1YYJ4DXRllbiS8bIoC7R9G6GnilzbyEXQcqfRfC58VDHNC2yW2XXK3QhqKE1rM oW45CuNRxaJPZ+cKoIjBLshupAqDaVakdMOpKtXMEPQDyihxT8jqFFZ92MImX6bzbkzx qzHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=jNnDTRhki199GELI080irERMkrNIusYmQYjl387mk94=; b=nKsg+AObOgyl2i8pXnhrfwxns+Z5pspKWFv9OnhjTMQwSMuSR9A2hj7xfhmsTVxhvx tyZwZAMtlc91PLQ2+m4wT5kMC8SWVc9EZEhIfOh93d4kCDfa8/L5zXf7YIoCR9ThlM0B jixej3cFiBRwuLNyr65+8Vgw/YqRbBupCqTdFlTenCYqXJ225DySr+o/hRhalIwc6e2x OxvyUTSdStK2rhTzx+vXi2k9alIl6Vy/J6+gmT8rHkBjcc+lNCmwi6BJn8LRqtMlvBHD WSu4Sbee2wPx9q0EhyqFzTGcEppAtQnv5eGd/7fttgkVh0Z8KAQk6ZmJH+KZf5DnpNnW QvjQ== X-Gm-Message-State: ANoB5pnZjJOyqUdKa+89ldToH9+S68AIZPX+Frr47fDIX9YMS+HujgEV WtF/iTN/KjavVxdU9sKJGWu0H2BQm3FneA== X-Google-Smtp-Source: AA0mqf6P15c8w1vOm6RRzIWEVdpwX6yubUU5USGgEdRrbS3RCLZbWA0rvoOeADbu0WXB7Mo8E47EGQ== X-Received: by 2002:a63:1949:0:b0:46f:38ad:de99 with SMTP id 9-20020a631949000000b0046f38adde99mr22523049pgz.218.1668633423078; Wed, 16 Nov 2022 13:17:03 -0800 (PST) Received: from kevinl.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id gl14-20020a17090b120e00b0020af2bab83fsm2086571pjb.23.2022.11.16.13.17.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Nov 2022 13:17:02 -0800 (PST) From: Kevin Lee To: gcc-patches@gcc.gnu.org Cc: gnu-toolchain@rivosinc.com, palmer@dabbelt.com, Kevin Lee Subject: [PATCH v3] RISC-V missing __builtin_lceil and __builtin_lfloor Date: Wed, 16 Nov 2022 13:16:14 -0800 Message-Id: <20221116211614.904834-1-kevinl@rivosinc.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" l insn condition has been modified based on the thread in https://gcc.gnu.org/pipermail/gcc-patches/2022-November/605481.html. The lfloor-lecil-inexact checks call instead of scan-assembler-not "fcvt.l.s/d" due to https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107723. Is this patch good for commit? gcc/ChangeLog: Michael Collison Kevin Lee * config/riscv/iterators.md (RINT): Additional iterators. (rint_pattern): Additional attributes. (rint_rm): Ditto. * config/riscv/riscv.md (UNSPEC_LCEIL): New unspec. (UNSPEC_LFLOOR): Ditto. (l2): Additional conditions. gcc/testsuite/ChangeLog: * gcc.target/riscv/lfloor-lceil-inexact.c: New test. * gcc.target/riscv/lfloor-lceil.c: New test. --- gcc/config/riscv/iterators.md | 10 ++- gcc/config/riscv/riscv.md | 8 +- .../gcc.target/riscv/lfloor-lceil-inexact.c | 78 ++++++++++++++++++ gcc/testsuite/gcc.target/riscv/lfloor-lceil.c | 79 +++++++++++++++++++ 4 files changed, 171 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/lfloor-lceil-inexact.c create mode 100644 gcc/testsuite/gcc.target/riscv/lfloor-lceil.c diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md index 50380ecfac9..c5adcb08421 100644 --- a/gcc/config/riscv/iterators.md +++ b/gcc/config/riscv/iterators.md @@ -233,9 +233,13 @@ (define_code_attr bitmanip_insn [(smin "min") ;; ------------------------------------------------------------------- ;; Iterator and attributes for floating-point rounding instructions. -(define_int_iterator RINT [UNSPEC_LRINT UNSPEC_LROUND]) -(define_int_attr rint_pattern [(UNSPEC_LRINT "rint") (UNSPEC_LROUND "round")]) -(define_int_attr rint_rm [(UNSPEC_LRINT "dyn") (UNSPEC_LROUND "rmm")]) +(define_int_iterator RINT [UNSPEC_LRINT UNSPEC_LROUND UNSPEC_LCEIL UNSPEC_LFLOOR]) +(define_int_attr rint_pattern [(UNSPEC_LRINT "rint") (UNSPEC_LROUND "round") + (UNSPEC_LCEIL "ceil") (UNSPEC_LFLOOR "floor")]) +(define_int_attr rint_rm [(UNSPEC_LRINT "dyn") (UNSPEC_LROUND "rmm") + (UNSPEC_LCEIL "rup") (UNSPEC_LFLOOR "rdn")]) +(define_int_attr rint_allow_inexact [(UNSPEC_LRINT "1") (UNSPEC_LROUND "0") + (UNSPEC_LCEIL "0") (UNSPEC_LFLOOR "0")]) ;; Iterator and attributes for quiet comparisons. (define_int_iterator QUIET_COMPARISON [UNSPEC_FLT_QUIET UNSPEC_FLE_QUIET]) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 798f7370a08..57777074f8e 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -60,6 +60,9 @@ (define_c_enum "unspec" [ UNSPEC_FMIN UNSPEC_FMAX + UNSPEC_LCEIL + UNSPEC_LFLOOR + ;; Stack tie UNSPEC_TIE ]) @@ -1552,7 +1555,10 @@ (define_insn "l2" (unspec:GPR [(match_operand:ANYF 1 "register_operand" " f")] RINT))] - "TARGET_HARD_FLOAT || TARGET_ZFINX" + "(TARGET_HARD_FLOAT || TARGET_ZFINX) && + ( + || flag_fp_int_builtin_inexact + || !flag_trapping_math)" "fcvt.. %0,%1," [(set_attr "type" "fcvt") (set_attr "mode" "")]) diff --git a/gcc/testsuite/gcc.target/riscv/lfloor-lceil-inexact.c b/gcc/testsuite/gcc.target/riscv/lfloor-lceil-inexact.c new file mode 100644 index 00000000000..3b37df20d0e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/lfloor-lceil-inexact.c @@ -0,0 +1,78 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -fno-fp-int-builtin-inexact" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +int +ceil1(float i) +{ + return __builtin_lceil(i); +} + +long +ceil2(float i) +{ + return __builtin_lceil(i); +} + +long long +ceil3(float i) +{ + return __builtin_lceil(i); +} + +int +ceil4(double i) +{ + return __builtin_lceil(i); +} + +long +ceil5(double i) +{ + return __builtin_lceil(i); +} + +long long +ceil6(double i) +{ + return __builtin_lceil(i); +} + +int +floor1(float i) +{ + return __builtin_lfloor(i); +} + +long +floor2(float i) +{ + return __builtin_lfloor(i); +} + +long long +floor3(float i) +{ + return __builtin_lfloor(i); +} + +int +floor4(double i) +{ + return __builtin_lfloor(i); +} + +long +floor5(double i) +{ + return __builtin_lfloor(i); +} + +long long +floor6(double i) +{ + return __builtin_lfloor(i); +} + +/* { dg-final { scan-assembler-times "call" 12 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/lfloor-lceil.c b/gcc/testsuite/gcc.target/riscv/lfloor-lceil.c new file mode 100644 index 00000000000..4715de746fb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/lfloor-lceil.c @@ -0,0 +1,79 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +int +ceil1(float i) +{ + return __builtin_lceil(i); +} + +long +ceil2(float i) +{ + return __builtin_lceil(i); +} + +long long +ceil3(float i) +{ + return __builtin_lceil(i); +} + +int +ceil4(double i) +{ + return __builtin_lceil(i); +} + +long +ceil5(double i) +{ + return __builtin_lceil(i); +} + +long long +ceil6(double i) +{ + return __builtin_lceil(i); +} + +int +floor1(float i) +{ + return __builtin_lfloor(i); +} + +long +floor2(float i) +{ + return __builtin_lfloor(i); +} + +long long +floor3(float i) +{ + return __builtin_lfloor(i); +} + +int +floor4(double i) +{ + return __builtin_lfloor(i); +} + +long +floor5(double i) +{ + return __builtin_lfloor(i); +} + +long long +floor6(double i) +{ + return __builtin_lfloor(i); +} + +/* { dg-final { scan-assembler-times "fcvt.l.s" 6 } } */ +/* { dg-final { scan-assembler-times "fcvt.l.d" 6 } } */ +/* { dg-final { scan-assembler-not "call" } } */