From patchwork Tue Nov 15 08:33:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawei X-Patchwork-Id: 60629 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7FE4E388A022 for ; Tue, 15 Nov 2022 08:35:27 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) by sourceware.org (Postfix) with ESMTP id D4CAD3885531 for ; Tue, 15 Nov 2022 08:34:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D4CAD3885531 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [47.113.87.88]) by APP-01 (Coremail) with SMTP id qwCowABX92gDT3NjglDgCQ--.2434S3; Tue, 15 Nov 2022 16:34:12 +0800 (CST) From: jiawei To: gcc-patches@gcc.gnu.org Cc: kito.cheng@sifive.com, palmer@rivosinc.com, juzhe.zhong@rivai.ai, jeffreyalaw@gmail.com, christoph.muellner@vrull.eu, philipp.tomsich@vrull.eu, wuwei2016@iscas.ac.cn, jiawei Subject: [PATCH v2 1/2] RISC-V: Add spill sp adjust check testcase. Date: Tue, 15 Nov 2022 16:33:57 +0800 Message-Id: <20221115083358.4130952-2-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221115083358.4130952-1-jiawei@iscas.ac.cn> References: <20221115083358.4130952-1-jiawei@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: qwCowABX92gDT3NjglDgCQ--.2434S3 X-Coremail-Antispam: 1UD129KBjvdXoW7Gw4UGr1xJr17GF45uw43GFg_yoWDCFgEyr 18K34fWr4Uua18tFWkZFsrCa4xCw4rXryaya9xJFn7Wa4DXan7u3Z2kF17t34UCr15JF4f AFWIyr97JF98KjkaLaAFLSUrUUUUUb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUIcSsGvfJTRUUUbfAFF20E14v26ryj6rWUM7CY07I20VC2zVCF04k26cxKx2IYs7xG 6rWj6s0DM7CIcVAFz4kK6r1j6r18M28IrcIa0xkI8VA2jI8067AKxVWUGwA2048vs2IY02 0Ec7CjxVAFwI0_JFI_Gr1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2x7M28EF7xv wVC0I7IYx2IY67AKxVW8JVW5JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwA2z4 x0Y4vEx4A2jsIE14v26F4UJVW0owA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE3s1le2I2 62IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcV AFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG 0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lc2xSY4AK67A8MxAIw28IcxkI7V AKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCj r7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6x IIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAI w20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x 0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7sRROJ53UUUUU== X-Originating-IP: [47.113.87.88] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiAwcLAGNzLGOBkwAAsC X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This testcase mix exist spill-1.c and adding new fun to check if there have redundant addi intructions. Idea provided by Jeff Law. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/spill-sp-adjust.c: New test. --- .../gcc.target/riscv/rvv/base/spill-sp-adjust.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c new file mode 100644 index 00000000000..0226554abf3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-sp-adjust.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv" } */ + +#include "spill-1.c" + +void +spill_sp_adjust (int8_t *v) +{ + vint8mf8_t v1 = *(vint8mf8_t*)v; +} + +/* Make sure we do not have a useless SP adjustment. */ +/* { dg-final { scan-assembler-not "addi\tsp,sp,0" } } */ From patchwork Tue Nov 15 08:33:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawei X-Patchwork-Id: 60628 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 82F07388E823 for ; Tue, 15 Nov 2022 08:34:44 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) by sourceware.org (Postfix) with ESMTP id CB521382D3B7 for ; Tue, 15 Nov 2022 08:34:16 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org CB521382D3B7 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [47.113.87.88]) by APP-01 (Coremail) with SMTP id qwCowABX92gDT3NjglDgCQ--.2434S4; Tue, 15 Nov 2022 16:34:13 +0800 (CST) From: jiawei To: gcc-patches@gcc.gnu.org Cc: kito.cheng@sifive.com, palmer@rivosinc.com, juzhe.zhong@rivai.ai, jeffreyalaw@gmail.com, christoph.muellner@vrull.eu, philipp.tomsich@vrull.eu, wuwei2016@iscas.ac.cn, jiawei Subject: [PATCH v2 2/2] RISC-V: Optimize RVV epilogue logic. Date: Tue, 15 Nov 2022 16:33:58 +0800 Message-Id: <20221115083358.4130952-3-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221115083358.4130952-1-jiawei@iscas.ac.cn> References: <20221115083358.4130952-1-jiawei@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: qwCowABX92gDT3NjglDgCQ--.2434S4 X-Coremail-Antispam: 1UD129KBjvJXoW7tw4xXw48GryfWr1DXFyfCrg_yoW8ZrWrpF s3WryfAF15Zwn3t3WftFW2kr1rWw4rGw15Cw1xJws3Aw4DWrW8WFsxKay3ZrWqgFWkA3s2 9F1qkFnI9a1fu3DanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUB214x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jryl82xGYIkIc2 x26xkF7I0E14v26r4j6ryUM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq3wAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY02Avz4vE174l42xK82IYc2 Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s02 6x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0x vE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4UMIIF0xvE 42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6x kF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjTRCUDGDUUUU X-Originating-IP: [47.113.87.88] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiCgULAGNy457TdAAEsL X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Sometimes "step1 -= scalable_frame" will cause adjust equal to zero. And it will generate additional redundant instruction "addi sp,sp,0". Add checking segement to skip that case. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_expand_epilogue): New check segement. --- gcc/config/riscv/riscv.cc | 35 +++++++++++++++++++---------------- 1 file changed, 19 insertions(+), 16 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 02a01ca0b7c..433b9b13eb6 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -5185,25 +5185,28 @@ riscv_expand_epilogue (int style) step1 -= scalable_frame; } - /* Get an rtx for STEP1 that we can add to BASE. */ - rtx adjust = GEN_INT (step1.to_constant ()); - if (!SMALL_OPERAND (step1.to_constant ())) - { - riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust); - adjust = RISCV_PROLOGUE_TEMP (Pmode); - } - - insn = emit_insn ( - gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, adjust)); - - rtx dwarf = NULL_RTX; - rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx, + /* Get an rtx for STEP1 that we can add to BASE. + Skip if adjust equal to zero. */ + if (step1.to_constant () != 0) + { + rtx adjust = GEN_INT (step1.to_constant ()); + if (!SMALL_OPERAND (step1.to_constant ())) + { + riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust); + adjust = RISCV_PROLOGUE_TEMP (Pmode); + } + + insn = emit_insn ( + gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, adjust)); + rtx dwarf = NULL_RTX; + rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (step2)); - dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf); - RTX_FRAME_RELATED_P (insn) = 1; + dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf); + RTX_FRAME_RELATED_P (insn) = 1; - REG_NOTES (insn) = dwarf; + REG_NOTES (insn) = dwarf; + } } else if (frame_pointer_needed) {