From patchwork Tue Nov 15 06:51:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiao Zeng X-Patchwork-Id: 60625 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A735C3830B19 for ; Tue, 15 Nov 2022 06:52:58 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from zg8tmja5ljk3lje4ms43mwaa.icoremail.net (zg8tmja5ljk3lje4ms43mwaa.icoremail.net [209.97.181.73]) by sourceware.org (Postfix) with SMTP id 821CB3830B3B for ; Tue, 15 Nov 2022 06:52:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 821CB3830B3B Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from user.DOMAINS (unknown [10.12.130.38]) by app1 (Coremail) with SMTP id EwgMCgB3PYYSN3NjF40RAA--.59816S5; Tue, 15 Nov 2022 14:52:04 +0800 (CST) From: zengxiao@eswincomputing.com To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, andrew@sifive.com, shihua@iscas.ac.cn, zengxiao , gaofei@eswincomputing.com Subject: [PATCH, V1 1/1] RISC-V: Make R_RISCV_SUB6 conforms to riscv abi standard Date: Tue, 15 Nov 2022 14:51:59 +0800 Message-Id: <20221115065159.2353620-2-zengxiao@eswincomputing.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221115065159.2353620-1-zengxiao@eswincomputing.com> References: <20221115065159.2353620-1-zengxiao@eswincomputing.com> MIME-Version: 1.0 X-CM-TRANSID: EwgMCgB3PYYSN3NjF40RAA--.59816S5 X-Coremail-Antispam: 1UD129KBjvJXoWxXry8XrWfKr47tF48JrWDurg_yoW5Zw47p3 WDJwn8KF4fJrsrtrs7tayUu3WSkw409FWF9w12qw47tr4kJryDtrn5tF17CFWDAFy8Cry5 ZrsY9F4Yk345Aw7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUP014x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r1Y6r1xM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_tr0E3s1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F4UJw A2z4x0Y4vEx4A2jsIE14v26rxl6s0DM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq3wAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwAKzVCY07xG64k0F24lc2xSY4 AK6svPMxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAF wI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc4 0Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AK xVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr 1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VU158n5UU UUU== X-CM-SenderInfo: p2hqw5xldrqvxvzl0uprps33xlqjhudrp/ X-Spam-Status: No, score=-10.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_VALIDITY_RPBL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: zengxiao This patch makes R_RISCV_SUB6 conforms to riscv abi standard. R_RISCV_SUB6 only the lower 6 bits of the code are valid. The proposed specification which can be found in 8.5. Relocations of, https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/download/v1.0-rc4/riscv-abi.pdf bfd/ChangeLog: * elfxx-riscv.c (riscv_elf_add_sub_reloc): binutils/ChangeLog: * testsuite/binutils-all/riscv/dwarf-SUB6.d: New test. * testsuite/binutils-all/riscv/dwarf-SUB6.s: New test. reviewed-by: gaofei@eswincomputing.com jinyanjiang@eswincomputing.com Signed-off-by: zengxiao --- bfd/elfxx-riscv.c | 7 +++++ .../testsuite/binutils-all/riscv/dwarf-SUB6.d | 31 +++++++++++++++++++ .../testsuite/binutils-all/riscv/dwarf-SUB6.s | 12 +++++++ 3 files changed, 50 insertions(+) create mode 100644 binutils/testsuite/binutils-all/riscv/dwarf-SUB6.d create mode 100644 binutils/testsuite/binutils-all/riscv/dwarf-SUB6.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 300ccf49534..e71d4a456f2 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -994,6 +994,13 @@ riscv_elf_add_sub_reloc (bfd *abfd, relocation = old_value + relocation; break; case R_RISCV_SUB6: + { + bfd_vma six_bit_valid_value = old_value & howto->dst_mask; + six_bit_valid_value -= relocation; + relocation = (six_bit_valid_value & howto->dst_mask) | + (old_value & ~howto->dst_mask); + } + break; case R_RISCV_SUB8: case R_RISCV_SUB16: case R_RISCV_SUB32: diff --git a/binutils/testsuite/binutils-all/riscv/dwarf-SUB6.d b/binutils/testsuite/binutils-all/riscv/dwarf-SUB6.d new file mode 100644 index 00000000000..47d5ae570d7 --- /dev/null +++ b/binutils/testsuite/binutils-all/riscv/dwarf-SUB6.d @@ -0,0 +1,31 @@ +#PROG: objcopy +#objdump: --dwarf=frames + +tmpdir/riscvcopy.o: file format elf32-littleriscv + +Contents of the .eh_frame section: + + +00000000 00000020 00000000 CIE + Version: 3 + Augmentation: "zR" + Code alignment factor: 1 + Data alignment factor: -4 + Return address column: 1 + Augmentation data: 1b + DW_CFA_def_cfa_register: r2 \(sp\) + DW_CFA_def_cfa_offset: 48 + DW_CFA_offset: r1 \(ra\) at cfa-4 + DW_CFA_offset: r8 \(s0\) at cfa-8 + DW_CFA_def_cfa: r8 \(s0\) ofs 0 + DW_CFA_restore: r1 \(ra\) + DW_CFA_restore: r8 \(s0\) + DW_CFA_def_cfa: r2 \(sp\) ofs 48 + DW_CFA_def_cfa_offset: 0 + DW_CFA_nop + +00000024 00000010 00000028 FDE cie=00000000 pc=0000002c..0000002c + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop + diff --git a/binutils/testsuite/binutils-all/riscv/dwarf-SUB6.s b/binutils/testsuite/binutils-all/riscv/dwarf-SUB6.s new file mode 100644 index 00000000000..fe959f59d9b --- /dev/null +++ b/binutils/testsuite/binutils-all/riscv/dwarf-SUB6.s @@ -0,0 +1,12 @@ + .attribute arch, "rv32i2p0_m2p0_a2p0_f2p0_c2p0" + .cfi_startproc + .cfi_def_cfa_offset 48 + .cfi_offset 1, -4 + .cfi_offset 8, -8 + .cfi_def_cfa 8, 0 + .cfi_restore 1 + .cfi_restore 8 + .cfi_def_cfa 2, 48 + .cfi_def_cfa_offset 0 + .cfi_endproc + \ No newline at end of file