From patchwork Mon Nov 14 07:52:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jakub Jelinek X-Patchwork-Id: 60574 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CBF3738518B8 for ; Mon, 14 Nov 2022 07:53:29 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CBF3738518B8 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1668412409; bh=0db71UpOuRAKnsJrJb4iVWsPHMSZ8eZyUMrvzIrUq5M=; h=Date:To:Cc:Subject:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=n//YHKcAo93HGccyPZ2KditxsKB/o4GGE7+BcMdEmqgIEICNIn2MtiLIdd7uJJlrc Xxpz31PbCEEzXpUD9t+TkwaTcD7Oq4C7xLgUZLXs3+n2sPwk4KiTU3sDaAqRdXQshu 2LBwRwSujVdE/pMzybrtAwRfkjFatfnqpYR+cy1M= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by sourceware.org (Postfix) with ESMTPS id CA6AF3856975 for ; Mon, 14 Nov 2022 07:52:58 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org CA6AF3856975 Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-86-F1Nj2ZEDNjGAxMxjSrDSQQ-1; Mon, 14 Nov 2022 02:52:55 -0500 X-MC-Unique: F1Nj2ZEDNjGAxMxjSrDSQQ-1 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.rdu2.redhat.com [10.11.54.7]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 2237085A59D; Mon, 14 Nov 2022 07:52:55 +0000 (UTC) Received: from tucnak.zalov.cz (unknown [10.39.192.38]) by smtp.corp.redhat.com (Postfix) with ESMTPS id C85BA140EBF5; Mon, 14 Nov 2022 07:52:54 +0000 (UTC) Received: from tucnak.zalov.cz (localhost [127.0.0.1]) by tucnak.zalov.cz (8.17.1/8.17.1) with ESMTPS id 2AE7qogf2822446 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NOT); Mon, 14 Nov 2022 08:52:50 +0100 Received: (from jakub@localhost) by tucnak.zalov.cz (8.17.1/8.17.1/Submit) id 2AE7qnjN2822445; Sun, 13 Nov 2022 19:52:49 -1200 Date: Sun, 13 Nov 2022 19:52:49 -1200 To: Uros Bizjak Cc: gcc-patches@gcc.gnu.org, Florian Weimer , "H.J. Lu" Subject: [PATCH] i386: Emit 16b atomics inline with -m64 -mcx16 -mavx [PR104688] Message-ID: MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.7 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Disposition: inline X-Spam-Status: No, score=-3.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jakub Jelinek via Gcc-patches From: Jakub Jelinek Reply-To: Jakub Jelinek Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Hi! Working virtually out of Baker Island. Given https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688#c10 the following patch implements atomic load/store (and therefore also enabling compare and exchange) for -m64 -mcx16 -mavx. Ok for trunk if it passes bootstrap/regtest? 2022-11-13 Jakub Jelinek PR target/104688 * config/i386/sync.md (atomic_loadti, atomic_storeti): New define_expand patterns. (atomic_loadti_1, atomic_storeti_1): New define_insn patterns. * gcc.target/i386/pr104688-1.c: New test. * gcc.target/i386/pr104688-2.c: New test. * gcc.target/i386/pr104688-3.c: New test. Jakub --- gcc/config/i386/sync.md.jj 2022-11-07 20:54:37.259400942 -1200 +++ gcc/config/i386/sync.md 2022-11-13 19:27:22.977987355 -1200 @@ -225,6 +225,31 @@ (define_insn_and_split "atomic_loaddi_fp DONE; }) +;; Intel SDM guarantees that 16-byte VMOVDQA on 16-byte aligned address +;; is atomic. AMD will give a similar guarantee. +(define_expand "atomic_loadti" + [(set (match_operand:TI 0 "register_operand" "=x,Yv") + (unspec:TI [(match_operand:TI 1 "memory_operand" "m,m") + (match_operand:SI 2 "const_int_operand")] + UNSPEC_LDA))] + "TARGET_64BIT && TARGET_CMPXCHG16B && TARGET_AVX" +{ + emit_insn (gen_atomic_loadti_1 (operands[0], operands[1])); + DONE; +}) + +(define_insn "atomic_loadti_1" + [(set (match_operand:TI 0 "register_operand" "=x,Yv") + (unspec:TI [(match_operand:TI 1 "memory_operand" "m,m")] + UNSPEC_LDA))] + "TARGET_64BIT && TARGET_CMPXCHG16B && TARGET_AVX" + "@ + vmovdqa\t{%1, %0|%0, %1} + vmovdqa64\t{%1, %0|%0, %1}" + [(set_attr "type" "ssemov") + (set_attr "prefix" "vex,evex") + (set_attr "mode" "TI")]) + (define_expand "atomic_store" [(set (match_operand:ATOMIC 0 "memory_operand") (unspec:ATOMIC [(match_operand:ATOMIC 1 "nonimmediate_operand") @@ -276,6 +301,36 @@ (define_insn "atomic_store_1" "" "%K2mov{}\t{%1, %0|%0, %1}") +(define_expand "atomic_storeti" + [(set (match_operand:TI 0 "memory_operand") + (unspec:TI [(match_operand:TI 1 "register_operand") + (match_operand:SI 2 "const_int_operand")] + UNSPEC_STA))] + "TARGET_64BIT && TARGET_CMPXCHG16B && TARGET_AVX" +{ + enum memmodel model = memmodel_from_int (INTVAL (operands[2])); + + emit_insn (gen_atomic_storeti_1 (operands[0], operands[1], operands[2])); + + /* ... followed by an MFENCE, if required. */ + if (is_mm_seq_cst (model)) + emit_insn (gen_mem_thread_fence (operands[2])); + DONE; +}) + +(define_insn "atomic_storeti_1" + [(set (match_operand:TI 0 "memory_operand" "=m,m") + (unspec:TI [(match_operand:TI 1 "register_operand" "x,Yv") + (match_operand:SI 2 "const_int_operand")] + UNSPEC_STA))] + "" + "@ + %K2vmovdqa\t{%1, %0|%0, %1} + %K2vmovdqa64\t{%1, %0|%0, %1}" + [(set_attr "type" "ssemov") + (set_attr "prefix" "vex,evex") + (set_attr "mode" "TI")]) + (define_insn_and_split "atomic_storedi_fpu" [(set (match_operand:DI 0 "memory_operand" "=m,m,m") (unspec:DI [(match_operand:DI 1 "nonimmediate_operand" "x,m,?r")] --- gcc/testsuite/gcc.target/i386/pr104688-1.c.jj 2022-11-13 19:36:43.251332612 -1200 +++ gcc/testsuite/gcc.target/i386/pr104688-1.c 2022-11-13 19:40:22.649334650 -1200 @@ -0,0 +1,34 @@ +/* PR target/104688 */ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O2 -mno-cx16" } */ +/* { dg-final { scan-assembler "\t__sync_val_compare_and_swap_16" } } */ +/* { dg-final { scan-assembler "\t__atomic_load_16" } } */ +/* { dg-final { scan-assembler "\t__atomic_store_16" } } */ +/* { dg-final { scan-assembler "\t__atomic_compare_exchange_16" } } */ + +__int128 v; + +__int128 +f1 (void) +{ + return __sync_val_compare_and_swap (&v, 42, 0); +} + +__int128 +f2 (void) +{ + return __atomic_load_n (&v, __ATOMIC_SEQ_CST); +} + +void +f3 (__int128 x) +{ + __atomic_store_n (&v, 42, __ATOMIC_SEQ_CST); +} + +__int128 +f4 (void) +{ + __int128 y = 42; + __atomic_compare_exchange_n (&v, &y, 0, 0, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); +} --- gcc/testsuite/gcc.target/i386/pr104688-2.c.jj 2022-11-13 19:36:46.513288025 -1200 +++ gcc/testsuite/gcc.target/i386/pr104688-2.c 2022-11-13 19:40:34.676170305 -1200 @@ -0,0 +1,34 @@ +/* PR target/104688 */ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O2 -mno-avx" } */ +/* { dg-final { scan-assembler "\t__sync_val_compare_and_swap_16" } } */ +/* { dg-final { scan-assembler "\t__atomic_load_16" } } */ +/* { dg-final { scan-assembler "\t__atomic_store_16" } } */ +/* { dg-final { scan-assembler "\t__atomic_compare_exchange_16" } } */ + +__int128 v; + +__int128 +f1 (void) +{ + return __sync_val_compare_and_swap (&v, 42, 0); +} + +__int128 +f2 (void) +{ + return __atomic_load_n (&v, __ATOMIC_SEQ_CST); +} + +void +f3 (__int128 x) +{ + __atomic_store_n (&v, 42, __ATOMIC_SEQ_CST); +} + +__int128 +f4 (void) +{ + __int128 y = 42; + __atomic_compare_exchange_n (&v, &y, 0, 0, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); +} --- gcc/testsuite/gcc.target/i386/pr104688-3.c.jj 2022-11-13 19:37:00.899091450 -1200 +++ gcc/testsuite/gcc.target/i386/pr104688-3.c 2022-11-13 19:40:41.984070460 -1200 @@ -0,0 +1,34 @@ +/* PR target/104688 */ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O2 -mcx16 -mavx" } */ +/* { dg-final { scan-assembler-not "\t__sync_val_compare_and_swap_16" } } */ +/* { dg-final { scan-assembler-not "\t__atomic_load_16" } } */ +/* { dg-final { scan-assembler-not "\t__atomic_store_16" } } */ +/* { dg-final { scan-assembler-not "\t__atomic_compare_exchange_16" } } */ + +__int128 v; + +__int128 +f1 (void) +{ + return __sync_val_compare_and_swap (&v, 42, 0); +} + +__int128 +f2 (void) +{ + return __atomic_load_n (&v, __ATOMIC_SEQ_CST); +} + +void +f3 (__int128 x) +{ + __atomic_store_n (&v, 42, __ATOMIC_SEQ_CST); +} + +__int128 +f4 (void) +{ + __int128 y = 42; + __atomic_compare_exchange_n (&v, &y, 0, 0, __ATOMIC_SEQ_CST, __ATOMIC_SEQ_CST); +}