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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id lb17-20020a170907785100b00734bfab4d59sm3432282ejc.170.2022.11.13.13.46.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 13:46:42 -0800 (PST) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH 1/7] riscv: Add basic XThead* vendor extension support Date: Sun, 13 Nov 2022 22:46:30 +0100 Message-Id: <20221113214636.2747737-2-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221113214636.2747737-1-christoph.muellner@vrull.eu> References: <20221113214636.2747737-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_MANYTO, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Christoph Müllner This patch add basic support for the following XThead* ISA extensions: * XTheadCmo, XTheadSync * XTheadBa, XTheadBb, XTheadBs, XTheadCondMov * XTheadMac * XTheadFMemIdx, XTheadMemIdx gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add xthead* extensions. * config/riscv/riscv-opts.h (MASK_XTHEADBA): New. (TARGET_XTHEADBA): New. (MASK_XTHEADBB): New. (TARGET_XTHEADBB): New. (MASK_XTHEADBS): New. (TARGET_XTHEADBS): New. (MASK_XTHEADCMO): New. (TARGET_XTHEADCMO): New. (MASK_XTHEADCONDMOV): New. (TARGET_XTHEADCONDMOV): New. (MASK_XTHEADFMEMIDX): New. (TARGET_XTHEADFMEMIDX): New. (MASK_XTHEADMAC): New. (TARGET_XTHEADMAC): New. (MASK_XTHEADMEMIDX): New. (TARGET_XTHEADMEMIDX): New. (MASK_XTHEADSYNC): New. (TARGET_XTHEADSYNC): New. * config/riscv/riscv.opt: Add riscv_xthead_subext. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadba.c: New test. * gcc.target/riscv/xtheadbb.c: New test. * gcc.target/riscv/xtheadbs.c: New test. * gcc.target/riscv/xtheadcmo.c: New test. * gcc.target/riscv/xtheadcondmov.c: New test. * gcc.target/riscv/xtheadfmemidx.c: New test. * gcc.target/riscv/xtheadmac.c: New test. * gcc.target/riscv/xtheadmemidx.c: New test. * gcc.target/riscv/xtheadsync.c: New test. Signed-off-by: Christoph Müllner --- gcc/common/config/riscv/riscv-common.cc | 20 +++++++++++++++++++ gcc/config/riscv/riscv-opts.h | 19 ++++++++++++++++++ gcc/config/riscv/riscv.opt | 3 +++ gcc/testsuite/gcc.target/riscv/xtheadba.c | 13 ++++++++++++ gcc/testsuite/gcc.target/riscv/xtheadbb.c | 13 ++++++++++++ gcc/testsuite/gcc.target/riscv/xtheadbs.c | 13 ++++++++++++ gcc/testsuite/gcc.target/riscv/xtheadcmo.c | 13 ++++++++++++ .../gcc.target/riscv/xtheadcondmov.c | 13 ++++++++++++ .../gcc.target/riscv/xtheadfmemidx.c | 13 ++++++++++++ gcc/testsuite/gcc.target/riscv/xtheadmac.c | 13 ++++++++++++ gcc/testsuite/gcc.target/riscv/xtheadmemidx.c | 13 ++++++++++++ gcc/testsuite/gcc.target/riscv/xtheadsync.c | 13 ++++++++++++ 12 files changed, 159 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbs.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcmo.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmemidx.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmac.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmemidx.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadsync.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 4b7f777c103..8e1449d3543 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -222,6 +222,16 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"svinval", ISA_SPEC_CLASS_NONE, 1, 0}, {"svnapot", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xtheadba", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xtheadbb", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xtheadbs", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xtheadcmo", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xtheadcondmov", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xtheadfmemidx", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xtheadmac", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0}, + /* Terminate the list. */ {NULL, ISA_SPEC_CLASS_NONE, 0, 0} }; @@ -1247,6 +1257,16 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"svinval", &gcc_options::x_riscv_sv_subext, MASK_SVINVAL}, {"svnapot", &gcc_options::x_riscv_sv_subext, MASK_SVNAPOT}, + {"xtheadba", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBA}, + {"xtheadbb", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBB}, + {"xtheadbs", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADBS}, + {"xtheadcmo", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADCMO}, + {"xtheadcondmov", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADCONDMOV}, + {"xtheadfmemidx", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADFMEMIDX}, + {"xtheadmac", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMAC}, + {"xtheadmemidx", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMIDX}, + {"xtheadsync", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADSYNC}, + {NULL, NULL, 0} }; diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 25fd85b09b1..18daac40dbd 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -189,4 +189,23 @@ enum stack_protector_guard { ? 0 \ : 32 << (__builtin_popcount (riscv_zvl_flags) - 1)) +#define MASK_XTHEADBA (1 << 0) +#define TARGET_XTHEADBA ((riscv_xthead_subext & MASK_XTHEADBA) != 0) +#define MASK_XTHEADBB (1 << 1) +#define TARGET_XTHEADBB ((riscv_xthead_subext & MASK_XTHEADBB) != 0) +#define MASK_XTHEADBS (1 << 2) +#define TARGET_XTHEADBS ((riscv_xthead_subext & MASK_XTHEADBS) != 0) +#define MASK_XTHEADCMO (1 << 3) +#define TARGET_XTHEADCMO ((riscv_xthead_subext & MASK_XTHEADCMO) != 0) +#define MASK_XTHEADCONDMOV (1 << 4) +#define TARGET_XTHEADCONDMOV ((riscv_xthead_subext & MASK_XTHEADCONDMOV) != 0) +#define MASK_XTHEADFMEMIDX (1 << 5) +#define TARGET_XTHEADFMEMIDX ((riscv_xthead_subext & MASK_XTHEADFMEMIDX) != 0) +#define MASK_XTHEADMAC (1 << 6) +#define TARGET_XTHEADMAC ((riscv_xthead_subext & MASK_XTHEADMAC) != 0) +#define MASK_XTHEADMEMIDX (1 << 7) +#define TARGET_XTHEADMEMIDX ((riscv_xthead_subext & MASK_XTHEADMEMIDX) != 0) +#define MASK_XTHEADSYNC (1 << 8) +#define TARGET_XTHEADSYNC ((riscv_xthead_subext & MASK_XTHEADSYNC) != 0) + #endif /* ! GCC_RISCV_OPTS_H */ diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 7c3ca48d1cc..3f2dd24d59b 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -233,6 +233,9 @@ int riscv_zm_subext TargetVariable int riscv_sv_subext +TargetVariable +int riscv_xthead_subext + Enum Name(isa_spec_class) Type(enum riscv_isa_spec_class) Supported ISA specs (for use with the -misa-spec= option): diff --git a/gcc/testsuite/gcc.target/riscv/xtheadba.c b/gcc/testsuite/gcc.target/riscv/xtheadba.c new file mode 100644 index 00000000000..c91b95b94a8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadba.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xtheadba" { target { rv64 } } } */ + +#ifndef __riscv_xtheadba +#error Feature macro not defined +#endif + +int +foo (int a) +{ + return a; +} + diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb.c b/gcc/testsuite/gcc.target/riscv/xtheadbb.c new file mode 100644 index 00000000000..4872faa999d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadbb.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xtheadbb" { target { rv64 } } } */ + +#ifndef __riscv_xtheadbb +#error Feature macro not defined +#endif + +int +foo (int a) +{ + return a; +} + diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbs.c b/gcc/testsuite/gcc.target/riscv/xtheadbs.c new file mode 100644 index 00000000000..9350505ebb1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadbs.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xtheadbs" { target { rv64 } } } */ + +#ifndef __riscv_xtheadbs +#error Feature macro not defined +#endif + +int +foo (int a) +{ + return a; +} + diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcmo.c b/gcc/testsuite/gcc.target/riscv/xtheadcmo.c new file mode 100644 index 00000000000..ce56f9a1277 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadcmo.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xtheadcmo" { target { rv64 } } } */ + +#ifndef __riscv_xtheadcmo +#error Feature macro not defined +#endif + +int +foo (int a) +{ + return a; +} + diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov.c new file mode 100644 index 00000000000..9324b30f6bd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xtheadcondmov" { target { rv64 } } } */ + +#ifndef __riscv_xtheadcondmov +#error Feature macro not defined +#endif + +int +foo (int a) +{ + return a; +} + diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmemidx.c b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx.c new file mode 100644 index 00000000000..9e69ee45cad --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmemidx.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xtheadfmemidx" { target { rv64 } } } */ + +#ifndef __riscv_xtheadfmemidx +#error Feature macro not defined +#endif + +int +foo (int a) +{ + return a; +} + diff --git a/gcc/testsuite/gcc.target/riscv/xtheadmac.c b/gcc/testsuite/gcc.target/riscv/xtheadmac.c new file mode 100644 index 00000000000..d8f356bbdec --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadmac.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xtheadmac" { target { rv64 } } } */ + +#ifndef __riscv_xtheadmac +#error Feature macro not defined +#endif + +int +foo (int a) +{ + return a; +} + diff --git a/gcc/testsuite/gcc.target/riscv/xtheadmemidx.c b/gcc/testsuite/gcc.target/riscv/xtheadmemidx.c new file mode 100644 index 00000000000..bd1545c0c24 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadmemidx.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xtheadmemidx" { target { rv64 } } } */ + +#ifndef __riscv_xtheadmemidx +#error Feature macro not defined +#endif + +int +foo (int a) +{ + return a; +} + diff --git a/gcc/testsuite/gcc.target/riscv/xtheadsync.c b/gcc/testsuite/gcc.target/riscv/xtheadsync.c new file mode 100644 index 00000000000..e51457e5376 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadsync.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xtheadsync" { target { rv64 } } } */ + +#ifndef __riscv_xtheadsync +#error Feature macro not defined +#endif + +int +foo (int a) +{ + return a; +} + From patchwork Sun Nov 13 21:46:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 60553 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 86F39389EC54 for ; Sun, 13 Nov 2022 21:47:06 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) by sourceware.org (Postfix) with ESMTPS id B88893857BB3 for ; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id lb17-20020a170907785100b00734bfab4d59sm3432282ejc.170.2022.11.13.13.46.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 13:46:43 -0800 (PST) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH 2/7] riscv: riscv-cores.def: Add T-Head XuanTie C906 Date: Sun, 13 Nov 2022 22:46:31 +0100 Message-Id: <20221113214636.2747737-3-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221113214636.2747737-1-christoph.muellner@vrull.eu> References: <20221113214636.2747737-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_MANYTO, KAM_NUMSUBJECT, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Christoph Müllner This adds T-Head's XuanTie C906 to the list of known cores as "thead-c906". The C906 is shipped for quite some time (it is the core of the Allwinner D1). Note, that the tuning struct for the C906 is already part of GCC (it is also name "thead-c906"). gcc/ChangeLog: * config/riscv/riscv-cores.def (RISCV_CORE): Add "thead-c906". gcc/testsuite/ChangeLog: * gcc.target/riscv/mcpu-thead-c906.c: New test. Signed-off-by: Christoph Müllner --- gcc/config/riscv/riscv-cores.def | 2 ++ .../gcc.target/riscv/mcpu-thead-c906.c | 18 ++++++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index 31ad34682c5..648a010e09b 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -73,4 +73,6 @@ RISCV_CORE("sifive-s76", "rv64imafdc", "sifive-7-series") RISCV_CORE("sifive-u54", "rv64imafdc", "sifive-5-series") RISCV_CORE("sifive-u74", "rv64imafdc", "sifive-7-series") +RISCV_CORE("thead-c906", "rv64imafdc", "thead-c906") + #undef RISCV_CORE diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c b/gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c new file mode 100644 index 00000000000..f579e7e2215 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ +/* { dg-options "-mcpu=thead-c906" { target { rv64 } } } */ +/* T-Head XuanTie C906 => rv64imafdc */ + +#if !((__riscv_xlen == 64) \ + && !defined(__riscv_32e) \ + && defined(__riscv_mul) \ + && defined(__riscv_atomic) \ + && (__riscv_flen == 64) \ + && defined(__riscv_compressed)) +#error "unexpected arch" +#endif + +int main() +{ + return 0; +} From patchwork Sun Nov 13 21:46:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 60556 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DDE803954412 for ; Sun, 13 Nov 2022 21:47:38 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by sourceware.org (Postfix) with ESMTPS id 1D4F1385782B for ; Sun, 13 Nov 2022 21:46:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 1D4F1385782B Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-ej1-x629.google.com with SMTP id m22so24073759eji.10 for ; Sun, 13 Nov 2022 13:46:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9OlnRIYUmb6Gx6yr98t0RsEMZDKjVP0+mzFMPVvXL9U=; b=l+nHeNAJVl22PIEGaPM/x2XOWp9s+agROOn8nMrVZMZyjpHUncr83na+0hxGyIBTzR akeIVaOLxyDfY4s/5norONfGILftvCJrntzWKcPKLVHTytDW45vssVyuzQdgKhWqRkwt rpMYOPy+RjpzZminHtFmXP8Ckg9UJrTd28eSuRPH0h0Mei1rCrsT5UUacHn4yH0N0bxK H95xm0Dqks2Rr2iU9pI21SrSmH/3caCgX6helkJcnhfnW0DpsbjbGenqmNiYVupm0uB/ nTy7B6kqm8Y3xFyeddMyTU6f1CWkKu+XHE+HlUgXUPVDFPfi4bfdwlJ5bHaBKlSf3DwP sN7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9OlnRIYUmb6Gx6yr98t0RsEMZDKjVP0+mzFMPVvXL9U=; b=4iZoa18oDkUn4710zy+2d76MrEggzv3+Lwh+HQv/jbvWIlDGexbAjM4Igw3vzNs253 DeC31VFdIQDkx/KYbCee+W9eCuKZEqIMNNS24LLPO/Z++tVoeZoRdxAoQVHPRzSNOS9b UzgDbKjO/q1j00TCnYtsPMgEFXCmJa3yhH40bQa6iRQUNX9i2sNNexd6mydXGUjXU4wQ /jF3p7KsMHltaKE+ZBiPTpEsRqkaMVm/X8Pcm0nIoJC9h1JfLMB/6pZX4HJup+B7vZrt RIoXSa7Pe0Hk+jy+wF2/t+sXEsixLDZsX7+GKH3EUDvSMDWt6UwSLbBHE8eU2HcOi/m4 TU2w== X-Gm-Message-State: ANoB5plA0YSnxx2xkz53lQ4lMnWWxyRKj0DnL1qORvlLW++lD7//vBYd S2LtksFiTxu/U4l/vln66+GsssWrswFEHOpo X-Google-Smtp-Source: AA0mqf5i5IDpY+nkf9c29CPD0q8EQzpplocr1DwUx2NSH8Mq3fyKENIse3S1lhcFUITODrkiuh0D8w== X-Received: by 2002:a17:907:7672:b0:7ad:c35a:ad76 with SMTP id kk18-20020a170907767200b007adc35aad76mr8558303ejc.705.1668376005468; Sun, 13 Nov 2022 13:46:45 -0800 (PST) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id lb17-20020a170907785100b00734bfab4d59sm3432282ejc.170.2022.11.13.13.46.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 13:46:45 -0800 (PST) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH 3/7] riscv: thead: Add support for XTheadBa and XTheadBs ISA extensions Date: Sun, 13 Nov 2022 22:46:32 +0100 Message-Id: <20221113214636.2747737-4-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221113214636.2747737-1-christoph.muellner@vrull.eu> References: <20221113214636.2747737-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_MANYTO, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Christoph Müllner This patch adds support for the following T-Head vendor extensions: * XTheadBa * XTheadBs Both extensions provide just one instruction, that has a counterpart in the similar named Bitmanip ISA extension. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_rtx_costs): Adjust for th.tst. * config/riscv/riscv.md: Include thead.md. * config/riscv/thead.md: New file. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadba-addsl-64.c: New test. * gcc.target/riscv/xtheadba-addsl.c: New test. * gcc.target/riscv/xtheadbs-tst.c: New test. Signed-off-by: Christoph Müllner --- gcc/config/riscv/riscv.cc | 4 +- gcc/config/riscv/riscv.md | 1 + gcc/config/riscv/thead.md | 38 +++++++++++++++++++ .../gcc.target/riscv/xtheadba-addsl-64.c | 18 +++++++++ .../gcc.target/riscv/xtheadba-addsl.c | 20 ++++++++++ gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c | 12 ++++++ 6 files changed, 91 insertions(+), 2 deletions(-) create mode 100644 gcc/config/riscv/thead.md create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba-addsl-64.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 02a01ca0b7c..decade0fedd 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2369,8 +2369,8 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN *total = COSTS_N_INSNS (SINGLE_SHIFT_COST); return true; } - /* bext pattern for zbs. */ - if (TARGET_ZBS && outer_code == SET + /* bit extraction pattern (zbs:bext, xtheadbs:tst). */ + if ((TARGET_ZBS || TARGET_XTHEADBS) && outer_code == SET && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 1) { diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 798f7370a08..a9254df7820 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -3009,3 +3009,4 @@ (define_insn "riscv_prefetchi_" (include "generic.md") (include "sifive-7.md") (include "vector.md") +(include "thead.md") diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md new file mode 100644 index 00000000000..676d10b71d7 --- /dev/null +++ b/gcc/config/riscv/thead.md @@ -0,0 +1,38 @@ +;; Machine description for T-Head vendor extensions +;; Copyright (C) 2021-2022 Free Software Foundation, Inc. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +(define_insn "*th_addsl" + [(set (match_operand:X 0 "register_operand" "=r") + (plus:X (ashift:X (match_operand:X 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "I")) + (match_operand:X 3 "register_operand" "r")))] + "TARGET_XTHEADBA + && (INTVAL (operands[2]) >= 0) && (INTVAL (operands[2]) <= 3)" + "th.addsl\t%0,%1,%3,%2" + [(set_attr "type" "bitmanip") + (set_attr "mode" "")]) + +(define_insn "*th_tst" + [(set (match_operand:X 0 "register_operand" "=r") + (zero_extract:X (match_operand:X 1 "register_operand" "r") + (const_int 1) + (match_operand 2 "immediate_operand" "i")))] + "TARGET_XTHEADBS" + "th.tst\t%0,%1,%2" + [(set_attr "type" "bitmanip")]) diff --git a/gcc/testsuite/gcc.target/riscv/xtheadba-addsl-64.c b/gcc/testsuite/gcc.target/riscv/xtheadba-addsl-64.c new file mode 100644 index 00000000000..7f47929967a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadba-addsl-64.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xtheadba -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +/* RV64 only. */ +int foos(short *x, int n){ + return x[n]; +} +int fooi(int *x, int n){ + return x[n]; +} +int fooll(long long *x, int n){ + return x[n]; +} + +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,1" 1 } } */ +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,2" 1 } } */ +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,3" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c b/gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c new file mode 100644 index 00000000000..d739f715430 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadba-addsl.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xtheadba -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +long test_1(long a, long b) +{ + return a + (b << 1); +} +long test_2(long a, long b) +{ + return a + (b << 2); +} +long test_3(long a, long b) +{ + return a + (b << 3); +} + +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,1" 1 } } */ +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,2" 1 } } */ +/* { dg-final { scan-assembler-times "th.addsl\[ \t\]*a\[0-9\]+,a\[0-9\]+,a\[0-9\]+,3" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c b/gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c new file mode 100644 index 00000000000..f4887bde535 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xtheadbs -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +long +foo1 (long i) +{ + return 1L & (i >> 20); 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id lb17-20020a170907785100b00734bfab4d59sm3432282ejc.170.2022.11.13.13.46.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 13:46:46 -0800 (PST) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH 4/7] riscv: thead: Add support for XTheadCondMov ISA extensions Date: Sun, 13 Nov 2022 22:46:33 +0100 Message-Id: <20221113214636.2747737-5-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221113214636.2747737-1-christoph.muellner@vrull.eu> References: <20221113214636.2747737-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_MANYTO, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Christoph Müllner This patch adds support for XTheadCondMov ISA extension. The extension brings a one-sided conditional move (no else-assignment). Given that GCC has a great if-conversion pass, we don't need to do much, besides properly expanding movcc accordingly and adjust the cost model. gcc/ChangeLog: * config/riscv/iterators.md (TARGET_64BIT): Add GPR2 iterator. * config/riscv/riscv.cc (riscv_rtx_costs): Add costs for XTheadCondMov. (riscv_expand_conditional_move_onesided): New function. (riscv_expand_conditional_move): New function. * config/riscv/riscv.md: Add support for XTheadCondMov. * config/riscv/thead.md (*th_cond_mov): Add support for XTheadCondMov. (*th_cond_gpr_mov): Likewise. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadcondmov-mveqz-imm-eqz.c: New test. * gcc.target/riscv/xtheadcondmov-mveqz-imm-not.c: New test. * gcc.target/riscv/xtheadcondmov-mveqz-reg-eqz.c: New test. * gcc.target/riscv/xtheadcondmov-mveqz-reg-not.c: New test. * gcc.target/riscv/xtheadcondmov-mvnez-imm-cond.c: New test. * gcc.target/riscv/xtheadcondmov-mvnez-imm-nez.c: New test. * gcc.target/riscv/xtheadcondmov-mvnez-reg-cond.c: New test. * gcc.target/riscv/xtheadcondmov-mvnez-reg-nez.c: New test. Signed-off-by: Christoph Müllner --- gcc/config/riscv/iterators.md | 4 ++ gcc/config/riscv/riscv.cc | 53 ++++++++++++++++--- gcc/config/riscv/riscv.md | 7 +-- gcc/config/riscv/thead.md | 35 ++++++++++++ .../riscv/xtheadcondmov-mveqz-imm-eqz.c | 37 +++++++++++++ .../riscv/xtheadcondmov-mveqz-imm-not.c | 37 +++++++++++++ .../riscv/xtheadcondmov-mveqz-reg-eqz.c | 37 +++++++++++++ .../riscv/xtheadcondmov-mveqz-reg-not.c | 37 +++++++++++++ .../riscv/xtheadcondmov-mvnez-imm-cond.c | 37 +++++++++++++ .../riscv/xtheadcondmov-mvnez-imm-nez.c | 37 +++++++++++++ .../riscv/xtheadcondmov-mvnez-reg-cond.c | 37 +++++++++++++ .../riscv/xtheadcondmov-mvnez-reg-nez.c | 37 +++++++++++++ 12 files changed, 386 insertions(+), 9 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-eqz.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-not.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-eqz.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-not.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-cond.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-nez.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-cond.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-nez.c diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md index 50380ecfac9..3932eab14fa 100644 --- a/gcc/config/riscv/iterators.md +++ b/gcc/config/riscv/iterators.md @@ -26,6 +26,10 @@ ;; from the same template. (define_mode_iterator GPR [SI (DI "TARGET_64BIT")]) +;; A copy of GPR that can be used when a pattern has two independent +;; modes. +(define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")]) + ;; This mode iterator allows :P to be used for patterns that operate on ;; pointer-sized quantities. Exactly one of the two alternatives will match. (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")]) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index decade0fedd..9a795264e00 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2269,8 +2269,8 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN return false; case IF_THEN_ELSE: - if (TARGET_SFB_ALU - && register_operand (XEXP (x, 1), mode) + if ((TARGET_SFB_ALU || TARGET_XTHEADCONDMOV) + && reg_or_0_operand (XEXP (x, 1), mode) && sfb_alu_operand (XEXP (x, 2), mode) && comparison_operator (XEXP (x, 0), VOIDmode)) { @@ -3231,16 +3231,57 @@ riscv_expand_conditional_branch (rtx label, rtx_code code, rtx op0, rtx op1) emit_jump_insn (gen_condjump (condition, label)); } +/* Helper to emit two one-sided conditional moves for the movecc. */ + +static void +riscv_expand_conditional_move_onesided (rtx dest, rtx cons, rtx alt, + rtx_code code, rtx op0, rtx op1) +{ + machine_mode mode = GET_MODE (dest); + + gcc_assert (GET_MODE_CLASS (mode) == MODE_INT); + gcc_assert (reg_or_0_operand (cons, mode)); + gcc_assert (reg_or_0_operand (alt, mode)); + + riscv_emit_int_compare (&code, &op0, &op1); + rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1); + + rtx tmp1 = gen_reg_rtx (mode); + rtx tmp2 = gen_reg_rtx (mode); + + emit_insn (gen_rtx_SET (tmp1, gen_rtx_IF_THEN_ELSE (mode, cond, + cons, const0_rtx))); + + /* We need to expand a sequence for both blocks and we do that such, + that the second conditional move will use the inverted condition. + We use temporaries that are or'd to the dest register. */ + cond = gen_rtx_fmt_ee ((code == EQ) ? NE : EQ, GET_MODE (op0), op0, op1); + emit_insn (gen_rtx_SET (tmp2, gen_rtx_IF_THEN_ELSE (mode, cond, + alt, const0_rtx))); + + emit_insn (gen_rtx_SET (dest, gen_rtx_IOR (mode, tmp1, tmp2))); + } + /* If (CODE OP0 OP1) holds, move CONS to DEST; else move ALT to DEST. */ void riscv_expand_conditional_move (rtx dest, rtx cons, rtx alt, rtx_code code, rtx op0, rtx op1) { - riscv_emit_int_compare (&code, &op0, &op1); - rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1); - emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (GET_MODE (dest), cond, - cons, alt))); + machine_mode mode = GET_MODE (dest); + + if (TARGET_XTHEADCONDMOV + && GET_MODE_CLASS (mode) == MODE_INT + && reg_or_0_operand (cons, mode) + && reg_or_0_operand (alt, mode)) + riscv_expand_conditional_move_onesided (dest, cons, alt, code, op0, op1); + else + { + riscv_emit_int_compare (&code, &op0, &op1); + rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1); + emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (GET_MODE (dest), + cond, cons, alt))); + } } /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index a9254df7820..850a2d958e4 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -233,6 +233,7 @@ (define_attr "enabled" "no,yes" ;; nop no operation ;; ghost an instruction that produces no real code ;; bitmanip bit manipulation instructions +;; condmove conditional moves ;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler. ;; rdvlenb vector byte length vlenb csrr read ;; rdvl vector length vl csrr read @@ -324,7 +325,7 @@ (define_attr "type" "unknown,branch,jump,call,load,fpload,store,fpstore, mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate, - atomic,rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts, + atomic,condmove,rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts, vldux,vldox,vstux,vstox,vldff,vldr,vstr, vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp, vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,vimov, @@ -2223,9 +2224,9 @@ (define_insn "*branch" (define_expand "movcc" [(set (match_operand:GPR 0 "register_operand") (if_then_else:GPR (match_operand 1 "comparison_operator") - (match_operand:GPR 2 "register_operand") + (match_operand:GPR 2 "reg_or_0_operand") (match_operand:GPR 3 "sfb_alu_operand")))] - "TARGET_SFB_ALU" + "TARGET_SFB_ALU || TARGET_XTHEADCONDMOV" { rtx cmp = operands[1]; /* We only handle word mode integer compares for now. */ diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md index 676d10b71d7..e9a6c1eeb71 100644 --- a/gcc/config/riscv/thead.md +++ b/gcc/config/riscv/thead.md @@ -36,3 +36,38 @@ (define_insn "*th_tst" "TARGET_XTHEADBS" "th.tst\t%0,%1,%2" [(set_attr "type" "bitmanip")]) + +(define_insn "*th_cond_mov" + [(set (match_operand:GPR 0 "register_operand" "=r,r") + (if_then_else:GPR + (match_operator 4 "equality_operator" + [(match_operand:GPR2 1 "register_operand" "r,r") + (const_int 0)]) + (match_operand:GPR 2 "reg_or_0_operand" "rJ,0") + (match_operand:GPR 3 "reg_or_0_operand" "0,rJ")))] + "TARGET_XTHEADCONDMOV" +{ + if (which_alternative == 0) + return "th.mv%C4z\t%0,%z2,%1"; + + /* Invert the condition and take else-block. */ + rtx_code code = GET_CODE (operands[4]); + code = (code == EQ) ? NE : EQ; + operands[4] = gen_rtx_fmt_ee (code, VOIDmode, const0_rtx, const0_rtx); + return "th.mv%C4z\t%0,%z3,%1"; +} + [(set_attr "type" "condmove") + (set_attr "mode" "")]) + +(define_insn "*th_cond_gpr_mov" + [(set (match_operand:GPR 0 "register_operand" "=r,r") + (if_then_else:GPR + (match_operand:GPR2 1 "register_operand" "r,r") + (match_operand:GPR 2 "reg_or_0_operand" "rJ,0") + (match_operand:GPR 3 "reg_or_0_operand" "0,rJ")))] + "TARGET_XTHEADCONDMOV" + "@ + th.mvnez\t%0,%z2,%1 + th.mveqz\t%0,%z3,%1" + [(set_attr "type" "condmove") + (set_attr "mode" "")]) diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-eqz.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-eqz.c new file mode 100644 index 00000000000..c66ec7fadbb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-eqz.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */ + +int +not_int_int (int x, int cond) +{ + if (cond == 0) + return 1025; + return x; +} + +long +not_long_int (long x, int cond) +{ + if (cond == 0) + return 1025l; + return x; +} + +int +not_int_long (int x, long cond) +{ + if (cond == 0) + return 1025; + return x; +} + +long +not_long_long (long x, int cond) +{ + if (cond == 0) + return 1025l; + return x; +} + +/* { dg-final { scan-assembler-times "th.mveqz" 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-not.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-not.c new file mode 100644 index 00000000000..c076dbca4ef --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-imm-not.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mabi=lp64 -O2" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */ + +int +not_int_int (int x, int cond) +{ + if (!cond) + return 1025; + return x; +} + +long +not_long_int (long x, int cond) +{ + if (!cond) + return 1025l; + return x; +} + +int +not_int_long (int x, long cond) +{ + if (!cond) + return 1025; + return x; +} + +long +not_long_long (long x, int cond) +{ + if (!cond) + return 1025l; + return x; +} + +/* { dg-final { scan-assembler-times "th.mveqz" 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-eqz.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-eqz.c new file mode 100644 index 00000000000..3e2e369bdb2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-eqz.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */ + +int +not_int_int (int x, int cond, int v) +{ + if (cond == 0) + return v; + return x; +} + +long +not_long_int (long x, int cond, long v) +{ + if (cond == 0) + return v; + return x; +} + +int +not_int_long (int x, long cond, int v) +{ + if (cond == 0) + return v; + return x; +} + +long +not_long_long (long x, int cond, long v) +{ + if (cond == 0) + return v; + return x; +} + +/* { dg-final { scan-assembler-times "th.mveqz" 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-not.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-not.c new file mode 100644 index 00000000000..c387d1c5f98 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mveqz-reg-not.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mabi=lp64 -O2" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */ + +int +not_int_int (int x, int cond, int v) +{ + if (!cond) + return v; + return x; +} + +long +not_long_int (long x, int cond, long v) +{ + if (!cond) + return v; + return x; +} + +int +not_int_long (int x, long cond, int v) +{ + if (!cond) + return v; + return x; +} + +long +not_long_long (long x, int cond, long v) +{ + if (!cond) + return v; + return x; +} + +/* { dg-final { scan-assembler-times "th.mveqz" 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-cond.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-cond.c new file mode 100644 index 00000000000..95b396057da --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-cond.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mabi=lp64 -O2" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */ + +int +not_int_int (int x, int cond) +{ + if (cond) + return 1025; + return x; +} + +long +not_long_int (long x, int cond) +{ + if (cond) + return 1025l; + return x; +} + +int +not_int_long (int x, long cond) +{ + if (cond) + return 1025; + return x; +} + +long +not_long_long (long x, int cond) +{ + if (cond) + return 1025l; + return x; +} + +/* { dg-final { scan-assembler-times "th.mvnez" 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-nez.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-nez.c new file mode 100644 index 00000000000..cc17f1bd82d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-imm-nez.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */ + +int +not_int_int (int x, int cond) +{ + if (cond != 0) + return 1025; + return x; +} + +long +not_long_int (long x, int cond) +{ + if (cond != 0) + return 1025l; + return x; +} + +int +not_int_long (int x, long cond) +{ + if (cond != 0) + return 1025; + return x; +} + +long +not_long_long (long x, int cond) +{ + if (cond != 0) + return 1025l; + return x; +} + +/* { dg-final { scan-assembler-times "th.mvnez" 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-cond.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-cond.c new file mode 100644 index 00000000000..732e892875b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-cond.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mabi=lp64 -O2" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */ + +int +not_int_int (int x, int cond, int v) +{ + if (cond) + return v; + return x; +} + +long +not_long_int (long x, int cond, long v) +{ + if (cond) + return v; + return x; +} + +int +not_int_long (int x, long cond, int v) +{ + if (cond) + return v; + return x; +} + +long +not_long_long (long x, int cond, long v) +{ + if (cond) + return v; + return x; +} + +/* { dg-final { scan-assembler-times "th.mvnez" 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-nez.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-nez.c new file mode 100644 index 00000000000..e369a972a16 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-mvnez-reg-nez.c @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xtheadcondmov -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */ + +int +not_int_int (int x, int cond, int v) +{ + if (cond != 0) + return v; + return x; +} + +long +not_long_int (long x, int cond, long v) +{ + if (cond != 0) + return v; + return x; +} + +int +not_int_long (int x, long cond, int v) +{ + if (cond != 0) + return v; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id lb17-20020a170907785100b00734bfab4d59sm3432282ejc.170.2022.11.13.13.46.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 13:46:47 -0800 (PST) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH 5/7] riscv: thead: Add support for XTheadBb ISA extension Date: Sun, 13 Nov 2022 22:46:34 +0100 Message-Id: <20221113214636.2747737-6-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221113214636.2747737-1-christoph.muellner@vrull.eu> References: <20221113214636.2747737-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_MANYTO, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Christoph Müllner The XTheadBb ISA extension provides instructions similar to Zbb: * th.srri/th.srriw * th.ext/th.extu * th.ff1 (count-leading-zeros) * th.rev/th.revw Instructions that are not covered, because they don't fit into a pattern: * th.ff0 (count-leading-ones) * th.tstnbz For the cases where the RISC-V backend already provides instruction patterns with GCC standard pattern names (e.g. rotatert), this patch simply uses expanders so we can match the pattern using unnamed instruction patterns for zb* and xtheadb*. gcc/ChangeLog: * config/riscv/bitmanip.md (clz2): Add expand. (ctz2): Add expand. (popcount2): Add expand. (*si2): Hide pattern name. (*di2): Hide pattern name. (rotr3): Add expand. (*rotrsi3): Hide pattern name. (*rotrdi3): Hide pattern name. (*rotrsi3_sext): Hide pattern name. (bswapdi2): Add expand. (bswapsi2): Add expand. (*bswap2): Hide pattern name. * config/riscv/riscv.cc (riscv_rtx_costs): Add support for sign-extract. * config/riscv/riscv.md (extv): New expand. (extzv): New expand. * config/riscv/thead.md (*th_srrisi3): New pattern. (*th_srridi3): New pattern. (*th_ext): New pattern. (*th_extu): New pattern. (*th_clz): New pattern. (*th_revsi2): New pattern. (*th_revdi2): New pattern. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadbb-ext.c: New test. * gcc.target/riscv/xtheadbb-extu.c: New test. * gcc.target/riscv/xtheadbb-rev.c: New test. * gcc.target/riscv/xtheadbb-srri.c: New test. Signed-off-by: Christoph Müllner --- gcc/config/riscv/bitmanip.md | 47 ++++++++++++-- gcc/config/riscv/riscv.cc | 10 +++ gcc/config/riscv/riscv.md | 26 ++++++++ gcc/config/riscv/thead.md | 62 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c | 19 ++++++ .../gcc.target/riscv/xtheadbb-extu.c | 12 ++++ gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c | 40 ++++++++++++ .../gcc.target/riscv/xtheadbb-srri.c | 18 ++++++ 8 files changed, 228 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-extu.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-srri.c diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index b44fb9517e7..3dbb92b6115 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -119,6 +119,21 @@ (define_insn "*slliuw" ;; ZBB extension. +(define_expand "clz2" + [(set (match_operand:GPR 0 "register_operand") + (clz:GPR (match_operand:GPR 1 "register_operand")))] + "TARGET_ZBB || TARGET_XTHEADBB") + +(define_expand "ctz2" + [(set (match_operand:GPR 0 "register_operand") + (ctz:GPR (match_operand:GPR 1 "register_operand")))] + "TARGET_ZBB") + +(define_expand "popcount2" + [(set (match_operand:GPR 0 "register_operand") + (popcount:GPR (match_operand:GPR 1 "register_operand")))] + "TARGET_ZBB") + (define_insn "*_not" [(set (match_operand:X 0 "register_operand" "=r") (bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r")) @@ -137,7 +152,7 @@ (define_insn "*xor_not" [(set_attr "type" "bitmanip") (set_attr "mode" "")]) -(define_insn "si2" +(define_insn "*si2" [(set (match_operand:SI 0 "register_operand" "=r") (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r")))] "TARGET_ZBB" @@ -154,7 +169,7 @@ (define_insn "*disi2" [(set_attr "type" "bitmanip") (set_attr "mode" "SI")]) -(define_insn "di2" +(define_insn "*di2" [(set (match_operand:DI 0 "register_operand" "=r") (clz_ctz_pcnt:DI (match_operand:DI 1 "register_operand" "r")))] "TARGET_64BIT && TARGET_ZBB" @@ -194,7 +209,17 @@ (define_insn "*zero_extendhi2_zbb" [(set_attr "type" "bitmanip,load") (set_attr "mode" "HI")]) -(define_insn "rotrsi3" +(define_expand "rotr3" + [(set (match_operand:GPR 0 "register_operand") + (rotatert:GPR (match_operand:GPR 1 "register_operand") + (match_operand:QI 2 "arith_operand")))] + "TARGET_ZBB || TARGET_XTHEADBB" +{ + if (TARGET_XTHEADBB && !immediate_operand (operands[2], VOIDmode)) + FAIL; +}) + +(define_insn "*rotrsi3" [(set (match_operand:SI 0 "register_operand" "=r") (rotatert:SI (match_operand:SI 1 "register_operand" "r") (match_operand:QI 2 "arith_operand" "rI")))] @@ -202,7 +227,7 @@ (define_insn "rotrsi3" "ror%i2%~\t%0,%1,%2" [(set_attr "type" "bitmanip")]) -(define_insn "rotrdi3" +(define_insn "*rotrdi3" [(set (match_operand:DI 0 "register_operand" "=r") (rotatert:DI (match_operand:DI 1 "register_operand" "r") (match_operand:QI 2 "arith_operand" "rI")))] @@ -210,7 +235,7 @@ (define_insn "rotrdi3" "ror%i2\t%0,%1,%2" [(set_attr "type" "bitmanip")]) -(define_insn "rotrsi3_sext" +(define_insn "*rotrsi3_sext" [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI (rotatert:SI (match_operand:SI 1 "register_operand" "r") (match_operand:QI 2 "register_operand" "r"))))] @@ -242,7 +267,17 @@ (define_insn "rotlsi3_sext" "rolw\t%0,%1,%2" [(set_attr "type" "bitmanip")]) -(define_insn "bswap2" +(define_expand "bswapdi2" + [(set (match_operand:DI 0 "register_operand") + (bswap:DI (match_operand:DI 1 "register_operand")))] + "TARGET_64BIT && (TARGET_ZBB || TARGET_XTHEADBB)") + +(define_expand "bswapsi2" + [(set (match_operand:SI 0 "register_operand") + (bswap:SI (match_operand:SI 1 "register_operand")))] + "(!TARGET_64BIT && TARGET_ZBB) || TARGET_XTHEADBB") + +(define_insn "*bswap2" [(set (match_operand:X 0 "register_operand" "=r") (bswap:X (match_operand:X 1 "register_operand" "r")))] "TARGET_ZBB" diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 9a795264e00..c0de99d1ca6 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2377,6 +2377,16 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN *total = COSTS_N_INSNS (SINGLE_SHIFT_COST); return true; } + /* Fall through. */ + case SIGN_EXTRACT: + if (TARGET_XTHEADBB + && REG_P (XEXP (x, 0)) + && CONST_INT_P (XEXP (x, 1)) + && CONST_INT_P (XEXP (x, 2))) + { + *total = COSTS_N_INSNS (SINGLE_SHIFT_COST); + return true; + } return false; case ASHIFT: diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 850a2d958e4..cfe1fd6baea 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -3003,6 +3003,32 @@ (define_insn "riscv_prefetchi_" "prefetch.i\t%a0" ) +(define_expand "extv" + [(set (match_operand:GPR 0 "register_operand" "=r") + (sign_extract:GPR (match_operand:GPR 1 "register_operand" "r") + (match_operand 2 "const_int_operand") + (match_operand 3 "const_int_operand")))] + "TARGET_XTHEADBB" +{ + if (TARGET_XTHEADBB + && ((INTVAL (operands[2]) + INTVAL (operands[3])) + >= GET_MODE_BITSIZE (GET_MODE (operands[1])).to_constant ())) + FAIL; +}) + +(define_expand "extzv" + [(set (match_operand:GPR 0 "register_operand" "=r") + (zero_extract:GPR (match_operand:GPR 1 "register_operand" "r") + (match_operand 2 "const_int_operand") + (match_operand 3 "const_int_operand")))] + "TARGET_XTHEADBB" +{ + if (TARGET_XTHEADBB + && ((INTVAL (operands[2]) + INTVAL (operands[3])) + >= GET_MODE_BITSIZE (GET_MODE (operands[1])).to_constant ())) + FAIL; +}) + (include "bitmanip.md") (include "sync.md") (include "peephole.md") diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md index e9a6c1eeb71..ad42c03c0ce 100644 --- a/gcc/config/riscv/thead.md +++ b/gcc/config/riscv/thead.md @@ -28,6 +28,68 @@ (define_insn "*th_addsl" [(set_attr "type" "bitmanip") (set_attr "mode" "")]) +(define_insn "*th_srrisi3" + [(set (match_operand:SI 0 "register_operand" "=r") + (rotatert:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "I")))] + "TARGET_XTHEADBB" + { return TARGET_64BIT ? "th.srriw\t%0,%1,%2" : "th.srri\t%0,%1,%2"; } + [(set_attr "type" "bitmanip")]) + +(define_insn "*th_srridi3" + [(set (match_operand:DI 0 "register_operand" "=r") + (rotatert:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "I")))] + "TARGET_XTHEADBB && TARGET_64BIT" + "th.srri\t%0,%1,%2" + [(set_attr "type" "bitmanip")]) + +(define_insn "*th_ext" + [(set (match_operand:X 0 "register_operand" "=r") + (sign_extract:X (match_operand:X 1 "register_operand" "r") + (match_operand 2 "const_int_operand") + (match_operand 3 "const_int_operand")))] + "TARGET_XTHEADBB" +{ + operands[3] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3])); + return "th.ext\t%0,%1,%2,%3"; +} + [(set_attr "type" "bitmanip")]) + +(define_insn "*th_extu" + [(set (match_operand:X 0 "register_operand" "=r") + (zero_extract:X (match_operand:X 1 "register_operand" "r") + (match_operand 2 "const_int_operand") + (match_operand 3 "const_int_operand")))] + "TARGET_XTHEADBB" +{ + operands[3] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3])); + return "th.extu\t%0,%1,%2,%3"; +} + [(set_attr "type" "bitmanip")]) + +(define_insn "*th_clz" + [(set (match_operand:X 0 "register_operand" "=r") + (clz:X (match_operand:X 1 "register_operand" "r")))] + "TARGET_XTHEADBB" + "th.ff1\t%0,%1" + [(set_attr "type" "bitmanip") + (set_attr "mode" "")]) + +(define_insn "*th_revsi2" + [(set (match_operand:SI 0 "register_operand" "=r") + (bswap:SI (match_operand:SI 1 "register_operand" "r")))] + "TARGET_XTHEADBB" + { return TARGET_64BIT ? "th.revw\t%0,%1" : "th.rev\t%0,%1"; } + [(set_attr "type" "bitmanip")]) + +(define_insn "*th_revdi2" + [(set (match_operand:DI 0 "register_operand" "=r") + (bswap:DI (match_operand:DI 1 "register_operand" "r")))] + "TARGET_XTHEADBB && TARGET_64BIT" + "th.rev\t%0,%1" + [(set_attr "type" "bitmanip")]) + (define_insn "*th_tst" [(set (match_operand:X 0 "register_operand" "=r") (zero_extract:X (match_operand:X 1 "register_operand" "r") diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c b/gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c new file mode 100644 index 00000000000..35c3afa5aad --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xtheadbb -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */ + +struct bar +{ + long a:18; + long b:24; + long c:22; +}; + +long +foo (struct bar *s) +{ + return s->b; +} + +/* { dg-final { scan-assembler "ext\t" } } */ +/* { dg-final { scan-assembler-not "andi" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-extu.c b/gcc/testsuite/gcc.target/riscv/xtheadbb-extu.c new file mode 100644 index 00000000000..d52af1dec61 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-extu.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xtheadbb -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */ + +int +foo (int a, int b) +{ + return ((a & (1 << 25)) ? 5 : 4); +} + +/* { dg-final { scan-assembler "extu\t" } } */ +/* { dg-final { scan-assembler-not "andi" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c b/gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c new file mode 100644 index 00000000000..fb35317ae9f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xtheadbb -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ + +unsigned int +foo32 (unsigned int x) +{ + return (((x << 24) & 0xff000000) + | ((x << 8) & 0xff0000) + | ((x >> 8) & 0xff00) + | ((x >> 24) & 0xff)); +} + +unsigned int +foo32_1 (unsigned int x) +{ + return __builtin_bswap32 (x); +} + +unsigned long +foo64 (unsigned long x) +{ + return (((x << 56) & 0xff00000000000000ull) + | ((x << 40) & 0xff000000000000ull) + | ((x << 24) & 0xff0000000000ull) + | ((x << 8) & 0xff00000000ull) + | ((x >> 8) & 0xff000000) + | ((x >> 24) & 0xff0000) + | ((x >> 40) & 0xff00) + | ((x >> 56) & 0xff)); +} + +unsigned long +foo64_1 (unsigned long x) +{ + return __builtin_bswap64 (x); +} + +/* { dg-final { scan-assembler-times "th.revw\t" 2 } } */ +/* { dg-final { scan-assembler-times "th.rev\t" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-srri.c b/gcc/testsuite/gcc.target/riscv/xtheadbb-srri.c new file mode 100644 index 00000000000..cd992ae3f0a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-srri.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xtheadbb -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-g" } } */ + +unsigned long foo1(unsigned long rs1) +{ + long shamt = __riscv_xlen - 11; + return (rs1 << shamt) | + (rs1 >> ((__riscv_xlen - shamt) & (__riscv_xlen - 1))); +} +unsigned long foo2(unsigned long rs1) +{ + unsigned long shamt = __riscv_xlen - 11; + return (rs1 >> shamt) | + (rs1 << ((__riscv_xlen - shamt) & (__riscv_xlen - 1))); +} + +/* { dg-final { scan-assembler-times "th.srri" 2 } } */ From patchwork Sun Nov 13 21:46:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 60558 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0F5D438515D7 for ; Sun, 13 Nov 2022 21:48:09 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ej1-x62e.google.com (mail-ej1-x62e.google.com [IPv6:2a00:1450:4864:20::62e]) by sourceware.org (Postfix) with ESMTPS id 0400F385703A for ; Sun, 13 Nov 2022 21:46:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0400F385703A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-ej1-x62e.google.com with SMTP id k2so24198331ejr.2 for ; Sun, 13 Nov 2022 13:46:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=phrtoKhMQ5NychQdHkBmRkfJcfboFJ0kZ4SXj3DFiG0=; b=CpdBekNxh2BD0lvqNfrwA9x5ZSKMnvK/xmMxj2N5ZIsIZyTc/4do37Pb004X3JB0sV NJ6np5nPFC+K0/LphSORG7Yv7LPvGUZ65DwrNq4Us/MnpO1gJKg6pV+LHKOJFVd1R4Vq nMFDNHKisi5zyDAWremUEzqz00wnNK+3l9Zzp+/DFx2t3QZr4fmRqFrBg+4FJ40zo5xs jBLkk0R6Iy3ihxLyLt4I1xpoFQ4dt6OnrhM3jy6VwcPmQkm9S/Cj2AGrji82LXPKCE7Q j22plqw/TjUD9SA3E/haYPjols0zkpdDCkV2WxNYeAxuoEirgWEKDk+X3/61MmyDacqK vZHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=phrtoKhMQ5NychQdHkBmRkfJcfboFJ0kZ4SXj3DFiG0=; b=ZATWJdjUqpMUkysplad7dlla9Dz8JIIe6Ruy5hvTjF1Tr05VSn/l9Zmz2Ae0iwB3fk dhSYY89gJ6TgSC5JNvnuBpUW/j1tYPsnesxLtEjITtxDnek+33MixBBO8Bm/2GT8YtV9 WVUyN+oGiq/jGO7F+fyPLhCwkF1IR6jV3TyOmW/3o0rhFNPLReEzBLZE5AUFhA7gC1FX +zA7fCVxrWRmT54UggZTUKo/deRG9+mi32Sse/mf1+6DBrmNXFRexja+lRu8vFMwRxTR j3eK5q/7CVbJ78y7H6SrkLxmL30iA3lqxX0vkVmO6zbtQtWFq6ObR59zJA8gPDiW28lS t0Iw== X-Gm-Message-State: ANoB5pl41j1SKX/RpPvH+KhhIa6OCfKZS4GsDj0ZUWfZPLVy7ME3X6sh tmqQVndcjxzq3IungNXiGSvLgz83RvQRH/GM X-Google-Smtp-Source: AA0mqf5NiQ75rmnhT3WsXao9iGR9yypRKiYaR8SflEwCzUTFM/uwTJhp6TU6FaVwuYJ/2TqUhCRxNQ== X-Received: by 2002:a17:907:2b08:b0:78d:424c:fa2b with SMTP id gc8-20020a1709072b0800b0078d424cfa2bmr8571112ejc.546.1668376009192; Sun, 13 Nov 2022 13:46:49 -0800 (PST) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id lb17-20020a170907785100b00734bfab4d59sm3432282ejc.170.2022.11.13.13.46.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 13:46:48 -0800 (PST) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?utf-8?q?Christoph_M=C3=BCllner?= , quxm Subject: [PATCH 6/7] riscv: thead: Add support for XTheadMac ISA extension Date: Sun, 13 Nov 2022 22:46:35 +0100 Message-Id: <20221113214636.2747737-7-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221113214636.2747737-1-christoph.muellner@vrull.eu> References: <20221113214636.2747737-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_MANYTO, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Christoph Müllner The XTheadMac ISA extension provides multiply-accumulate/subtract instructions: * mula/mulaw/mulah * muls/mulsw/mulsh To benefit from middle-end passes, we expand the following named patterns in riscv.md (as they are not T-Head-specific): * maddhisi4 * msubhisi4 gcc/ChangeLog: * config/riscv/riscv.md (maddhisi4): New expand. (msubhisi4): New expand. * config/riscv/thead.md (*th_mula): New pattern. (*th_mulawsi): New pattern. (*th_mulawsi2): New pattern. (*th_maddhisi4): New pattern. (*th_sextw_maddhisi4): New pattern. (*th_muls): New pattern. (*th_mulswsi): New pattern. (*th_mulswsi2): New pattern. (*th_msubhisi4): New pattern. (*th_sextw_msubhisi4): New pattern. gcc/testsuite/ChangeLog: * gcc.target/riscv/thead-mula-1.c: New test. * gcc.target/riscv/thead-mula-2.c: New test. Co-Developed-by: quxm Signed-off-by: quxm Signed-off-by: Christoph Müllner --- gcc/config/riscv/riscv.md | 18 +++ gcc/config/riscv/thead.md | 117 ++++++++++++++++++ gcc/testsuite/gcc.target/riscv/thead-mula-1.c | 40 ++++++ gcc/testsuite/gcc.target/riscv/thead-mula-2.c | 28 +++++ 4 files changed, 203 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/thead-mula-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/thead-mula-2.c diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index cfe1fd6baea..998169115f2 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -3029,6 +3029,24 @@ (define_expand "extzv" FAIL; }) +(define_expand "maddhisi4" + [(set (match_operand:SI 0 "register_operand") + (plus:SI + (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand")) + (sign_extend:SI (match_operand:HI 2 "register_operand"))) + (match_operand:SI 3 "register_operand")))] + "TARGET_XTHEADMAC" +) + +(define_expand "msubhisi4" + [(set (match_operand:SI 0 "register_operand") + (minus:SI + (match_operand:SI 3 "register_operand") + (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand")) + (sign_extend:SI (match_operand:HI 2 "register_operand")))))] + "TARGET_XTHEADMAC" +) + (include "bitmanip.md") (include "sync.md") (include "peephole.md") diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md index ad42c03c0ce..f31ba18aa84 100644 --- a/gcc/config/riscv/thead.md +++ b/gcc/config/riscv/thead.md @@ -133,3 +133,120 @@ (define_insn "*th_cond_gpr_mov" th.mveqz\t%0,%z3,%1" [(set_attr "type" "condmove") (set_attr "mode" "")]) + +;; XTheadMac + +(define_insn "*th_mula" + [(set (match_operand:X 0 "register_operand" "=r") + (plus:X (mult:X (match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r")) + (match_operand:X 3 "register_operand" "0")))] + "TARGET_XTHEADMAC" + "th.mula\\t%0,%1,%2" + [(set_attr "type" "imul") + (set_attr "mode" "")] +) + +(define_insn "*th_mulawsi" + [(set (match_operand:DI 0 "register_operand" "=r") + (sign_extend:DI + (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")) + (match_operand:SI 3 "register_operand" "0"))))] + "TARGET_XTHEADMAC && TARGET_64BIT" + "th.mulaw\\t%0,%1,%2" + [(set_attr "type" "imul") + (set_attr "mode" "SI")] +) + +(define_insn "*th_mulawsi2" + [(set (match_operand:SI 0 "register_operand" "=r") + (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")) + (match_operand:SI 3 "register_operand" "0")))] + "TARGET_XTHEADMAC && TARGET_64BIT" + "mulaw\\t%0,%1,%2" + [(set_attr "type" "imul") + (set_attr "mode" "SI")] +) + +(define_insn "*th_maddhisi4" + [(set (match_operand:SI 0 "register_operand" "=r") + (plus:SI (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" " r")) + (sign_extend:SI (match_operand:HI 2 "register_operand" " r"))) + (match_operand:SI 3 "register_operand" " 0")))] + "TARGET_XTHEADMAC" + "th.mulah\\t%0,%1,%2" + [(set_attr "type" "imul") + (set_attr "mode" "SI")] +) + +(define_insn "*th_sextw_maddhisi4" + [(set (match_operand:DI 0 "register_operand" "=r") + (sign_extend:DI + (plus:SI (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" " r")) + (sign_extend:SI (match_operand:HI 2 "register_operand" " r"))) + (match_operand:SI 3 "register_operand" " 0"))))] + "TARGET_XTHEADMAC && TARGET_64BIT" + "th.mulah\\t%0,%1,%2" + [(set_attr "type" "imul") + (set_attr "mode" "SI")] +) + +(define_insn "*th_muls" + [(set (match_operand:X 0 "register_operand" "=r") + (minus:X (match_operand:X 3 "register_operand" "0") + (mult:X (match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r"))))] + "TARGET_XTHEADMAC" + "th.muls\\t%0,%1,%2" + [(set_attr "type" "imul") + (set_attr "mode" "")] +) + +(define_insn "*th_mulswsi" + [(set (match_operand:DI 0 "register_operand" "=r") + (sign_extend:DI + (minus:SI (match_operand:SI 3 "register_operand" "0") + (mult:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")))))] + "TARGET_XTHEADMAC && TARGET_64BIT" + "th.mulsw\\t%0,%1,%2" + [(set_attr "type" "imul") + (set_attr "mode" "SI")] +) + +(define_insn "*th_mulswsi2" + [(set (match_operand:SI 0 "register_operand" "=r") + (minus:SI (match_operand:SI 3 "register_operand" "0") + (mult:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r"))))] + "TARGET_XTHEADMAC && TARGET_64BIT" + "th.mulsw\\t%0,%1,%2" + [(set_attr "type" "imul") + (set_attr "mode" "SI")] +) + +(define_insn "*th_msubhisi4" + [(set (match_operand:SI 0 "register_operand" "=r") + (minus:SI (match_operand:SI 3 "register_operand" " 0") + (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" " r")) + (sign_extend:SI (match_operand:HI 2 "register_operand" " r")))))] + "TARGET_XTHEADMAC" + "th.mulsh\\t%0,%1,%2" + [(set_attr "type" "imul") + (set_attr "mode" "SI")] +) + +(define_insn "*th_sextw_msubhisi4" + [(set (match_operand:DI 0 "register_operand" "=r") + (sign_extend:DI + (minus:SI (match_operand:SI 3 "register_operand" " 0") + (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" " r")) + (sign_extend:SI (match_operand:HI 2 "register_operand" " r"))))))] + "TARGET_XTHEADMAC && TARGET_64BIT" + "th.mulsh\\t%0,%1,%2" + [(set_attr "type" "imul") + (set_attr "mode" "SI")] +) + diff --git a/gcc/testsuite/gcc.target/riscv/thead-mula-1.c b/gcc/testsuite/gcc.target/riscv/thead-mula-1.c new file mode 100644 index 00000000000..446bbdd98a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/thead-mula-1.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv64gc_xtheadmac -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ + +long f_mula(long a, long b, long c) +{ + return a + b * c; +} + +long f_muls(long a, long b, long c) +{ + return a - b * c; +} + +int f_mulaw(int a, int b, int c) +{ + return a + b * c; +} + +int f_mulsw(int a, int b, int c) +{ + return a - b * c; +} + +long f_mulah(int a, unsigned short b, unsigned short c) +{ + return a + (int)(short)b * (int)(short)c; +} + +long f_mulsh(int a, unsigned short b, unsigned short c) +{ + return a - (int)(short)b * (int)(short)c; +} + +/* { dg-final { scan-assembler-times "th.mula\t" 1 } } */ +/* { dg-final { scan-assembler-times "th.muls\t" 1 } } */ +/* { dg-final { scan-assembler-times "th.mulaw\t" 1 } } */ +/* { dg-final { scan-assembler-times "th.mulsw\t" 1 } } */ +/* { dg-final { scan-assembler-times "th.mulah\t" 1 } } */ +/* { dg-final { scan-assembler-times "th.mulsh\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/thead-mula-2.c b/gcc/testsuite/gcc.target/riscv/thead-mula-2.c new file mode 100644 index 00000000000..87145669573 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/thead-mula-2.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=rv32gc_xtheadmac -mabi=ilp32" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ + +long f_mula(long a, long b, long c) +{ + return a + b * c; +} + +long f_muls(long a, long b, long c) +{ + return a - b * c; +} + +long f_mulah(int a, unsigned short b, unsigned short c) +{ + return a + (int)(short)b * (int)(short)c; +} + +long f_mulsh(int a, unsigned short b, unsigned short c) +{ + return a - (int)(short)b * (int)(short)c; +} + +/* { dg-final { scan-assembler-times "th.mula\t" 1 } } */ +/* { dg-final { scan-assembler-times "th.muls\t" 1 } } */ +/* { dg-final { scan-assembler-times "th.mulah\t" 1 } } */ +/* { dg-final { scan-assembler-times "th.mulsh\t" 1 } } */ From patchwork Sun Nov 13 21:46:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 60557 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C91C7395443C for ; Sun, 13 Nov 2022 21:47:48 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by sourceware.org (Postfix) with ESMTPS id E00DF3887F47 for ; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id lb17-20020a170907785100b00734bfab4d59sm3432282ejc.170.2022.11.13.13.46.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 13:46:49 -0800 (PST) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH 7/7] riscv: Add basic extension support for XTheadFmv and XTheadInt Date: Sun, 13 Nov 2022 22:46:36 +0100 Message-Id: <20221113214636.2747737-8-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221113214636.2747737-1-christoph.muellner@vrull.eu> References: <20221113214636.2747737-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_MANYTO, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Christoph Müllner This patch add basic support for the XTheadFmv and XTheadInt ISA extension. As both extensions only contain instruction, which are not supposed to be emitted by the compiler, the support only covers awareness of the extension name in the march string and the definition of a feature test macro. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add xtheadfmv and xtheadint. * config/riscv/riscv-opts.h (MASK_XTHEADMAC): New. (MASK_XTHEADFMV): New. (TARGET_XTHEADFMV): New. (MASK_XTHEADINT): New. (TARGET_XTHEADINT): New. (MASK_XTHEADMEMIDX): New. (MASK_XTHEADSYNC): New. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadfmv.c: New test. * gcc.target/riscv/xtheadint.c: New test. Signed-off-by: Christoph Müllner --- gcc/common/config/riscv/riscv-common.cc | 4 ++++ gcc/config/riscv/riscv-opts.h | 10 +++++++--- gcc/testsuite/gcc.target/riscv/xtheadfmv.c | 14 ++++++++++++++ gcc/testsuite/gcc.target/riscv/xtheadint.c | 14 ++++++++++++++ 4 files changed, 39 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadfmv.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadint.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 8e1449d3543..b3e6732dddd 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -228,6 +228,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"xtheadcmo", ISA_SPEC_CLASS_NONE, 1, 0}, {"xtheadcondmov", ISA_SPEC_CLASS_NONE, 1, 0}, {"xtheadfmemidx", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xtheadfmv", ISA_SPEC_CLASS_NONE, 1, 0}, + {"xtheadint", ISA_SPEC_CLASS_NONE, 1, 0}, {"xtheadmac", ISA_SPEC_CLASS_NONE, 1, 0}, {"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0}, {"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1263,6 +1265,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"xtheadcmo", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADCMO}, {"xtheadcondmov", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADCONDMOV}, {"xtheadfmemidx", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADFMEMIDX}, + {"xtheadfmv", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADFMV}, + {"xtheadint", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADINT}, {"xtheadmac", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMAC}, {"xtheadmemidx", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMIDX}, {"xtheadsync", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADSYNC}, diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 18daac40dbd..c1868dcf284 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -201,11 +201,15 @@ enum stack_protector_guard { #define TARGET_XTHEADCONDMOV ((riscv_xthead_subext & MASK_XTHEADCONDMOV) != 0) #define MASK_XTHEADFMEMIDX (1 << 5) #define TARGET_XTHEADFMEMIDX ((riscv_xthead_subext & MASK_XTHEADFMEMIDX) != 0) -#define MASK_XTHEADMAC (1 << 6) +#define MASK_XTHEADFMV (1 << 6) +#define TARGET_XTHEADFMV ((riscv_xthead_subext & MASK_XTHEADFMV) != 0) +#define MASK_XTHEADINT (1 << 7) +#define TARGET_XTHEADINT ((riscv_xthead_subext & MASK_XTHEADINT) != 0) +#define MASK_XTHEADMAC (1 << 8) #define TARGET_XTHEADMAC ((riscv_xthead_subext & MASK_XTHEADMAC) != 0) -#define MASK_XTHEADMEMIDX (1 << 7) +#define MASK_XTHEADMEMIDX (1 << 9) #define TARGET_XTHEADMEMIDX ((riscv_xthead_subext & MASK_XTHEADMEMIDX) != 0) -#define MASK_XTHEADSYNC (1 << 8) +#define MASK_XTHEADSYNC (1 << 10) #define TARGET_XTHEADSYNC ((riscv_xthead_subext & MASK_XTHEADSYNC) != 0) #endif /* ! GCC_RISCV_OPTS_H */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadfmv.c b/gcc/testsuite/gcc.target/riscv/xtheadfmv.c new file mode 100644 index 00000000000..e97e8f461f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadfmv.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_xtheadfmv" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc_xtheadfmv" { target { rv64 } } } */ + +#ifndef __riscv_xtheadfmv +#error Feature macro not defined +#endif + +int +foo (int a) +{ + return a; +} + diff --git a/gcc/testsuite/gcc.target/riscv/xtheadint.c b/gcc/testsuite/gcc.target/riscv/xtheadint.c new file mode 100644 index 00000000000..ee6989a380e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadint.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_xtheadint" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc_xtheadint" { target { rv64 } } } */ + +#ifndef __riscv_xtheadint +#error Feature macro not defined +#endif + +int +foo (int a) +{ + return a; +} +