From patchwork Sun Nov 13 20:48:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 60537 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 43DE2388B681 for ; Sun, 13 Nov 2022 20:48:48 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by sourceware.org (Postfix) with ESMTPS id A6F2E3858436 for ; Sun, 13 Nov 2022 20:48:29 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org A6F2E3858436 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-lj1-x22f.google.com with SMTP id z24so10688251ljn.4 for ; Sun, 13 Nov 2022 12:48:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fh9PEErohlGIgQlw9f9f9yHEIKzfCH+F6Kyj3H7BRGw=; b=cQsAPTZFRx+GzbbRmJjxz2pifr4d+IsuGYcHQ+2zlA1ELBK5j5xm28krmih5QPCt4+ Q6OMh5NbuLVpyaHWmbncLUzkOSU9/v1pAY7z2nEuUQYsa5DYl0QoBTYkwN47uee6kZ3i wIiJ0oBY/4AveIbEBkJ7zZfJDIUDQxQI0MWhZS7kGiyWDkvvn7rUCpBgJB/3cuzdSRX4 aVKK6ofhg4q88qa0p8qykNq0eLX7keOY6UrCx3ci0A6X2QwZ7dovwZ1n+S6b9kbZv1Lz VXVPDwLCy6u/82eqZ3k4AnFZtYn8xrjogD3TFCHsiC7Kjk3PONAyspDHf+ZdPZXFO43p +ppw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fh9PEErohlGIgQlw9f9f9yHEIKzfCH+F6Kyj3H7BRGw=; b=C9DMfFDvuWxkd2xGIkhQXPO2Kaa1t5KA5gStHmNi2uFzkISyK0nOM38TQIHyhhje/1 mjYnEBXxQOwxiyt7SZDOpyyHnPzm7h65awhP+FdMcyXrsTgle930nhSpfH8y9ayvhEbh A6nYjwkKF+bDEOZjbNVwweljFyXbupb+Wg9KGlQVAuGG5bELJtFD65u6QnBRfLDyv6FK 1bjejaKeXw/JhQnM2A9YxgRxYgZOl9h+YUtzya0SpQobsQuHau3R0mGexmKdSJI2VYu0 Kyl5HLWloLEtLHEGS1V4HBJ16lYWMslByT/6jTms/Z+jEcWDOOVqW413l59LKeAM7uq2 SnSA== X-Gm-Message-State: ANoB5pnMDmYQ8sjNyWNrxfyhv7EQ0KbLTARkcUfsNbwUHidl4WV43Qxx CRxBTQAWd9E6HIOqTieOcN4zAcxh/zaBPT+m X-Google-Smtp-Source: AA0mqf6DbEfzubwgxRJ18viwids0BqFZwJfhSDAh62KnvvaJVf82pd8HzjMxt1PIdE7UejYU1CNJtw== X-Received: by 2002:a2e:8081:0:b0:277:1273:f3b8 with SMTP id i1-20020a2e8081000000b002771273f3b8mr3072653ljg.178.1668372507877; Sun, 13 Nov 2022 12:48:27 -0800 (PST) Received: from ubuntu-focal.. ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id m5-20020a056512114500b004979db5aa5bsm1520567lfg.223.2022.11.13.12.48.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 12:48:27 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Palmer Dabbelt , Vineet Gupta , Jeff Law , Kito Cheng , Christoph Muellner , Philipp Tomsich Subject: [PATCH v2 1/2] RISC-V: Add basic support for the Ventana-VT1 core Date: Sun, 13 Nov 2022 21:48:23 +0100 Message-Id: <20221113204824.4062042-2-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221113204824.4062042-1-philipp.tomsich@vrull.eu> References: <20221113204824.4062042-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" The Ventana-VT1 core is compatible with rv64gc, Zb[abcs], Zifenci and XVentanaCondOps. This introduces a placeholder -mcpu=ventana-vt1, so tooling and scripts don't need to change once full support (pipeline, tuning, etc.) will become public later. gcc/ChangeLog: * config/riscv/riscv-cores.def (RISCV_TUNE): Add ventana-vt1. (RISCV_CORE): Ditto. * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): Ditto. * config/riscv/riscv.cc: Add tune_info for ventana-vt1. * config/riscv/riscv.md: Add ventana-vt1. * doc/gcc/gcc-command-options/machine-dependent-options/risc-v-options.rst: Document -mcpu= and -mtune with ventana-vt1. Signed-off-by: Philipp Tomsich --- Changes in v2: - Rebased and changed over to .rst-based documentation - Updated to catch more fusion cases - Signals support for Zifencei - Rebase to master, adjusting for the new way to define cores. - Change documentation to the new way (.rst) - Include Zifencei in the VT1 definition. gcc/config/riscv/riscv-cores.def | 3 +++ gcc/config/riscv/riscv-opts.h | 2 +- gcc/config/riscv/riscv.cc | 14 ++++++++++++++ .../machine-dependent-options/risc-v-options.rst | 5 +++-- 4 files changed, 21 insertions(+), 3 deletions(-) diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index 31ad34682c5..aef1e92ae24 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -38,6 +38,7 @@ RISCV_TUNE("sifive-3-series", generic, rocket_tune_info) RISCV_TUNE("sifive-5-series", generic, rocket_tune_info) RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info) RISCV_TUNE("thead-c906", generic, thead_c906_tune_info) +RISCV_TUNE("ventana-vt1", generic, ventana_vt1_tune_info) RISCV_TUNE("size", generic, optimize_size_tune_info) #undef RISCV_TUNE @@ -73,4 +74,6 @@ RISCV_CORE("sifive-s76", "rv64imafdc", "sifive-7-series") RISCV_CORE("sifive-u54", "rv64imafdc", "sifive-5-series") RISCV_CORE("sifive-u74", "rv64imafdc", "sifive-7-series") +RISCV_CORE("ventana-vt1", "rv64imafdc_zba_zbb_zbc_zbs_zifencei", "ventana-vt1") + #undef RISCV_CORE diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 84c987626bc..7962dbe5018 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -52,7 +52,7 @@ extern enum riscv_isa_spec_class riscv_isa_spec; /* Keep this list in sync with define_attr "tune" in riscv.md. */ enum riscv_microarchitecture_type { generic, - sifive_7 + sifive_7, }; extern enum riscv_microarchitecture_type riscv_microarchitecture; diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index c04e5db21df..31d651f8744 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -360,6 +360,20 @@ static const struct riscv_tune_param optimize_size_tune_info = { false, /* slow_unaligned_access */ }; +/* Costs to use when optimizing for Ventana Micro VT1. */ +static const struct riscv_tune_param ventana_vt1_tune_info = { + {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */ + {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */ + {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */ + {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */ + {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */ + 4, /* issue_rate */ + 4, /* branch_cost */ + 5, /* memory_cost */ + 8, /* fmv_cost */ + false, /* slow_unaligned_access */ +}; + static tree riscv_handle_fndecl_attribute (tree *, tree, tree, int, bool *); static tree riscv_handle_type_attribute (tree *, tree, tree, int, bool *); diff --git a/gcc/doc/gcc/gcc-command-options/machine-dependent-options/risc-v-options.rst b/gcc/doc/gcc/gcc-command-options/machine-dependent-options/risc-v-options.rst index 2b5167b56b2..5a0345ae2b3 100644 --- a/gcc/doc/gcc/gcc-command-options/machine-dependent-options/risc-v-options.rst +++ b/gcc/doc/gcc/gcc-command-options/machine-dependent-options/risc-v-options.rst @@ -95,14 +95,15 @@ These command-line options are defined for RISC-V targets: Permissible values for this option are: :samp:`sifive-e20`, :samp:`sifive-e21`, :samp:`sifive-e24`, :samp:`sifive-e31`, :samp:`sifive-e34`, :samp:`sifive-e76`, :samp:`sifive-s21`, :samp:`sifive-s51`, :samp:`sifive-s54`, :samp:`sifive-s76`, - :samp:`sifive-u54`, and :samp:`sifive-u74`. + :samp:`sifive-u54`, :samp:`sifive-u74`, and :samp:`ventana-vt1`. .. option:: -mtune={processor-string} Optimize the output for the given processor, specified by microarchitecture or particular CPU name. Permissible values for this option are: :samp:`rocket`, :samp:`sifive-3-series`, :samp:`sifive-5-series`, :samp:`sifive-7-series`, - :samp:`thead-c906`, :samp:`size`, and all valid options for :option:`-mcpu=`. + :samp:`thead-c906`, :samp:`ventana-vt1`, and :samp:`size`, and all valid + options for :option:`-mcpu=`. When :option:`-mtune=` is not specified, use the setting from :option:`-mcpu`, the default is :samp:`rocket` if both are not specified. From patchwork Sun Nov 13 20:48:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 60539 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D9CBF38AA265 for ; Sun, 13 Nov 2022 20:49:20 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by sourceware.org (Postfix) with ESMTPS id CDF1938582A1 for ; Sun, 13 Nov 2022 20:48:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org CDF1938582A1 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-lf1-x12e.google.com with SMTP id j4so16341804lfk.0 for ; Sun, 13 Nov 2022 12:48:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0BrkerkDROsR5ApAPblgKv8S2/iMF/udGV09TW2gzwM=; b=so+6en6w2HuA17dPdIlDTXRk9jR337J2kInrjIuXPquSQwP1DAorPzGspcIztuKHv+ GyO7e2YMEUxvyyLSIG6J8IOsziFoIkx5v9r795QX1/19G9kdPeV1xx9fv/8EJJkbm+Ug yer4eQ5mZLKBzMx2ytV4c3YjIw/xiSPbmxim3JFJsQ787PR6mSHZ5ZWd3QJ/+2+/5/yX 2F/67vj3jRYpNcxTOVUMvnqcvRkJsSMjDUBS8vYZl4hVcpIIvvgtYWUUo0lSQkPz7gxY Qie4Un+E54t9jV8mjK5YRzw9DQ68nTEe+yZu6IbQscwUG5N4p7AoQ+wmO82EUbrZAVcs ehyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0BrkerkDROsR5ApAPblgKv8S2/iMF/udGV09TW2gzwM=; b=h0X2FCG+pjdrGGaKbglVb0993fNQT38PUt59A1j5NQ7LcHQoFTX9R/qjV6pgWZt07d JENntX++DHfErEOhyXWD59P628UI4qJY23eI2+uhxO9aJZZBzZKkT31s778HljCpS4Vf G2lqIAhdG/5uHxeL4r95l9tOUEjg7oiKQsnpvtzqtJef6JhEgj9s/TalGdpskVnzdD82 xyNus+gch3rdKMAW3gmDfcu1xm1Y54nH9YD6CaSulgMEhrxmO/s2RVdvAmYIsRlPSBUH Qt62EjVrOMtZtJUw4CSZXqt6+YScVMrdletPeQGnxDk/IaKOH6LcFxkXJzSwrnDCXKzX qZ4g== X-Gm-Message-State: ANoB5pkiYIvsELf9KeTzUpV0V0GCz0XtN06dcoA8wQvZoKiJZNLW7k96 dL+qD6j9yXAoYu7I4Hynn1PIaT2lhxehx0Ab X-Google-Smtp-Source: AA0mqf61rb8MHQ0n/rvwyXCbugUfEdKExsHFZ+07cpF3HCSkSya4wyLk7j9Dr7TLrdfjT22rAcQxLg== X-Received: by 2002:a05:6512:b92:b0:4a7:66ba:df18 with SMTP id b18-20020a0565120b9200b004a766badf18mr3220130lfv.208.1668372509070; Sun, 13 Nov 2022 12:48:29 -0800 (PST) Received: from ubuntu-focal.. ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id m5-20020a056512114500b004979db5aa5bsm1520567lfg.223.2022.11.13.12.48.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 12:48:28 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Palmer Dabbelt , Vineet Gupta , Jeff Law , Kito Cheng , Christoph Muellner , Philipp Tomsich Subject: [PATCH v2 2/2] RISC-V: Add instruction fusion (for ventana-vt1) Date: Sun, 13 Nov 2022 21:48:24 +0100 Message-Id: <20221113204824.4062042-3-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221113204824.4062042-1-philipp.tomsich@vrull.eu> References: <20221113204824.4062042-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" The Ventana VT1 core supports quad-issue and instruction fusion. This implemented TARGET_SCHED_MACRO_FUSION_P to keep fusible sequences together and adds idiom matcheing for the supported fusion cases. gcc/ChangeLog: * config/riscv/riscv.cc (enum riscv_fusion_pairs): Add symbolic constants to identify supported fusion patterns. (struct riscv_tune_param): Add fusible_op field. (riscv_macro_fusion_p): Implement. (riscv_fusion_enabled_p): Implement. (riscv_macro_fusion_pair_p): Implement and recoginze fusible idioms for Ventana VT1. (TARGET_SCHED_MACRO_FUSION_P): Point to riscv_macro_fusion_p. (TARGET_SCHED_MACRO_FUSION_PAIR_P): Point to riscv_macro_fusion_pair_p. Signed-off-by: Philipp Tomsich --- Changes in v2: - Update fusion patterns and catch some missing idioms/fusion pairs. gcc/config/riscv/riscv.cc | 219 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 219 insertions(+) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 31d651f8744..43ba520885c 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -215,6 +215,19 @@ struct riscv_integer_op { The worst case is LUI, ADDI, SLLI, ADDI, SLLI, ADDI, SLLI, ADDI. */ #define RISCV_MAX_INTEGER_OPS 8 +enum riscv_fusion_pairs +{ + RISCV_FUSE_NOTHING = 0, + RISCV_FUSE_ZEXTW = (1 << 0), + RISCV_FUSE_ZEXTH = (1 << 1), + RISCV_FUSE_ZEXTWS = (1 << 2), + RISCV_FUSE_LDINDEXED = (1 << 3), + RISCV_FUSE_LUI_ADDI = (1 << 4), + RISCV_FUSE_AUIPC_ADDI = (1 << 5), + RISCV_FUSE_LUI_LD = (1 << 6), + RISCV_FUSE_AUIPC_LD = (1 << 7), +}; + /* Costs of various operations on the different architectures. */ struct riscv_tune_param @@ -229,6 +242,7 @@ struct riscv_tune_param unsigned short memory_cost; unsigned short fmv_cost; bool slow_unaligned_access; + unsigned int fusible_ops; }; /* Information about one micro-arch we know about. */ @@ -316,6 +330,7 @@ static const struct riscv_tune_param rocket_tune_info = { 5, /* memory_cost */ 8, /* fmv_cost */ true, /* slow_unaligned_access */ + RISCV_FUSE_NOTHING, /* fusible_ops */ }; /* Costs to use when optimizing for Sifive 7 Series. */ @@ -330,6 +345,7 @@ static const struct riscv_tune_param sifive_7_tune_info = { 3, /* memory_cost */ 8, /* fmv_cost */ true, /* slow_unaligned_access */ + RISCV_FUSE_NOTHING, /* fusible_ops */ }; /* Costs to use when optimizing for T-HEAD c906. */ @@ -344,6 +360,7 @@ static const struct riscv_tune_param thead_c906_tune_info = { 5, /* memory_cost */ 8, /* fmv_cost */ false, /* slow_unaligned_access */ + RISCV_FUSE_NOTHING, /* fusible_ops */ }; /* Costs to use when optimizing for size. */ @@ -358,6 +375,7 @@ static const struct riscv_tune_param optimize_size_tune_info = { 2, /* memory_cost */ 8, /* fmv_cost */ false, /* slow_unaligned_access */ + RISCV_FUSE_NOTHING, /* fusible_ops */ }; /* Costs to use when optimizing for Ventana Micro VT1. */ @@ -372,6 +390,10 @@ static const struct riscv_tune_param ventana_vt1_tune_info = { 5, /* memory_cost */ 8, /* fmv_cost */ false, /* slow_unaligned_access */ + ( RISCV_FUSE_ZEXTW | RISCV_FUSE_ZEXTH | /* fusible_ops */ + RISCV_FUSE_ZEXTWS | RISCV_FUSE_LDINDEXED | + RISCV_FUSE_LUI_ADDI | RISCV_FUSE_AUIPC_ADDI | + RISCV_FUSE_LUI_LD | RISCV_FUSE_AUIPC_LD ) }; static tree riscv_handle_fndecl_attribute (tree *, tree, tree, int, bool *); @@ -5627,6 +5649,199 @@ riscv_issue_rate (void) return tune_param->issue_rate; } +/* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports + instruction fusion of some sort. */ + +static bool +riscv_macro_fusion_p (void) +{ + return tune_param->fusible_ops != RISCV_FUSE_NOTHING; +} + +/* Return true iff the instruction fusion described by OP is enabled. */ + +static bool +riscv_fusion_enabled_p(enum riscv_fusion_pairs op) +{ + return tune_param->fusible_ops & op; +} + +/* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR + should be kept together during scheduling. */ + +static bool +riscv_macro_fusion_pair_p (rtx_insn *prev, rtx_insn *curr) +{ + rtx prev_set = single_set (prev); + rtx curr_set = single_set (curr); + /* prev and curr are simple SET insns i.e. no flag setting or branching. */ + bool simple_sets_p = prev_set && curr_set && !any_condjump_p (curr); + + if (!riscv_macro_fusion_p ()) + return false; + + if (simple_sets_p && (riscv_fusion_enabled_p (RISCV_FUSE_ZEXTW) || + riscv_fusion_enabled_p (RISCV_FUSE_ZEXTH))) + { + /* We are trying to match the following: + prev (slli) == (set (reg:DI rD) + (ashift:DI (reg:DI rS) (const_int 32))) + curr (slri) == (set (reg:DI rD) + (lshiftrt:DI (reg:DI rD) (const_int ))) + with being either 32 for FUSE_ZEXTW, or + `less than 32 for FUSE_ZEXTWS. */ + + if (GET_CODE (SET_SRC (prev_set)) == ASHIFT + && GET_CODE (SET_SRC (curr_set)) == LSHIFTRT + && REG_P (SET_DEST (prev_set)) + && REG_P (SET_DEST (curr_set)) + && REGNO (SET_DEST (prev_set)) == REGNO (SET_DEST (curr_set)) + && REGNO (XEXP (SET_SRC (curr_set), 0)) == REGNO(SET_DEST (curr_set)) + && CONST_INT_P (XEXP (SET_SRC (prev_set), 1)) + && CONST_INT_P (XEXP (SET_SRC (curr_set), 1)) + && INTVAL (XEXP (SET_SRC (prev_set), 1)) == 32 + && (( INTVAL (XEXP (SET_SRC (curr_set), 1)) == 32 + && riscv_fusion_enabled_p(RISCV_FUSE_ZEXTW) ) + || ( INTVAL (XEXP (SET_SRC (curr_set), 1)) < 32 + && riscv_fusion_enabled_p(RISCV_FUSE_ZEXTWS)))) + return true; + } + + if (simple_sets_p && riscv_fusion_enabled_p (RISCV_FUSE_ZEXTH)) + { + /* We are trying to match the following: + prev (slli) == (set (reg:DI rD) + (ashift:DI (reg:DI rS) (const_int 48))) + curr (slri) == (set (reg:DI rD) + (lshiftrt:DI (reg:DI rD) (const_int 48))) */ + + if (GET_CODE (SET_SRC (prev_set)) == ASHIFT + && GET_CODE (SET_SRC (curr_set)) == LSHIFTRT + && REG_P (SET_DEST (prev_set)) + && REG_P (SET_DEST (curr_set)) + && REGNO (SET_DEST (prev_set)) == REGNO (SET_DEST (curr_set)) + && REGNO (XEXP (SET_SRC (curr_set), 0)) == REGNO(SET_DEST (curr_set)) + && CONST_INT_P (XEXP (SET_SRC (prev_set), 1)) + && CONST_INT_P (XEXP (SET_SRC (curr_set), 1)) + && INTVAL (XEXP (SET_SRC (prev_set), 1)) == 48 + && INTVAL (XEXP (SET_SRC (curr_set), 1)) == 48) + return true; + } + + if (simple_sets_p && riscv_fusion_enabled_p (RISCV_FUSE_LDINDEXED)) + { + /* We are trying to match the following: + prev (add) == (set (reg:DI rD) + (plus:DI (reg:DI rS1) (reg:DI rS2)) + curr (ld) == (set (reg:DI rD) + (mem:DI (reg:DI rD))) */ + + if (MEM_P (SET_SRC (curr_set)) + && REG_P (XEXP (SET_SRC (curr_set), 0)) + && REGNO (XEXP (SET_SRC (curr_set), 0)) == REGNO (SET_DEST (prev_set)) + && GET_CODE (SET_SRC (prev_set)) == PLUS + && REG_P (XEXP (SET_SRC (prev_set), 0)) + && REG_P (XEXP (SET_SRC (prev_set), 1))) + return true; + + /* We are trying to match the following: + prev (add) == (set (reg:DI rD) + (plus:DI (reg:DI rS1) (reg:DI rS2))) + curr (lw) == (set (any_extend:DI (mem:SUBX (reg:DI rD)))) */ + + if ((GET_CODE (SET_SRC (curr_set)) == SIGN_EXTEND + || (GET_CODE (SET_SRC (curr_set)) == ZERO_EXTEND)) + && MEM_P (XEXP (SET_SRC (curr_set), 0)) + && REG_P (XEXP (XEXP (SET_SRC (curr_set), 0), 0)) + && REGNO (XEXP (XEXP (SET_SRC (curr_set), 0), 0)) == REGNO (SET_DEST (prev_set)) + && GET_CODE (SET_SRC (prev_set)) == PLUS + && REG_P (XEXP (SET_SRC (prev_set), 0)) + && REG_P (XEXP (SET_SRC (prev_set), 1))) + return true; + } + + if (simple_sets_p && riscv_fusion_enabled_p (RISCV_FUSE_LUI_ADDI)) + { + /* We are trying to match the following: + prev (lui) == (set (reg:DI rD) (const_int UPPER_IMM_20)) + curr (addi) == (set (reg:DI rD) + (plus:DI (reg:DI rD) (const_int IMM12))) */ + + if ((GET_CODE (SET_SRC (curr_set)) == LO_SUM + || (GET_CODE (SET_SRC (curr_set)) == PLUS + && CONST_INT_P (XEXP (SET_SRC (curr_set), 1)) + && SMALL_OPERAND (INTVAL (XEXP (SET_SRC (curr_set), 1))))) + && (GET_CODE (SET_SRC (prev_set)) == HIGH + || (CONST_INT_P (SET_SRC (prev_set)) + && LUI_OPERAND (INTVAL (SET_SRC (prev_set)))))) + return true; + } + + if (simple_sets_p && riscv_fusion_enabled_p (RISCV_FUSE_AUIPC_ADDI)) + { + /* We are trying to match the following: + prev (auipc) == (set (reg:DI rD) (unspec:DI [...] UNSPEC_AUIPC)) + curr (addi) == (set (reg:DI rD) + (plus:DI (reg:DI rD) (const_int IMM12))) + and + prev (auipc) == (set (reg:DI rD) (unspec:DI [...] UNSPEC_AUIPC)) + curr (addi) == (set (reg:DI rD) + (lo_sum:DI (reg:DI rD) (const_int IMM12))) */ + + if (GET_CODE (SET_SRC (prev_set)) == UNSPEC + && XINT (prev_set, 1) == UNSPEC_AUIPC + && (GET_CODE (SET_SRC (curr_set)) == LO_SUM + || (GET_CODE (SET_SRC (curr_set)) == PLUS + && SMALL_OPERAND (INTVAL (XEXP (SET_SRC (curr_set), 1)))))) + + return true; + } + + if (simple_sets_p && riscv_fusion_enabled_p (RISCV_FUSE_LUI_LD)) + { + /* We are trying to match the following: + prev (lui) == (set (reg:DI rD) (const_int UPPER_IMM_20)) + curr (ld) == (set (reg:DI rD) + (mem:DI (plus:DI (reg:DI rD) (const_int IMM12)))) */ + + if (CONST_INT_P (SET_SRC (prev_set)) + && LUI_OPERAND (INTVAL (SET_SRC (prev_set))) + && MEM_P (SET_SRC (curr_set)) + && GET_CODE (XEXP (SET_SRC (curr_set), 0)) == PLUS) + return true; + + if (GET_CODE (SET_SRC (prev_set)) == HIGH + && MEM_P (SET_SRC (curr_set)) + && GET_CODE (XEXP (SET_SRC (curr_set), 0)) == LO_SUM + && REGNO (SET_DEST (prev_set)) == REGNO (XEXP (XEXP (SET_SRC (curr_set), 0), 0))) + return true; + + if (GET_CODE (SET_SRC (prev_set)) == HIGH + && (GET_CODE (SET_SRC (curr_set)) == SIGN_EXTEND + || GET_CODE (SET_SRC (curr_set)) == ZERO_EXTEND) + && MEM_P (XEXP (SET_SRC (curr_set), 0)) + && (GET_CODE (XEXP (XEXP (SET_SRC (curr_set), 0), 0)) == LO_SUM + && REGNO (SET_DEST (prev_set)) == REGNO (XEXP (XEXP (XEXP (SET_SRC (curr_set), 0), 0), 0)))) + return true; + } + + if (simple_sets_p && riscv_fusion_enabled_p (RISCV_FUSE_AUIPC_LD)) + { + /* We are trying to match the following: + prev (auipc) == (set (reg:DI rD) (unspec:DI [...] UNSPEC_AUIPC)) + curr (ld) == (set (reg:DI rD) + (mem:DI (plus:DI (reg:DI rD) (const_int IMM12)))) */ + + if (GET_CODE (SET_SRC (prev_set)) == UNSPEC + && XINT (prev_set, 1) == UNSPEC_AUIPC + && MEM_P (SET_SRC (curr_set)) + && GET_CODE (XEXP (SET_SRC (curr_set), 0)) == PLUS) + return true; + } + + return false; +} + /* Auxiliary function to emit RISC-V ELF attribute. */ static void riscv_emit_attribute () @@ -6657,6 +6872,10 @@ riscv_shamt_matches_mask_p (int shamt, HOST_WIDE_INT mask) #undef TARGET_SCHED_ISSUE_RATE #define TARGET_SCHED_ISSUE_RATE riscv_issue_rate +#undef TARGET_SCHED_MACRO_FUSION_P +#define TARGET_SCHED_MACRO_FUSION_P riscv_macro_fusion_p +#undef TARGET_SCHED_MACRO_FUSION_PAIR_P +#define TARGET_SCHED_MACRO_FUSION_PAIR_P riscv_macro_fusion_pair_p #undef TARGET_FUNCTION_OK_FOR_SIBCALL #define TARGET_FUNCTION_OK_FOR_SIBCALL riscv_function_ok_for_sibcall