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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id z20-20020a195e54000000b004a05402c5c3sm2444440lfi.93.2022.11.09.15.07.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Nov 2022 15:07:38 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Vineet Gupta , Jeff Law , Palmer Dabbelt , Christoph Muellner , Kito Cheng , Philipp Tomsich Subject: [PATCH] RISC-V: Implement movmisalign to enable SLP Date: Thu, 10 Nov 2022 00:07:36 +0100 Message-Id: <20221109230736.3240512-1-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" The default implementation of support_vector_misalignment() checks whether movmisalign is present for the requested mode. This will be used by vect_supportable_dr_alignment() to determine whether a misaligned access of vectorized data is permissible. For RISC-V this is required to convert multiple integer data refs, such as "c[1] << 8) | c[0]" into a larger (in the example before: a halfword load) access. We conditionalize on !riscv_slow_unaligned_access_p to allow the misaligned refs, if they are not expected to be slow. This benefits both xalancbmk and blender on SPEC CPU 2017. gcc/ChangeLog: * config/riscv/riscv.md (movmisalign): Implement. gcc/testsuite/ChangeLog: * gcc.target/riscv/movmisalign-1.c: New test. * gcc.target/riscv/movmisalign-2.c: New test. * gcc.target/riscv/movmisalign-3.c: New test. Signed-off-by: Philipp Tomsich --- gcc/config/riscv/riscv.md | 18 ++++++++++++++++++ gcc/testsuite/gcc.target/riscv/movmisalign-1.c | 12 ++++++++++++ gcc/testsuite/gcc.target/riscv/movmisalign-2.c | 12 ++++++++++++ gcc/testsuite/gcc.target/riscv/movmisalign-3.c | 12 ++++++++++++ 4 files changed, 54 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/movmisalign-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/movmisalign-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/movmisalign-3.c diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 289ff7470c6..1b357a9c57f 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -1715,6 +1715,24 @@ MAX_MACHINE_MODE, &operands[3], TRUE); }) +;; Misaligned (integer) moves: provide an implementation for +;; movmisalign, so the default support_vector_misalignment() will +;; return the right boolean depending on whether +;; riscv_slow_unaligned_access_p is set or not. +;; +;; E.g., this is needed for SLP to convert "c[1] << 8) | c[0]" into a +;; HImode load (a good test case will be blender and xalancbmk in SPEC +;; CPU 2017). +;; +(define_expand "movmisalign" + [(set (match_operand:ANYI 0 "") + (match_operand:ANYI 1 ""))] + "!riscv_slow_unaligned_access_p" +{ + if (riscv_legitimize_move (mode, operands[0], operands[1])) + DONE; +}) + ;; 64-bit integer moves (define_expand "movdi" diff --git a/gcc/testsuite/gcc.target/riscv/movmisalign-1.c b/gcc/testsuite/gcc.target/riscv/movmisalign-1.c new file mode 100644 index 00000000000..791a3d63335 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movmisalign-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64 -mtune=size" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" } } */ + +void f(unsigned short *sink, unsigned char *arr) +{ + *sink = (arr[1] << 8) | arr[0]; +} + +/* { dg-final { scan-assembler-times "lhu\t" 1 } } */ +/* { dg-final { scan-assembler-not "lbu\t" } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/movmisalign-2.c b/gcc/testsuite/gcc.target/riscv/movmisalign-2.c new file mode 100644 index 00000000000..ef73dcb2d9d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movmisalign-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64 -mtune=size -mstrict-align" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" } } */ + +void f(unsigned short *sink, unsigned char *arr) +{ + *sink = (arr[1] << 8) | arr[0]; +} + +/* { dg-final { scan-assembler-times "lbu\t" 2 } } */ +/* { dg-final { scan-assembler-not "lhu\t" } } */ + diff --git a/gcc/testsuite/gcc.target/riscv/movmisalign-3.c b/gcc/testsuite/gcc.target/riscv/movmisalign-3.c new file mode 100644 index 00000000000..963b11c27fd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/movmisalign-3.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64 -mtune=rocket" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" } } */ + +void f(unsigned short *sink, unsigned char *arr) +{ + *sink = (arr[1] << 8) | arr[0]; +} + +/* { dg-final { scan-assembler-times "lbu\t" 2 } } */ +/* { dg-final { scan-assembler-not "lhu\t" } } */ +