From patchwork Tue Nov 8 18:20:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramana Radhakrishnan X-Patchwork-Id: 60221 X-Patchwork-Delegate: rearnsha@gcc.gnu.org Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0CD553858406 for ; Tue, 8 Nov 2022 18:21:05 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 0CD553858406 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1667931665; bh=Qt9bNEfRaSQy7i1Rw/EeJZGPKEXTy8sbcLyzvlSy0KE=; h=Date:Subject:To:Cc:List-Id:List-Unsubscribe:List-Archive: List-Post:List-Help:List-Subscribe:From:Reply-To:From; b=PZlikff6M7yVq2ZqiMP6pitoCuEAzjhP06d8ueOAV3MoPtHtDD9+PnDB3tWqw3Hcj WfWY7aBSh3KtJwJRttn5n6e2aQ2quj0/gJQfzWb0qw6IiRvA1B3hf+ZMiSsi+v4jlB ctJBwGGY58TzYv62bBXT57l9hwoAUEetknygmpQw= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by sourceware.org (Postfix) with ESMTPS id 15AE53858D3C for ; Tue, 8 Nov 2022 18:20:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 15AE53858D3C Received: by mail-wr1-x42c.google.com with SMTP id y16so22261490wrt.12 for ; Tue, 08 Nov 2022 10:20:33 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:mime-version:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=Qt9bNEfRaSQy7i1Rw/EeJZGPKEXTy8sbcLyzvlSy0KE=; b=om9MBEQiaH86wzWm/+U6jNoZsIfgkCZkZj8vB1jVGiVVZojrMt+5AO1adXcbqmQuX9 oZsc8GXBhAe50bhLckzqBlngfBMlZNQHGDt3kPVYHnQTWM8hrMIK3uMe5Ha8Zy3nghZ6 tzPndzhdQkYVNi5KimbI7Fvi5ueVXOY1RKu9AZQAAPvHwXR80cFPp7kRfO/jZqRzfvn7 LeoL4W4IB0ion6ttV9gQzXq9fAE14if3L6K4R4fA/MOSZOjQGQZIJfXX8efdo2QhjyUA nsGajuz/rm+3pcvCfU1G6hxQLty3F4CIYIe/g65DaUUzDMl+Cuyb556s515fdYfyVcz3 qrRA== X-Gm-Message-State: ACrzQf3fcREkyRP7k3cwrNObMFpSATTUzhC8O8UrYJ8O2JUufOWAaN1C lyzZRiwO4kUy4CcIQ+fbRTKYWpcFeBRED4m0dgokyIv+ X-Google-Smtp-Source: AMsMyM618pugQzqgZjFZn8dyMlhYKhFtvaD3+o1MbmhRtcgFGAVuKJVp+Asw5wug6pOZCyD73AHncBPtBDGgwxCG3oA= X-Received: by 2002:a5d:6185:0:b0:236:776f:2bed with SMTP id j5-20020a5d6185000000b00236776f2bedmr35796102wru.535.1667931631620; Tue, 08 Nov 2022 10:20:31 -0800 (PST) MIME-Version: 1.0 Date: Tue, 8 Nov 2022 18:20:20 +0000 Message-ID: Subject: [Patch Arm] Fix PR 92999 To: gcc-patches Cc: Richard Earnshaw X-Spam-Status: No, score=-8.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Ramana Radhakrishnan via Gcc-patches From: Ramana Radhakrishnan Reply-To: Ramana Radhakrishnan Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" PR92999 is a case where the VFP calling convention does not allocate enough FP registers for a homogenous aggregate containing FP16 values. I believe this is the complete fix but would appreciate another set of eyes on this. Could I get a hand with a regression test run on an armhf environment while I fix my environment ? gcc/ChangeLog: PR target/92999 * config/arm/arm.c (aapcs_vfp_allocate_return_reg): Adjust to handle aggregates with elements smaller than SFmode. gcc/testsuite/ChangeLog: * gcc.target/arm/pr92999.c: New test. Thanks, Ramana Signed-off-by: Ramana Radhakrishnan --- gcc/config/arm/arm.cc | 6 ++++- gcc/testsuite/gcc.target/arm/pr92999.c | 31 ++++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/arm/pr92999.c diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc index 2eb4d51e4a3..03f4057f717 100644 --- a/gcc/config/arm/arm.cc +++ b/gcc/config/arm/arm.cc @@ -6740,7 +6740,11 @@ aapcs_vfp_allocate_return_reg (enum arm_pcs pcs_variant ATTRIBUTE_UNUSED, count *= 2; } } - shift = GET_MODE_SIZE(ag_mode) / GET_MODE_SIZE(SFmode); + + /* Aggregates can contain FP16 or BF16 values which would need to + be passed in via FP registers. */ + shift = (MAX(GET_MODE_SIZE(ag_mode), GET_MODE_SIZE(SFmode)) + / GET_MODE_SIZE(SFmode)); par = gen_rtx_PARALLEL (mode, rtvec_alloc (count)); for (i = 0; i < count; i++) { diff --git a/gcc/testsuite/gcc.target/arm/pr92999.c b/gcc/testsuite/gcc.target/arm/pr92999.c new file mode 100644 index 00000000000..faa21fdb7d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr92999.c @@ -0,0 +1,31 @@ +/* { dg-do run } */ +/* { dg-options "-mfp16-format=ieee" } */ + +// +// Compile with gcc -mfp16-format=ieee +// Any optimization level is fine. +// +// Correct output should be +// "y.first = 1, y.second = -99" +// +// Buggy output is +// "y.first = -99, y.second = -99" +// +#include +struct phalf { + __fp16 first; + __fp16 second; +}; + +struct phalf phalf_copy(struct phalf* src) __attribute__((noinline)); +struct phalf phalf_copy(struct phalf* src) { + return *src; +} + +int main() { + struct phalf x = { 1.0, -99.0}; + struct phalf y = phalf_copy(&x); + if (y.first != 1.0 && y.second != -99.0) + abort(); + return 0; +}