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gcc-patches@gcc.gnu.org, kito.cheng@gmail.com, jim.wilson.gcc@gmail.com, palmer@dabbelt.com, andrew@sifive.com, juzhe.zhong@rivai.ai, jeffreyalaw@gmail.com, schwab@linux-m68k.org Subject: [PATCH] RISC-V: Fix RVV related testsuite Date: Sat, 5 Nov 2022 17:01:02 -0700 Message-Id: <20221106000102.18696-1-kito.cheng@sifive.com> X-Mailer: git-send-email 2.17.1 X-Spam-Status: No, score=-13.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kito Cheng Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Use wrapper of riscv_vector.h for RVV related testcases, more detail see https://gcc.gnu.org/pipermail/gcc-patches/2022-October/603140.html gcc/testsuite/ChangeLog: * gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c: Use double quotes to include riscv_vector.h rather than angle brackets. * gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c: Ditto. * gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c: Ditto. * gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c: Ditto. * gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c: Ditto. * gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c: Ditto. * gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c: Ditto. * gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c: Ditto. * gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c: Ditto. * gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c: Ditto. * gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c: Ditto. * gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c: Ditto. * gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c: Ditto. * gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c: Ditto. * gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c: Ditto. * gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c: Ditto. --- gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c | 2 +- gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c | 2 +- 16 files changed, 16 insertions(+), 16 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c index 6a235e308f9..cfc565b8922 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c @@ -2,7 +2,7 @@ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include +#include "riscv_vector.h" /* ** mov1: diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c index 10aa8297c30..419f19d0184 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c @@ -2,7 +2,7 @@ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include +#include "riscv_vector.h" /* ** mov1: diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c index f8da5bb6b93..1bb159c7099 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c @@ -2,7 +2,7 @@ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include +#include "riscv_vector.h" /* ** mov1: diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c index 5b8ce40b62d..7886886e2f5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c @@ -2,7 +2,7 @@ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include +#include "riscv_vector.h" /* ** mov14: diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c index 8c630f3bedb..9515e07eca1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -#include +#include "riscv_vector.h" void mov1 (int8_t *in, int8_t *out) { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c index b9bdd515747..301607a2906 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c @@ -2,7 +2,7 @@ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include +#include "riscv_vector.h" /* ** mov2: diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c index a7a89db2735..ea69ab2dbd5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c @@ -2,7 +2,7 @@ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include +#include "riscv_vector.h" /* ** mov3: diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c index e8cfb4b10b4..50bbd106692 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c @@ -2,7 +2,7 @@ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include +#include "riscv_vector.h" /* ** mov4: diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c index 5ca232ba867..680b4f42842 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c @@ -2,7 +2,7 @@ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include +#include "riscv_vector.h" /* ** mov3: diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c index 41fc73bb099..6348b38d9d7 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c @@ -2,7 +2,7 @@ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include +#include "riscv_vector.h" /* ** mov4: diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c index d4636e0adfb..c60920a8847 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c @@ -1,7 +1,7 @@ /* { dg-do compile } */ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ -#include +#include "riscv_vector.h" /* This testcase is testing whether RISC-V define REGMODE_NATURAL_SIZE. */ void foo (int8_t *in, int8_t *out) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c index 9447b05899d..f2cb244473f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c @@ -2,7 +2,7 @@ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include +#include "riscv_vector.h" /* ** mov1: diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c index 6d39e3c0f4d..902d65eb503 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c @@ -2,7 +2,7 @@ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ -#include +#include "riscv_vector.h" /* Test tieable of RVV types with same LMUL. */ /* diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c index fa643c58785..69c9c1fa5ca 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c @@ -2,7 +2,7 @@ /* { dg-additional-options "-O3" } */ /* { dg-skip-if "test intrinsic using rvv" { *-*-* } { "*" } { "-march=rv*v*zfh*" } } */ -#include +#include "riscv_vector.h" unsigned long vread_csr_vstart(void) { return vread_csr(RVV_VSTART); diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c index 661f2c9170e..60d3b499719 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c @@ -2,7 +2,7 @@ /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ #include -#include +#include "riscv_vector.h" size_t test_vsetvl_e8mf8_imm0() { diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c index e23da4b12ea..f9b4e8848df 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c @@ -2,7 +2,7 @@ /* { dg-additional-options "-O3" } */ /* { dg-skip-if "test intrinsic using rvv" { *-*-* } { "*" } { "-march=rv*v*zfh*" } } */ -#include +#include "riscv_vector.h" void vwrite_csr_vstart(unsigned long value) { vwrite_csr(RVV_VSTART, value);