From patchwork Wed Oct 26 07:49:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Huber X-Patchwork-Id: 59428 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 500BB3846425 for ; Wed, 26 Oct 2022 07:50:12 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from dedi548.your-server.de (dedi548.your-server.de [85.10.215.148]) by sourceware.org (Postfix) with ESMTPS id D6612385E032 for ; Wed, 26 Oct 2022 07:49:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D6612385E032 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embedded-brains.de Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=embedded-brains.de Received: from sslproxy03.your-server.de ([88.198.220.132]) by dedi548.your-server.de with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1onbAg-000PAO-95 for gcc-patches@gcc.gnu.org; Wed, 26 Oct 2022 09:49:53 +0200 Received: from [82.100.198.138] (helo=mail.embedded-brains.de) by sslproxy03.your-server.de with esmtpsa (TLSv1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1onbAf-0009Lz-RO for gcc-patches@gcc.gnu.org; Wed, 26 Oct 2022 09:49:53 +0200 Received: from localhost (localhost [127.0.0.1]) by mail.embedded-brains.de (Postfix) with ESMTP id 85EC7480025 for ; Wed, 26 Oct 2022 09:49:53 +0200 (CEST) Received: from mail.embedded-brains.de ([127.0.0.1]) by localhost (zimbra.eb.localhost [127.0.0.1]) (amavisd-new, port 10032) with ESMTP id FbwMbG5RwfbT for ; Wed, 26 Oct 2022 09:49:53 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by mail.embedded-brains.de (Postfix) with ESMTP id 31C974800CD for ; Wed, 26 Oct 2022 09:49:53 +0200 (CEST) X-Virus-Scanned: amavisd-new at zimbra.eb.localhost Received: from mail.embedded-brains.de ([127.0.0.1]) by localhost (zimbra.eb.localhost [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id NrwVLCrl3U11 for ; Wed, 26 Oct 2022 09:49:53 +0200 (CEST) Received: from zimbra.eb.localhost (unknown [192.168.96.242]) by mail.embedded-brains.de (Postfix) with ESMTPSA id 0FD3D480025 for ; Wed, 26 Oct 2022 09:49:53 +0200 (CEST) From: Sebastian Huber To: gcc-patches@gcc.gnu.org Subject: [PATCH] riscv/RTEMS: Add RISCV_GCOV_TYPE_SIZE Date: Wed, 26 Oct 2022 09:49:50 +0200 Message-Id: <20221026074950.10462-1-sebastian.huber@embedded-brains.de> X-Mailer: git-send-email 2.35.3 MIME-Version: 1.0 X-Authenticated-Sender: smtp-embedded@poldinet.de X-Virus-Scanned: Clear (ClamAV 0.103.7/26699/Tue Oct 25 09:58:49 2022) X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" The RV32A extension does not support 64-bit atomic operations. For RTEMS, use a 32-bit gcov type for RV32. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_gcov_type_size): New. (TARGET_GCOV_TYPE_SIZE): Likewise. * config/riscv/rtems.h (RISCV_GCOV_TYPE_SIZE): New. --- gcc/config/riscv/riscv.cc | 11 +++++++++++ gcc/config/riscv/rtems.h | 2 ++ 2 files changed, 13 insertions(+) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 4e18a43539a..1b7f4fb1981 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -6637,6 +6637,17 @@ riscv_vector_alignment (const_tree type) #undef TARGET_VECTOR_ALIGNMENT #define TARGET_VECTOR_ALIGNMENT riscv_vector_alignment +#ifdef RISCV_GCOV_TYPE_SIZE +static HOST_WIDE_INT +riscv_gcov_type_size (void) +{ + return RISCV_GCOV_TYPE_SIZE; +} + +#undef TARGET_GCOV_TYPE_SIZE +#define TARGET_GCOV_TYPE_SIZE riscv_gcov_type_size +#endif + struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-riscv.h" diff --git a/gcc/config/riscv/rtems.h b/gcc/config/riscv/rtems.h index 14e5e59caaa..3982b24382f 100644 --- a/gcc/config/riscv/rtems.h +++ b/gcc/config/riscv/rtems.h @@ -29,3 +29,5 @@ builtin_define ("__USE_INIT_FINI__"); \ builtin_assert ("system=rtems"); \ } while (0) + +#define RISCV_GCOV_TYPE_SIZE (TARGET_64BIT ? 64 : 32)