From patchwork Mon Oct 17 23:55:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jeff Law X-Patchwork-Id: 58965 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 12A133857BAE for ; Mon, 17 Oct 2022 23:55:39 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 12A133857BAE DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1666050939; bh=fHNLCTMCjE1n+zGsOcFYq8GngFsEMrJ+H+irZXoS83k=; h=Date:To:Subject:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=XQFp10kaGFPKDwC0c/3XoGBnv9Hp8alxRwFi8v8zVwS7KNhpCgwguyj2XBgAreIWs XL0uyN6slcRUXEJtl/QDnO4xsu813BKRwyw9LZtGee9NzjN/nf1zOTGz7jJmSVYmcJ g2JpSV7B0Zn3Z2ZaEvzna/oDktfPLR5wj+Eur1Yk= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by sourceware.org (Postfix) with ESMTPS id 2B2A33858C83 for ; Mon, 17 Oct 2022 23:55:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 2B2A33858C83 Received: by mail-pl1-x62e.google.com with SMTP id o21so9828245ple.5 for ; Mon, 17 Oct 2022 16:55:08 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=subject:from:to:content-language:user-agent:mime-version:date :message-id:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=fHNLCTMCjE1n+zGsOcFYq8GngFsEMrJ+H+irZXoS83k=; b=awT09DU62jx4cRarACvoTbpVT3wyD6Rp1F+9bJnAW5sJkwNTf2EMajeQpJZH2Nfz2o XKvgaSdN7Z23aUysQ3X1Si15nOj5C/vmFmslCJpHm/0APMVbWhBEy5ITluIm3z76MN2A Oy/8j2gjlYAtAiIPRvyCacR1ZwtsNDtwBtrT0mbzROhvyZyLsjo1bjlf1y3oL/C+p8/a GdrJsEIv+wKnYSmWRYX1caxu5XhLfU72+fq0SxAKZ8ewyiNsfcOENQNBSVrJ9yKXs8Lm /TixCv7Qzvt1a3SujqiliZTj5bgec9Q6dYkQrrTosJQTkc4p0aVgo1MniOgwufz2c36l rahw== X-Gm-Message-State: ACrzQf1yriNat3iiKK7gfo8dfWbUfTmgYkZ2bsTNPL+me87dKbQmg04u +43wfHGsiHmQBZJttIvFxFOV+nBruN4= X-Google-Smtp-Source: AMsMyM6kif2mUyHMeynlTvu0UgODy4HxTP8qiNgMBoDZgx1hzzdRad3/o6NNrO6fV1x0uzfYer720w== X-Received: by 2002:a17:90b:4d0d:b0:20d:6fc0:51 with SMTP id mw13-20020a17090b4d0d00b0020d6fc00051mr29306922pjb.10.1666050906641; Mon, 17 Oct 2022 16:55:06 -0700 (PDT) Received: from ?IPV6:2601:681:8600:13d0::f0a? ([2601:681:8600:13d0::f0a]) by smtp.gmail.com with ESMTPSA id x6-20020a170902a38600b00179988ca61bsm7079308pla.161.2022.10.17.16.55.05 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 17 Oct 2022 16:55:06 -0700 (PDT) Message-ID: <1f041491-d9d2-5fa2-c889-b29e91b69798@gmail.com> Date: Mon, 17 Oct 2022 17:55:05 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.3.1 Content-Language: en-US To: "gcc-patches@gcc.gnu.org" Subject: [committed][PR target/101697] Fix bogus RTL on the H8 X-Spam-Status: No, score=-8.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_NUMSUBJECT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Jeff Law via Gcc-patches From: Jeff Law Reply-To: Jeff Law Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This patch actually fixes the bogus RTL seen in PR101697. Basically we continue to use the insn condition to catch most of the problem cases related to autoinc addressing modes.  This patch adds constraints which can guide reload (and hopefully LRA) away from doing blind replacements during register elimination that would ultimately result in bogus RTL.  The idea is from Paul K who has done something very similar on the pdp11.  I guess it shouldn't be a big surprise that the H8 and pdp11 need the same kind of handling given some of the similarities in their architectures. Anyway, this has been tested in my tester without regressions. In fact, it fixes several bugs where the testsuite was tripping over the same problem.  Given this issue is covered by the testsuite, I haven't added a new test. Pushed to the trunk. Jeff commit 4374c424a60777a7658050f0aeb1dcc9af915647 Author: Jeff Law Date: Mon Oct 17 19:52:18 2022 -0400 Fix bogus RTL on the H8. This patch actually fixes the bogus RTL seen in PR101697. Basically we continue to use the insn condition to catch most of the problem cases related to autoinc addressing modes. This patch adds constraints which can guide reload (and hopefully LRA) away from doing blind replacements during register elimination that would ultimately result in bogus RTL. The idea is from Paul K. who has done something very similar on the pdp11. I guess it shouldn't be a big surprise that the H8 and pdp11 need the same kind of handling given some of the similarities in their architectures. gcc/ PR target/101697 * config/h8300/combiner.md: Replace '<' preincment constraint with ZA/Z1..ZH/Z7 combinations. * config/h8300/movepush.md: Similarly diff --git a/gcc/config/h8300/combiner.md b/gcc/config/h8300/combiner.md index 067f26678c1..fd5cf2f4af4 100644 --- a/gcc/config/h8300/combiner.md +++ b/gcc/config/h8300/combiner.md @@ -1142,8 +1142,8 @@ ;; Storing a part of HImode to QImode. (define_insn_and_split "" - [(set (match_operand:QI 0 "general_operand_dst" "=rm<") - (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r") + [(set (match_operand:QI 0 "general_operand_dst" "=rm,Za,Zb,Zc,Zd,Ze,Zf,Zg,Zh") + (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r,Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7") (const_int 8)) 1))] "" "#" @@ -1153,8 +1153,8 @@ (clobber (reg:CC CC_REG))])]) (define_insn "" - [(set (match_operand:QI 0 "general_operand_dst" "=rm<") - (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r") + [(set (match_operand:QI 0 "general_operand_dst" "=rm,Za,Zb,Zc,Zd,Ze,Zf,Zh,Zg") + (subreg:QI (lshiftrt:HI (match_operand:HI 1 "register_operand" "r,Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7") (const_int 8)) 1)) (clobber (reg:CC CC_REG))] "" @@ -1164,8 +1164,8 @@ ;; Storing a part of SImode to QImode. (define_insn_and_split "" - [(set (match_operand:QI 0 "general_operand_dst" "=rm<") - (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") + [(set (match_operand:QI 0 "general_operand_dst" "=rm,Za,Zb,Zc,Zd,Ze,Zf,Zh,Zg") + (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7") (const_int 8)) 3))] "" "#" @@ -1175,8 +1175,8 @@ (clobber (reg:CC CC_REG))])]) (define_insn "" - [(set (match_operand:QI 0 "general_operand_dst" "=rm<") - (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") + [(set (match_operand:QI 0 "general_operand_dst" "=rm,Za,Zb,Zc,Zd,Ze,Zf,Zh,Zg") + (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7") (const_int 8)) 3)) (clobber (reg:CC CC_REG))] "" @@ -1184,10 +1184,10 @@ [(set_attr "length" "8")]) (define_insn_and_split "" - [(set (match_operand:QI 0 "general_operand_dst" "=rm<") - (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") + [(set (match_operand:QI 0 "general_operand_dst" "=rm,Za,Zb,Zc,Zd,Ze,Zf,Zh,Zg") + (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7") (const_int 16)) 3)) - (clobber (match_scratch:SI 2 "=&r"))] + (clobber (match_scratch:SI 2 "=&r,&r,&r,&r,&r,&r,&r,&r,&r"))] "" "#" "&& reload_completed" @@ -1197,20 +1197,20 @@ (clobber (reg:CC CC_REG))])]) (define_insn "" - [(set (match_operand:QI 0 "general_operand_dst" "=rm<") - (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") + [(set (match_operand:QI 0 "general_operand_dst" "=rm,Za,Zb,Zc,Zd,Ze,Zf,Zh,Zg") + (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7") (const_int 16)) 3)) - (clobber (match_scratch:SI 2 "=&r")) + (clobber (match_scratch:SI 2 "=&r,&r,&r,&r,&r,&r,&r,&r,&r")) (clobber (reg:CC CC_REG))] "" "mov.w\\t%e1,%f2\;mov.b\\t%w2,%R0" [(set_attr "length" "10")]) (define_insn_and_split "" - [(set (match_operand:QI 0 "general_operand_dst" "=rm<") - (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") + [(set (match_operand:QI 0 "general_operand_dst" "=rm,Za,Zb,Zc,Zd,Ze,Zf,Zh,Zg") + (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7") (const_int 24)) 3)) - (clobber (match_scratch:SI 2 "=&r"))] + (clobber (match_scratch:SI 2 "=&r,&r,&r,&r,&r,&r,&r,&r,&r"))] "" "#" "&& reload_completed" @@ -1220,10 +1220,10 @@ (clobber (reg:CC CC_REG))])]) (define_insn "" - [(set (match_operand:QI 0 "general_operand_dst" "=rm<") - (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") + [(set (match_operand:QI 0 "general_operand_dst" "=rm,Za,Zb,Zc,Zd,Ze,Zf,Zh,Zg") + (subreg:QI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7") (const_int 24)) 3)) - (clobber (match_scratch:SI 2 "=&r")) + (clobber (match_scratch:SI 2 "=&r,&r,&r,&r,&r,&r,&r,&r,&r")) (clobber (reg:CC CC_REG))] "" "mov.w\\t%e1,%f2\;mov.b\\t%x2,%R0" diff --git a/gcc/config/h8300/movepush.md b/gcc/config/h8300/movepush.md index e895de8ce59..e536602a01d 100644 --- a/gcc/config/h8300/movepush.md +++ b/gcc/config/h8300/movepush.md @@ -5,8 +5,8 @@ ;; movqi (define_insn_and_split "*movqi" - [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m") - (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r"))] + [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,Za,Zb,Zc,Zd,Ze,Zf,Zg,Zh,r,r,m") + (match_operand:QI 1 "general_operand_src" " I,r>,Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7,n,m,r"))] "!TARGET_H8300SX && h8300_move_ok (operands[0], operands[1])" "#" "&& reload_completed" @@ -14,14 +14,21 @@ (clobber (reg:CC CC_REG))])]) (define_insn "*movqi" - [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,<,r,r,m") - (match_operand:QI 1 "general_operand_src" " I,r>,r,n,m,r")) + [(set (match_operand:QI 0 "general_operand_dst" "=r,r ,Za,Zb,Zc,Zd,Ze,Zf,Zg,Zh,r,r,m") + (match_operand:QI 1 "general_operand_src" " I,r>,Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7,n,m,r")) (clobber (reg:CC CC_REG))] "!TARGET_H8300SX && h8300_move_ok (operands[0], operands[1])" "@ sub.b %X0,%X0 mov.b %R1,%X0 mov.b %X1,%R0 + mov.b %X1,%R0 + mov.b %X1,%R0 + mov.b %X1,%R0 + mov.b %X1,%R0 + mov.b %X1,%R0 + mov.b %X1,%R0 + mov.b %X1,%R0 mov.b %R1,%X0 mov.b %R1,%X0 mov.b %X1,%R0" @@ -88,8 +95,8 @@ ;; movhi (define_insn_and_split "*movhi" - [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m") - (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r"))] + [(set (match_operand:HI 0 "general_operand_dst" "=r,r,Za,Zb,Zc,Zd,Ze,Zf,Zg,Zh,r,r,m") + (match_operand:HI 1 "general_operand_src" "I,r>,Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7,i,m,r"))] "!TARGET_H8300SX && h8300_move_ok (operands[0], operands[1])" "#" @@ -98,8 +105,8 @@ (clobber (reg:CC CC_REG))])]) (define_insn "*movhi" - [(set (match_operand:HI 0 "general_operand_dst" "=r,r,<,r,r,m") - (match_operand:HI 1 "general_operand_src" "I,r>,r,i,m,r")) + [(set (match_operand:HI 0 "general_operand_dst" "=r,r,Za,Zb,Zc,Zd,Ze,Zf,Zg,Zh,r,r,m") + (match_operand:HI 1 "general_operand_src" "I,r>,Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7,i,m,r")) (clobber (reg:CC CC_REG))] "!TARGET_H8300SX && h8300_move_ok (operands[0], operands[1])" @@ -109,6 +116,13 @@ mov.w %T1,%T0 mov.w %T1,%T0 mov.w %T1,%T0 + mov.w %T1,%T0 + mov.w %T1,%T0 + mov.w %T1,%T0 + mov.w %T1,%T0 + mov.w %T1,%T0 + mov.w %T1,%T0 + mov.w %T1,%T0 mov.w %T1,%T0" [(set (attr "length") (symbol_ref "compute_mov_length (operands)"))]) @@ -158,8 +172,8 @@ ;; movsi (define_insn_and_split "*movsi" - [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a,r") - (match_operand:SI 1 "general_operand_src" "I,r,i,r,>,m,r,I,r,*a"))] + [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,Za,Zb,Zc,Zd,Ze,Zf,Zg,Zh,r,r,m,*a,*a,r") + (match_operand:SI 1 "general_operand_src" "I,r,i,Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7,>,m,r,I,r,*a"))] "(TARGET_H8300S || TARGET_H8300H) && !TARGET_H8300SX && h8300_move_ok (operands[0], operands[1])" "#" @@ -168,8 +182,8 @@ (clobber (reg:CC CC_REG))])]) (define_insn "*movsi_clobber_flags" - [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m,*a,*a, r") - (match_operand:SI 1 "general_operand_src" " I,r,i,r,>,m,r, I, r,*a")) + [(set (match_operand:SI 0 "general_operand_dst" "=r,r,r,Za,Zb,Zc,Zd,Ze,Zf,Zg,Zh,r,r,m,*a,*a, r") + (match_operand:SI 1 "general_operand_src" " I,r,i,Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7,>,m,r, I, r,*a")) (clobber (reg:CC CC_REG))] "(TARGET_H8300S || TARGET_H8300H) && !TARGET_H8300SX && h8300_move_ok (operands[0], operands[1])" @@ -178,11 +192,11 @@ { case 0: return "sub.l %S0,%S0"; - case 7: + case 14: return "clrmac"; - case 8: + case 15: return "clrmac\;ldmac %1,macl"; - case 9: + case 16: return "stmac macl,%0"; default: if (GET_CODE (operands[1]) == CONST_INT) @@ -238,9 +252,9 @@ (define_insn "*movsi_cczn" [(set (reg:CCZN CC_REG) (compare:CCZN - (match_operand:SI 1 "general_operand_src" " I,r,i,r,>,m,r") + (match_operand:SI 1 "general_operand_src" " I,r,i,Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7,>,m,r") (const_int 0))) - (set (match_operand:SI 0 "general_operand_dst" "=r,r,r,<,r,r,m") + (set (match_operand:SI 0 "general_operand_dst" "=r,r,r,Za,Zb,Zc,Zd,Ze,Zf,Zg,Zh,r,r,m") (match_dup 1))] "(TARGET_H8300S || TARGET_H8300H) && !TARGET_H8300SX && h8300_move_ok (operands[0], operands[1])" @@ -251,6 +265,13 @@ mov.l %S1,%S0 mov.l %S1,%S0 mov.l %S1,%S0 + mov.l %S1,%S0 + mov.l %S1,%S0 + mov.l %S1,%S0 + mov.l %S1,%S0 + mov.l %S1,%S0 + mov.l %S1,%S0 + mov.l %S1,%S0 mov.l %S1,%S0" [(set (attr "length") (symbol_ref "compute_mov_length (operands)"))]) @@ -316,8 +337,8 @@ (set_attr "length_table" "*,movl")]) (define_insn_and_split "*movsf" - [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r") - (match_operand:SF 1 "general_operand_src" "G,r,im,r,r,>"))] + [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,Za,Zb,Zc,Zd,Ze,Zf,Zg,Zh,r") + (match_operand:SF 1 "general_operand_src" "G,r,im,r,Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7,>"))] "!TARGET_H8300SX && (register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode))" @@ -327,8 +348,8 @@ (clobber (reg:CC CC_REG))])]) (define_insn "*movsf_clobber_flags" - [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,<,r") - (match_operand:SF 1 "general_operand_src" "G,r,im,r,r,>")) + [(set (match_operand:SF 0 "general_operand_dst" "=r,r,r,m,Za,Zb,Zc,Zd,Ze,Zf,Zg,Zh,r") + (match_operand:SF 1 "general_operand_src" "G,r,im,r,Z0,Z1,Z2,Z3,Z4,Z5,Z6,Z7,>")) (clobber (reg:CC CC_REG))] "!TARGET_H8300SX && (register_operand (operands[0], SFmode) @@ -339,6 +360,13 @@ mov.l %S1,%S0 mov.l %S1,%S0 mov.l %S1,%S0 + mov.l %S1,%S0 + mov.l %S1,%S0 + mov.l %S1,%S0 + mov.l %S1,%S0 + mov.l %S1,%S0 + mov.l %S1,%S0 + mov.l %S1,%S0 mov.l %S1,%S0" [(set (attr "length") (symbol_ref "compute_mov_length (operands)"))])