From patchwork Thu Oct 13 23:56:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 58822 From: segher@kernel.crashing.org (Segher Boessenkool) Date: Thu, 13 Oct 2022 23:56:03 +0000 Subject: [PATCH] Always enable LRA Message-ID: This small patch changes everything that checks targetm.lra_p behave as if it returned true. It has no effect on any primary or secondary target. It also is fine for nds32 and for nios2, and it works fine for microblaze (which used old reload before), resulting in smaller code. I have patches to completely rip out old reload, and more stuff after that, but of course not everything is nice yet: It makes a few targets no longer build though. In my testing (of all linux targets that built before) these are alpha, c6x, h8300, m68k, 32-bit parisc, sh, and xtensa. alpha builds the compiler, but it then crashes with /home/segher/src/kernel/drivers/tty/serial/serial_core.c:1029:1: internal compiler error: maximum number of generated reload insns per insn achieved (90) (and in three more files) which can mean anything unfortunately. c6x is more exciting: /home/segher/src/kernel/fs/char_dev.c:598:1: internal compiler error: in priority, at haifa-sched.cc:1597 which is /* We should not be interested in priority of an already scheduled insn. */ gcc_assert (QUEUE_INDEX (insn) != QUEUE_SCHEDULED); h8300 fails during GCC build: /home/segher/src/gcc/libgcc/unwind.inc: In function '_Unwind_SjLj_RaiseException': /home/segher/src/gcc/libgcc/unwind.inc:141:1: error: could not split insn 141 | } | ^ (insn 69 256 327 (set (mem/f:SI (pre_dec:SI (reg/f:SI 7 sp)) [12 S4 A32]) (reg/f:SI 7 sp)) "/home/segher/src/gcc/libgcc/unwind.inc":118:12 19 {*movsi} (expr_list:REG_ARGS_SIZE (const_int 4 [0x4]) (nil))) during RTL pass: final which looks like a backend bug, I don't see a pattern that could split this (without needing an extra clobber)? m68k builds the compiler fine, but then has /home/segher/src/kernel/fs/squashfs/namei.c: In function 'squashfs_lookup': /home/segher/src/kernel/fs/squashfs/namei.c:232:1: error: insn does not satisfy its constraints: 232 | } | ^ (insn 270 470 271 30 (set (mem:SI (pre_dec:SI (reg/f:SI 15 %sp)) [1 S4 A16]) (plus:SI (sign_extend:SI (reg:HI 8 %a0 [175])) (reg:SI 2 %d2 [orig:173 val ] [173]))) "/home/segher/src/kernel/fs/squashfs/namei.c":212:13 77 {pushasi} (expr_list:REG_ARGS_SIZE (const_int 4 [0x4]) (nil))) during RTL pass: postreload /home/segher/src/kernel/fs/squashfs/namei.c:232:1: internal compiler error: in extract_constrain_insn, at recog.cc:2692 (and similar in two more files). 32-bit parisc now runs into the 90 reloads thing (parisc64 already did without the patch). sh doesn't build GCC: /home/segher/src/gcc/libgcc/libgcc2.c: In function '__divdc3': /home/segher/src/gcc/libgcc/libgcc2.c:2182:1: error: unable to generate reloads for: 2182 | } | ^ (call_insn/u 132 131 1855 7 (parallel [ (set (reg:SI 0 r0) (call (mem:SI (symbol_ref:SI ("__ltdf2") [flags 0x41] ) [0 S4 A32]) (const_int 0 [0]))) (use (reg:SI 154 fpscr0)) (use (reg:SI 12 r12)) (clobber (reg:SI 146 pr)) (clobber (reg:SI 758)) ]) "/home/segher/src/gcc/libgcc/libgcc2.c":2082:7 233 {call_value_pcrel} (expr_list:REG_DEAD (reg:DF 6 r6) (expr_list:REG_DEAD (reg:DF 4 r4) (expr_list:REG_CALL_DECL (symbol_ref:SI ("__ltdf2") [flags 0x41] ) (expr_list:REG_EH_REGION (const_int -2147483648 [0xffffffff80000000]) (nil))))) (expr_list (use (reg:DF 6 r6)) (expr_list (use (reg:DF 4 r4)) (nil)))) during RTL pass: reload And finally, xtensa does /home/segher/src/gcc/libgcc/libgcc2.c:840:1: error: insn does not satisfy its constraints: 840 | } | ^ (insn 8 7 9 2 (set (reg:SI 9 a9 [57]) (const_int 1431655765 [0x55555555])) "/home/segher/src/gcc/libgcc/libgcc2.c":828:21 37 {movsi_internal} (expr_list:REG_EQUIV (const_int 1431655765 [0x55555555]) (nil))) during RTL pass: postreload /home/segher/src/gcc/libgcc/libgcc2.c:840:1: internal compiler error: in extract_constrain_insn, at recog.cc:2692 - ~ - ~ - All in all, more worked than expected. I think it is time to finally make this switch. I did not test targets without a linux port. I build the linux kernel as well, to see if the resulting compiler actually works :-) Suggestions what to use for other targets are welcome. Is there any way to get the final targets updated for LRA? Other rants? :-) Segher --- gcc/auto-inc-dec.cc | 2 +- gcc/combine.cc | 2 +- gcc/ira-lives.cc | 5 ----- gcc/ira.cc | 2 +- gcc/recog.cc | 2 +- gcc/targhooks.cc | 4 ---- 6 files changed, 4 insertions(+), 13 deletions(-) diff --git a/gcc/auto-inc-dec.cc b/gcc/auto-inc-dec.cc index 481e7af..0186c17 100644 --- a/gcc/auto-inc-dec.cc +++ b/gcc/auto-inc-dec.cc @@ -1443,7 +1443,7 @@ merge_in_block (int max_reg, basic_block bb) /* Reload should handle auto-inc within a jump correctly, while LRA is known to have issues with autoinc. */ - if (JUMP_P (insn) && targetm.lra_p ()) + if (JUMP_P (insn)) continue; if (dump_file) diff --git a/gcc/combine.cc b/gcc/combine.cc index a5fabf3..64a96c6 100644 --- a/gcc/combine.cc +++ b/gcc/combine.cc @@ -2026,7 +2026,7 @@ can_combine_p (rtx_insn *insn, rtx_insn *i3, rtx_insn *pred ATTRIBUTE_UNUSED, if (AUTO_INC_DEC) for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) if (REG_NOTE_KIND (link) == REG_INC - && ((JUMP_P (i3) && targetm.lra_p ()) + && (JUMP_P (i3) || reg_used_between_p (XEXP (link, 0), insn, i3) || (pred != NULL_RTX && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred))) diff --git a/gcc/ira-lives.cc b/gcc/ira-lives.cc index 7a92c44..87b2d52 100644 --- a/gcc/ira-lives.cc +++ b/gcc/ira-lives.cc @@ -1133,11 +1133,6 @@ find_call_crossed_cheap_reg (rtx_insn *insn) rtx non_conflicting_reg_copy_p (rtx_insn *insn) { - /* Reload has issues with overlapping pseudos being assigned to the - same hard register, so don't allow it. See PR87600 for details. */ - if (!targetm.lra_p ()) - return NULL_RTX; - rtx set = single_set (insn); /* Disallow anything other than a simple register to register copy diff --git a/gcc/ira.cc b/gcc/ira.cc index 42c9cea..02a2f7b 100644 --- a/gcc/ira.cc +++ b/gcc/ira.cc @@ -1664,7 +1664,7 @@ ira_init_once (void) ira_init_costs_once (); lra_init_once (); - ira_use_lra_p = targetm.lra_p (); + ira_use_lra_p = 1; } /* Free ira_max_register_move_cost, ira_may_move_in_cost and diff --git a/gcc/recog.cc b/gcc/recog.cc index dac172b..6f41022 100644 --- a/gcc/recog.cc +++ b/gcc/recog.cc @@ -3242,7 +3242,7 @@ constrain_operands (int strict, alternative_mask alternatives) || (strict < 0 && CONSTANT_P (op)) /* Before reload, accept a pseudo or hard register, since LRA can turn it into a mem. */ - || (strict < 0 && targetm.lra_p () && REG_P (op)) + || (strict < 0 && REG_P (op)) /* During reload, accept a pseudo */ || (reload_in_progress && REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER))) diff --git a/gcc/targhooks.cc b/gcc/targhooks.cc index d17d393..c7f92c4 100644 --- a/gcc/targhooks.cc +++ b/gcc/targhooks.cc @@ -1380,10 +1380,6 @@ default_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x ATTRIBUTE_UNUSED, machine_mode default_secondary_memory_needed_mode (machine_mode mode) { - if (!targetm.lra_p () - && known_lt (GET_MODE_BITSIZE (mode), BITS_PER_WORD) - && INTEGRAL_MODE_P (mode)) - return mode_for_size (BITS_PER_WORD, GET_MODE_CLASS (mode), 0).require (); return mode; }