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Thu, 18 Aug 2022 21:48:31 +0000 (GMT) Date: Thu, 18 Aug 2022 17:48:29 -0400 To: gcc-patches@gcc.gnu.org, Michael Meissner , Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner , Will Schmidt Subject: [PATCH] Improve converting between 128-bit modes that use the same format Message-ID: Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner , Will Schmidt MIME-Version: 1.0 Content-Disposition: inline X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: fNKg1CN2cMie85fn8McZ7EUJMxA2-FtB X-Proofpoint-GUID: TS4NwAIV6Dc-DiaT_A-JO00LXyuljr-C X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-18_16,2022-08-18_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 suspectscore=0 bulkscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 impostorscore=0 priorityscore=1501 spamscore=0 mlxscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2208180077 X-Spam-Status: No, score=-10.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_MANYTO, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Michael Meissner via Gcc-patches From: Michael Meissner Reply-To: Michael Meissner Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" mprove converting between 128-bit modes that use the same format. This patch improves the insns used for converting between two modes using the 128-bit floating point format (i.e. converting between KFmode and TFmode if -mabi=ieeelongdouble is used, and converting between IFmode and TFmode if -mabi=ibmlongdouble is used). The new insns have the correct insn type and instruction length for the move involved. Previously, the two different moves were lumped together (i.e. converting between IEEE 128-bit and IEEE 128-bit was matched by the same insns as converting between IBM 128-bit and IBM 128-bit moves). I have tested this patch on the following systems: 1) LE Power10 using --with-cpu=power10 --with-long-double-format=ieee 2) LE Power10 using --with-cpu=power9 --with-long-double-format=ibm 3) LE Power10 using --with-cpu=power8 --with-long-double-format=ibm 4) LE Power10 using --with-cpu=power10 --with-long-double-format=ibm 5) LE Power9 using --with-cpu=power9 --with-long-double-format=ibm 6) BE Power8 using --with-cpu=power8 --with-long-double-format=ibm 7) BE Power8 using --with-cpu=power5 --with-long-double-format=ibm There were no regressions in the build or in the tests. On the power10 with long double using the IEEE 128-bit format, pr105334.c now runs where it previously failed. Can I check this patch into the trunk? Did we want to backport this to earlier GCC releases? 2022-08-17 Michael Meissner gcc/ * config/rs6000/rs6000.md (IFKF): Delete. (IFKF_reg): Delete. (extendkfif2): New define_expand. (trunckfif2): New define_expand. (extendtf2_internal): Split into extendiftf2_internal and extendkftf2_internal. Update the insns to use the correct insn type and length attributes based on whether the move uses IEEE 128-bit floating point or IBM 128-bit floating point type. (extendiftf2_internal): Likewise. (extendkftf2_internal): Likewise. (extendtf2_internal): Split into extendtfif2_internal and extendtfkf2_internal. Update the insns to use the correct insn type and length attributes based on whether the move uses IEEE 128-bit floating e point or IBM 128-bit floating point type. (extendtfif2_internal): Likewise. (extendtfkf2_internal): Likewise. --- gcc/config/rs6000/rs6000.md | 94 +++++++++++++++++++++++++++++-------- 1 file changed, 74 insertions(+), 20 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index f942597c3b4..e17252bb8de 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -543,12 +543,6 @@ (define_mode_iterator FMOVE128_GPR [TI ; Iterator for 128-bit VSX types for pack/unpack (define_mode_iterator FMOVE128_VSX [V1TI KF]) -; Iterators for converting to/from TFmode -(define_mode_iterator IFKF [IF KF]) - -; Constraints for moving IF/KFmode. -(define_mode_attr IFKF_reg [(IF "d") (KF "wa")]) - ; Whether a floating point move is ok, don't allow SD without hardware FP (define_mode_attr fmove_ok [(SF "") (DF "") @@ -9075,6 +9069,15 @@ (define_expand "extendifkf2" DONE; }) +(define_expand "extendkfif2" + [(set (match_operand:IF 0 "gpc_reg_operand") + (float_extend:IF (match_operand:KF 1 "gpc_reg_operand")))] + "TARGET_FLOAT128_TYPE" +{ + rs6000_expand_float128_convert (operands[0], operands[1], false); + DONE; +}) + (define_expand "extendtfkf2" [(set (match_operand:KF 0 "gpc_reg_operand") (float_extend:KF (match_operand:TF 1 "gpc_reg_operand")))] @@ -9111,6 +9114,15 @@ (define_expand "truncifkf2" DONE; }) +(define_expand "trunckfif2" + [(set (match_operand:IF 0 "gpc_reg_operand") + (float_truncate:IF (match_operand:KF 1 "gpc_reg_operand")))] + "TARGET_FLOAT128_TYPE" +{ + rs6000_expand_float128_convert (operands[0], operands[1], false); + DONE; +}) + (define_expand "trunckftf2" [(set (match_operand:TF 0 "gpc_reg_operand") (float_truncate:TF (match_operand:KF 1 "gpc_reg_operand")))] @@ -9129,31 +9141,73 @@ (define_expand "trunctfif2" DONE; }) -(define_insn_and_split "*extendtf2_internal" - [(set (match_operand:TF 0 "gpc_reg_operand" "=") +;; Convert between KFmode and TFmode when -mabi=ieeelongdouble +(define_insn_and_split "*extendkftf2_internal" + [(set (match_operand:TF 0 "gpc_reg_operand" "=wa,wa") (float_extend:TF - (match_operand:IFKF 1 "gpc_reg_operand" "")))] - "TARGET_FLOAT128_TYPE - && FLOAT128_IBM_P (TFmode) == FLOAT128_IBM_P (mode)" + (match_operand:KF 1 "gpc_reg_operand" "0,wa")))] + "FLOAT128_IEEE_P (TFmode)" "#" "&& reload_completed" [(set (match_dup 0) (match_dup 2))] { operands[2] = gen_rtx_REG (TFmode, REGNO (operands[1])); -}) +} + [(set_attr "type" "vecsimple")]) -(define_insn_and_split "*extendtf2_internal" - [(set (match_operand:IFKF 0 "gpc_reg_operand" "=") - (float_extend:IFKF - (match_operand:TF 1 "gpc_reg_operand" "")))] - "TARGET_FLOAT128_TYPE - && FLOAT128_IBM_P (TFmode) == FLOAT128_IBM_P (mode)" +(define_insn_and_split "*extendtfkf2_internal" + [(set (match_operand:KF 0 "gpc_reg_operand" "=wa,wa") + (float_extend:KF + (match_operand:TF 1 "gpc_reg_operand" "0,wa")))] + "FLOAT128_IEEE_P (TFmode)" "#" "&& reload_completed" [(set (match_dup 0) (match_dup 2))] { - operands[2] = gen_rtx_REG (mode, REGNO (operands[1])); -}) + operands[2] = gen_rtx_REG (KFmode, REGNO (operands[1])); +} + [(set_attr "type" "vecsimple")]) + +;; Convert between IFmode and TFmode when -mabi=ibmlongdouble +(define_insn_and_split "*extendiftf2_internal" + [(set (match_operand:TF 0 "gpc_reg_operand" "=d,&d") + (float_extend:TF + (match_operand:IF 1 "input_operand" "0,d")))] + "FLOAT128_IBM_P (TFmode)" + "#" + "&& reload_completed" + [(set (match_dup 2) (match_dup 3)) + (set (match_dup 4) (match_dup 5))] +{ + unsigned int op0_regno = reg_or_subregno (operands[0]); + unsigned int op1_regno = reg_or_subregno (operands[1]); + operands[2] = gen_rtx_REG (DFmode, op0_regno); + operands[3] = gen_rtx_REG (DFmode, op1_regno); + operands[4] = gen_rtx_REG (DFmode, op0_regno + 1); + operands[5] = gen_rtx_REG (DFmode, op1_regno + 1); +} + [(set_attr "type" "two") + (set_attr "num_insns" "2")]) + +(define_insn_and_split "*extendtfif2_internal" + [(set (match_operand:IF 0 "gpc_reg_operand" "=d,&d") + (float_extend:IF + (match_operand:TF 1 "input_operand" "0,d")))] + "FLOAT128_IBM_P (TFmode)" + "#" + "&& reload_completed" + [(set (match_dup 2) (match_dup 3)) + (set (match_dup 4) (match_dup 5))] +{ + unsigned int op0_regno = reg_or_subregno (operands[0]); + unsigned int op1_regno = reg_or_subregno (operands[1]); + operands[2] = gen_rtx_REG (DFmode, op0_regno); + operands[3] = gen_rtx_REG (DFmode, op1_regno); + operands[4] = gen_rtx_REG (DFmode, op0_regno + 1); + operands[5] = gen_rtx_REG (DFmode, op1_regno + 1); +} + [(set_attr "type" "two") + (set_attr "num_insns" "2")]) ;; Reload helper functions used by rs6000_secondary_reload. The patterns all