From patchwork Thu Aug 18 21:39:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 56863 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 86F273858292 for ; Thu, 18 Aug 2022 21:40:02 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 86F273858292 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1660858802; bh=g9Q2zCBsyS6CY770qIbXcYCljZkXxc1JcvJv4jTpzfY=; h=Date:To:Subject:References:In-Reply-To:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=Wdf4fVXycetw1hrCV3dGI+Gg411+iVVm7T0J2iJo2me3BdSOXw4G/453ii9jyfp7V iN4h6eMISa1JyJr1cAeH3+KGn+/ndvqvoMzwQWm0Om2tm0p+TL7e5tToD/Jq+Ot/YP 0IFVC0dbrloUnn7Sh5eKHOQpoeDQVoQY1wUI+Dn8= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) by sourceware.org (Postfix) with ESMTPS id 2623E3858D39 for ; Thu, 18 Aug 2022 21:39:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 2623E3858D39 Received: from pps.filterd (m0098409.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27ILT4BC006580; Thu, 18 Aug 2022 21:39:30 GMT Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3j1wcpg5am-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 18 Aug 2022 21:39:30 +0000 Received: from m0098409.ppops.net (m0098409.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 27ILTMtI006988; Thu, 18 Aug 2022 21:39:30 GMT Received: from ppma02dal.us.ibm.com (a.bd.3ea9.ip4.static.sl-reverse.com [169.62.189.10]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3j1wcpg5a4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 18 Aug 2022 21:39:30 +0000 Received: from pps.filterd (ppma02dal.us.ibm.com [127.0.0.1]) by ppma02dal.us.ibm.com (8.16.1.2/8.16.1.2) with SMTP id 27ILTZva006902; Thu, 18 Aug 2022 21:39:29 GMT Received: from b03cxnp08028.gho.boulder.ibm.com (b03cxnp08028.gho.boulder.ibm.com [9.17.130.20]) by ppma02dal.us.ibm.com with ESMTP id 3hx3kahch0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 18 Aug 2022 21:39:29 +0000 Received: from b03ledav002.gho.boulder.ibm.com (b03ledav002.gho.boulder.ibm.com [9.17.130.233]) by b03cxnp08028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 27ILdRpb13042292 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 18 Aug 2022 21:39:27 GMT Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9EBE5136053; Thu, 18 Aug 2022 21:39:27 +0000 (GMT) Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 02BF2136051; Thu, 18 Aug 2022 21:39:26 +0000 (GMT) Received: from toto.the-meissners.org (unknown [9.65.225.181]) by b03ledav002.gho.boulder.ibm.com (Postfix) with ESMTPS; Thu, 18 Aug 2022 21:39:26 +0000 (GMT) Date: Thu, 18 Aug 2022 17:39:25 -0400 To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner , Will Schmidt Subject: [PATCH 1/3] Allow __ibm128 even if IEEE 128-bit floating point is not supported. Message-ID: Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner , Will Schmidt References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-GUID: SSjts-_TDvZm9sYVbYfOjBZfosYq6Lpv X-Proofpoint-ORIG-GUID: RinYLf8DWFg00I9gr0btiL6niW4A-DW6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-18_16,2022-08-18_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 mlxlogscore=999 mlxscore=0 clxscore=1011 priorityscore=1501 lowpriorityscore=0 impostorscore=0 spamscore=0 malwarescore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2208180077 X-Spam-Status: No, score=-10.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_MANYTO, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Michael Meissner via Gcc-patches From: Michael Meissner Reply-To: Michael Meissner Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Allow __ibm128 even if IEEE 128-bit floating point is not supported. This patch allows the use of the __ibm128 keyword on non-VSX systems. Originally, the __ibm128 keyword was only enabled when the IEEE 128-bit floating point is enabled. Sometime back in the GCC 12 development period, Segher asked that the __ibm128 keyword be allowed in older systems that don't support IEEE 128-bit. But at the time, stage 1 had closed for GCC 12, so I deferred doing this change until GCC 13. This patch allows __ibm128 to be used if either IEEE 128-bit is enabled or long double used the IBM 128-bit format. I have tested these patches on the following systems: 1) LE Power10 using --with-cpu=power10 --with-long-double-format=ieee 2) LE Power10 using --with-cpu=power9 --with-long-double-format=ibm 3) LE Power10 using --with-cpu=power8 --with-long-double-format=ibm 4) LE Power10 using --with-cpu=power10 --with-long-double-format=ibm 5) LE Power9 using --with-cpu=power9 --with-long-double-format=ibm 6) BE Power8 using --with-cpu=power8 --with-long-double-format=ibm 7) BE Power8 using --with-cpu=power5 --with-long-double-format=ibm There were no regressions in the build or in the tests. Can I check this patch into the trunk? Did we want to backport this to earlier GCC releases? 2022-08-17 Michael Meissner gcc/ * config/rs6000/rs6000-builtins.cc (rs6000_init_builtins): Enable using the__ibm128 keyword on systems that either use the 128-bit IBM long double format for long double or support IEEE 128-bit. * config/rs6000/rs6000.cc (rs6000_init_libfuncs): Create IBM 128-bit floating point support functions on systems that support the __ibm128 keyword. (rs6000_scalar_mode_supported_p): Likewise. * config/rs6000/rs6000.h (TARGET_IBM128): New macro. * config/rs6000/rs6000.md (@extenddf2_fprs): Allow IFmode to be converted even if long double is not 128-bits. (extenddf2_vsx): Likewise. (extendiftf2):Allow conversion on systems that support the __ibm128 keyword. (extendtfif2): Likewise. (trunciftf2): Likewise. (trunctfif2): Likewise. --- gcc/config/rs6000/rs6000-builtin.cc | 2 +- gcc/config/rs6000/rs6000.cc | 13 ++++++++----- gcc/config/rs6000/rs6000.h | 6 ++++++ gcc/config/rs6000/rs6000.md | 13 ++++++------- 4 files changed, 21 insertions(+), 13 deletions(-) diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc index 12afa86854c..70680890415 100644 --- a/gcc/config/rs6000/rs6000-builtin.cc +++ b/gcc/config/rs6000/rs6000-builtin.cc @@ -713,7 +713,7 @@ rs6000_init_builtins (void) For IEEE 128-bit floating point, always create the type __ieee128. If the user used -mfloat128, rs6000-c.cc will create a define from __float128 to __ieee128. */ - if (TARGET_LONG_DOUBLE_128 && (!TARGET_IEEEQUAD || TARGET_FLOAT128_TYPE)) + if (TARGET_IBM128) { if (!TARGET_IEEEQUAD) ibm128_float_type_node = long_double_type_node; diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index df491bee2ea..39527ce9bbc 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -11115,10 +11115,11 @@ rs6000_init_libfuncs (void) { /* __float128 support. */ if (TARGET_FLOAT128_TYPE) - { - init_float128_ibm (IFmode); - init_float128_ieee (KFmode); - } + init_float128_ieee (KFmode); + + /* __ibm128 support. */ + if (TARGET_IBM128) + init_float128_ibm (IFmode); /* AIX/Darwin/64-bit Linux quad floating point routines. */ if (TARGET_LONG_DOUBLE_128) @@ -23752,7 +23753,9 @@ rs6000_scalar_mode_supported_p (scalar_mode mode) if (DECIMAL_FLOAT_MODE_P (mode)) return default_decimal_float_supported_p (); - else if (TARGET_FLOAT128_TYPE && (mode == KFmode || mode == IFmode)) + else if (TARGET_FLOAT128_TYPE && mode == KFmode) + return true; + else if (TARGET_IBM128 && mode == IFmode) return true; else return default_scalar_mode_supported_p (mode); diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index ad9bf0f7358..813ec696c0d 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -564,6 +564,12 @@ extern int rs6000_vector_align[]; && TARGET_P8_VECTOR \ && TARGET_POWERPC64) +/* Whether the __ibm128 keyword is allowed. Any system that supports _Float128 + is assumed to be capable of supporting __ibm128. Similarly if the long + double size is 128 bits, we assume __ibm128 is supported. We don't want to + support it on a system without existing 128-bit long doubles. */ +#define TARGET_IBM128 (TARGET_FLOAT128_TYPE || TARGET_LONG_DOUBLE_128) + /* Inlining allows targets to define the meanings of bits in target_info field of ipa_fn_summary by itself, the used bits for rs6000 are listed below. */ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 1367a2cb779..f942597c3b4 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -8586,8 +8586,7 @@ (define_insn_and_split "@extenddf2_fprs" (float_extend:IBM128 (match_operand:DF 1 "nonimmediate_operand" "d,m,d"))) (use (match_operand:DF 2 "nonimmediate_operand" "m,m,d"))] - "!TARGET_VSX && TARGET_HARD_FLOAT - && TARGET_LONG_DOUBLE_128 && FLOAT128_IBM_P (mode)" + "!TARGET_VSX && TARGET_HARD_FLOAT && FLOAT128_IBM_P (mode)" "#" "&& reload_completed" [(set (match_dup 3) (match_dup 1)) @@ -8604,7 +8603,7 @@ (define_insn_and_split "@extenddf2_vsx" [(set (match_operand:IBM128 0 "gpc_reg_operand" "=d,d") (float_extend:IBM128 (match_operand:DF 1 "nonimmediate_operand" "wa,m")))] - "TARGET_LONG_DOUBLE_128 && TARGET_VSX && FLOAT128_IBM_P (mode)" + "TARGET_VSX && FLOAT128_IBM_P (mode)" "#" "&& reload_completed" [(set (match_dup 2) (match_dup 1)) @@ -9061,7 +9060,7 @@ (define_insn "*ieee_128bit_vsx_nabs2_internal" (define_expand "extendiftf2" [(set (match_operand:TF 0 "gpc_reg_operand") (float_extend:TF (match_operand:IF 1 "gpc_reg_operand")))] - "TARGET_FLOAT128_TYPE" + "TARGET_IBM128" { rs6000_expand_float128_convert (operands[0], operands[1], false); DONE; @@ -9088,7 +9087,7 @@ (define_expand "extendtfkf2" (define_expand "extendtfif2" [(set (match_operand:IF 0 "gpc_reg_operand") (float_extend:IF (match_operand:TF 1 "gpc_reg_operand")))] - "TARGET_FLOAT128_TYPE" + "TARGET_IBM128" { rs6000_expand_float128_convert (operands[0], operands[1], false); DONE; @@ -9097,7 +9096,7 @@ (define_expand "extendtfif2" (define_expand "trunciftf2" [(set (match_operand:TF 0 "gpc_reg_operand") (float_truncate:TF (match_operand:IF 1 "gpc_reg_operand")))] - "TARGET_FLOAT128_TYPE" + "TARGET_IBM128" { rs6000_expand_float128_convert (operands[0], operands[1], false); DONE; @@ -9124,7 +9123,7 @@ (define_expand "trunckftf2" (define_expand "trunctfif2" [(set (match_operand:IF 0 "gpc_reg_operand") (float_truncate:IF (match_operand:TF 1 "gpc_reg_operand")))] - "TARGET_FLOAT128_TYPE" + "TARGET_IBM128" { rs6000_expand_float128_convert (operands[0], operands[1], false); DONE; From patchwork Thu Aug 18 21:41:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 56864 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 471673858436 for ; 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Thu, 18 Aug 2022 21:41:18 +0000 Received: from b03ledav005.gho.boulder.ibm.com (b03ledav005.gho.boulder.ibm.com [9.17.130.236]) by b03cxnp08026.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 27ILfH8g45089154 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 18 Aug 2022 21:41:17 GMT Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 196F1BE04F; Thu, 18 Aug 2022 21:41:17 +0000 (GMT) Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8A38ABE054; Thu, 18 Aug 2022 21:41:16 +0000 (GMT) Received: from toto.the-meissners.org (unknown [9.65.225.181]) by b03ledav005.gho.boulder.ibm.com (Postfix) with ESMTPS; Thu, 18 Aug 2022 21:41:16 +0000 (GMT) Date: Thu, 18 Aug 2022 17:41:14 -0400 To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner , Will Schmidt Subject: [PATCH 2/3] Allow __ibm128 with -msoft-float (PR target/105334) Message-ID: Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner , Will Schmidt References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 4MoNhgTdvjujYMJW4jj13n9ShELEgkQZ X-Proofpoint-ORIG-GUID: aNUzID6dLoXj1bcqRdhzdoBCfaHTq5S9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-18_16,2022-08-18_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxscore=0 mlxlogscore=884 lowpriorityscore=0 malwarescore=0 priorityscore=1501 suspectscore=0 impostorscore=0 phishscore=0 bulkscore=0 clxscore=1015 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2208180077 X-Spam-Status: No, score=-10.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_MANYTO, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Michael Meissner via Gcc-patches From: Michael Meissner Reply-To: Michael Meissner Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Allow __ibm128 with -msoft-float (PR target/105334) This patch allows __ibm128 to be used on systems with software floating point enabled. Previously, we required hardware floating point to be enabled to use __ibm128 keyword and the __ibm128 built-in functions. This patch fixes PR target/105334. I have tested this patch on the following systems: 1) LE Power10 using --with-cpu=power10 --with-long-double-format=ieee 2) LE Power10 using --with-cpu=power9 --with-long-double-format=ibm 3) LE Power10 using --with-cpu=power8 --with-long-double-format=ibm 4) LE Power10 using --with-cpu=power10 --with-long-double-format=ibm 5) LE Power9 using --with-cpu=power9 --with-long-double-format=ibm 6) BE Power8 using --with-cpu=power8 --with-long-double-format=ibm 7) BE Power8 using --with-cpu=power5 --with-long-double-format=ibm There were no regressions in the build or in the tests. On the power10 with long double using the IEEE 128-bit format, pr105334.c now runs where it previously failed. Can I check this patch into the trunk? Did we want to backport this to earlier GCC releases? 2022-08-17 Michael Meissner gcc/ PR target/105334 * config/rs6000/rs6000.cc (init_float128_ibm): Do not require hardware floating point for the IBM 128-bit floating point comparison functions. * config/rs6000/rs6000.h (FLOAT128_IBM_P): Do not require hardware floating point to enable recognizing IBM 128-bit floating point modes. --- gcc/config/rs6000/rs6000.cc | 37 +++++++++++++++++-------------------- gcc/config/rs6000/rs6000.h | 2 +- 2 files changed, 18 insertions(+), 21 deletions(-) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 39527ce9bbc..a6ec4c71ac0 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -10913,26 +10913,23 @@ init_float128_ibm (machine_mode mode) set_optab_libfunc (smul_optab, mode, "__gcc_qmul"); set_optab_libfunc (sdiv_optab, mode, "__gcc_qdiv"); - if (!TARGET_HARD_FLOAT) - { - set_optab_libfunc (neg_optab, mode, "__gcc_qneg"); - set_optab_libfunc (eq_optab, mode, "__gcc_qeq"); - set_optab_libfunc (ne_optab, mode, "__gcc_qne"); - set_optab_libfunc (gt_optab, mode, "__gcc_qgt"); - set_optab_libfunc (ge_optab, mode, "__gcc_qge"); - set_optab_libfunc (lt_optab, mode, "__gcc_qlt"); - set_optab_libfunc (le_optab, mode, "__gcc_qle"); - set_optab_libfunc (unord_optab, mode, "__gcc_qunord"); - - set_conv_libfunc (sext_optab, mode, SFmode, "__gcc_stoq"); - set_conv_libfunc (sext_optab, mode, DFmode, "__gcc_dtoq"); - set_conv_libfunc (trunc_optab, SFmode, mode, "__gcc_qtos"); - set_conv_libfunc (trunc_optab, DFmode, mode, "__gcc_qtod"); - set_conv_libfunc (sfix_optab, SImode, mode, "__gcc_qtoi"); - set_conv_libfunc (ufix_optab, SImode, mode, "__gcc_qtou"); - set_conv_libfunc (sfloat_optab, mode, SImode, "__gcc_itoq"); - set_conv_libfunc (ufloat_optab, mode, SImode, "__gcc_utoq"); - } + set_optab_libfunc (neg_optab, mode, "__gcc_qneg"); + set_optab_libfunc (eq_optab, mode, "__gcc_qeq"); + set_optab_libfunc (ne_optab, mode, "__gcc_qne"); + set_optab_libfunc (gt_optab, mode, "__gcc_qgt"); + set_optab_libfunc (ge_optab, mode, "__gcc_qge"); + set_optab_libfunc (lt_optab, mode, "__gcc_qlt"); + set_optab_libfunc (le_optab, mode, "__gcc_qle"); + set_optab_libfunc (unord_optab, mode, "__gcc_qunord"); + + set_conv_libfunc (sext_optab, mode, SFmode, "__gcc_stoq"); + set_conv_libfunc (sext_optab, mode, DFmode, "__gcc_dtoq"); + set_conv_libfunc (trunc_optab, SFmode, mode, "__gcc_qtos"); + set_conv_libfunc (trunc_optab, DFmode, mode, "__gcc_qtod"); + set_conv_libfunc (sfix_optab, SImode, mode, "__gcc_qtoi"); + set_conv_libfunc (ufix_optab, SImode, mode, "__gcc_qtou"); + set_conv_libfunc (sfloat_optab, mode, SImode, "__gcc_itoq"); + set_conv_libfunc (ufloat_optab, mode, SImode, "__gcc_utoq"); } else { diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 813ec696c0d..f58f5f3f355 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -337,7 +337,7 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); #define FLOAT128_IBM_P(MODE) \ ((!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 \ && ((MODE) == TFmode || (MODE) == TCmode)) \ - || (TARGET_HARD_FLOAT && ((MODE) == IFmode || (MODE) == ICmode))) + || ((MODE) == IFmode || (MODE) == ICmode)) /* Helper macros to say whether a 128-bit floating point type can go in a single vector register, or whether it needs paired scalar values. */ From patchwork Thu Aug 18 21:42:50 2022 Content-Type: text/plain; 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Thu, 18 Aug 2022 21:42:53 GMT Received: from b01cxnp23032.gho.pok.ibm.com (b01cxnp23032.gho.pok.ibm.com [9.57.198.27]) by ppma04wdc.us.ibm.com with ESMTP id 3hx3ka18fk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 18 Aug 2022 21:42:53 +0000 Received: from b01ledav001.gho.pok.ibm.com (b01ledav001.gho.pok.ibm.com [9.57.199.106]) by b01cxnp23032.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 27ILgqRh18874778 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 18 Aug 2022 21:42:52 GMT Received: from b01ledav001.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 542242805A; Thu, 18 Aug 2022 21:42:52 +0000 (GMT) Received: from b01ledav001.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0F93728058; Thu, 18 Aug 2022 21:42:52 +0000 (GMT) Received: from toto.the-meissners.org (unknown [9.65.225.181]) by b01ledav001.gho.pok.ibm.com (Postfix) with ESMTPS; Thu, 18 Aug 2022 21:42:51 +0000 (GMT) Date: Thu, 18 Aug 2022 17:42:50 -0400 To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner , Will Schmidt Subject: [PATCH 3/3] Add 'w' suffix for __ibm128 constants Message-ID: Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , "Kewen.Lin" , David Edelsohn , Peter Bergner , Will Schmidt References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-TM-AS-GCONF: 00 X-Proofpoint-GUID: Ab3CIhra0vL_1PZyUwHsPd29AzLWT3-N X-Proofpoint-ORIG-GUID: R6azdIqTnPTq7RYEIYfDLVMy-6ZHtxC9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-18_16,2022-08-18_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 mlxlogscore=999 mlxscore=0 clxscore=1015 priorityscore=1501 lowpriorityscore=0 impostorscore=0 spamscore=0 malwarescore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2208180077 X-Spam-Status: No, score=-10.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_MANYTO, KAM_SHORT, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Michael Meissner via Gcc-patches From: Michael Meissner Reply-To: Michael Meissner Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Add 'w' suffix for __ibm128 constants. In the documentation, we mention that 'w' or 'W' can be used as a suffix for __ibm128 constants. We never implemented this. This patch fixes that. In addition, the 'q' and 'Q' suffix were changed to use the mode used for the __float128 type, instead of knowing whether to use KFmode or TFmode explicitly. This will be used in a future patch where we change the mode used for __float128 on systems where long double is IEEE 128-bit. I have tested this patch on the following systems: 1) LE Power10 using --with-cpu=power10 --with-long-double-format=ieee 2) LE Power10 using --with-cpu=power9 --with-long-double-format=ibm 3) LE Power10 using --with-cpu=power8 --with-long-double-format=ibm 4) LE Power10 using --with-cpu=power10 --with-long-double-format=ibm 5) LE Power9 using --with-cpu=power9 --with-long-double-format=ibm 6) BE Power8 using --with-cpu=power8 --with-long-double-format=ibm 7) BE Power8 using --with-cpu=power5 --with-long-double-format=ibm There were no regressions in the build or in the tests. Can I check this patch into the trunk? Did we want to backport this to earlier GCC releases? 2022-08-17 Michael Meissner gcc/ * config/rs6000/rs6000.cc (rs6000_c_mode_for_suffix): Allow 'w' or 'W' for __ibm128 constants. gcc/testsuite/ * gcc.target/powerpc/ibm128-suffix.c: New test. --- gcc/config/rs6000/rs6000.cc | 25 ++++++++++--------- .../gcc.target/powerpc/ibm128-suffix.c | 13 ++++++++++ 2 files changed, 26 insertions(+), 12 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/ibm128-suffix.c diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index a6ec4c71ac0..046c538c748 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -23845,22 +23845,23 @@ rs6000_floatn_mode (int n, bool extended) } -/* Target hook for c_mode_for_suffix. */ +/* Target hook for c_mode_for_suffix. We use TYPE_MODE to follow the mode used + for __float128 and __ibm128. + + Only two suffixes are allowed, 'q' and 'w'. The 'q' suffix is used for + float128 constants on both the x86 and PowerPC processors. Its use predates + the use of 'f128' for _Float128 constants, and existing code still uses it. + + The 'w' suffix was used on the x86 processors for their 80-bit long + double. We use it for __ibm128 constants. */ static machine_mode rs6000_c_mode_for_suffix (char suffix) { - if (TARGET_FLOAT128_TYPE) - { - if (suffix == 'q' || suffix == 'Q') - return (FLOAT128_IEEE_P (TFmode)) ? TFmode : KFmode; + if (TARGET_FLOAT128_TYPE && (suffix == 'q' || suffix == 'Q')) + return TYPE_MODE (ieee128_float_type_node); - /* At the moment, we are not defining a suffix for IBM extended double. - If/when the default for -mabi=ieeelongdouble is changed, and we want - to support __ibm128 constants in legacy library code, we may need to - re-evalaute this decision. Currently, c-lex.cc only supports 'w' and - 'q' as machine dependent suffixes. The x86_64 port uses 'w' for - __float80 constants. */ - } + if (TARGET_IBM128 && (suffix == 'w' || suffix == 'W')) + return TYPE_MODE (ibm128_float_type_node); return VOIDmode; } diff --git a/gcc/testsuite/gcc.target/powerpc/ibm128-suffix.c b/gcc/testsuite/gcc.target/powerpc/ibm128-suffix.c new file mode 100644 index 00000000000..ff619860409 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/ibm128-suffix.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target longdouble128 } */ +/* { dg-options "-O2" } */ + +/* See if the 'w' suffix is accepted for __ibm128. */ +#ifndef NUMBER +#define NUMBER 123456789012345678901234567890123456789E-10 +#endif + +#define GLUE2(X,Y) X ## Y +#define GLUE(X,Y) GLUE2(X,Y) + +__ibm128 x = GLUE (NUMBER, w);