From patchwork Tue Aug 16 08:08:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xi Ruoyao X-Patchwork-Id: 56769 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id F1A8B3858437 for ; Tue, 16 Aug 2022 08:08:42 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org F1A8B3858437 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1660637323; bh=5o5zD5VAgDfPs9LPz17+HSzjAFDgcB1CBEUbKamRcf8=; h=Subject:To:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=dW7SH/qmDOwzk96pwEJgZpRpC1bSmbgtxXThYXd0W5AX6CL+f10MbLDcD/N3galZb ryYLJRQSa0DOEDM5CykpMomEBUeUI0rmbTOVqNAwu0zOv59K9IpuDnchViHMflazm8 l9BoEzphbjbzxxAiZg/f6efwbbZHGTytuZRLEbwE= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from xry111.site (xry111.site [89.208.246.23]) by sourceware.org (Postfix) with ESMTPS id 559643858C20 for ; Tue, 16 Aug 2022 08:08:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 559643858C20 Received: from localhost.localdomain (xry111.site [IPv6:2001:470:683e::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature ECDSA (P-384) server-digest SHA384) (Client did not present a certificate) (Authenticated sender: xry111@xry111.site) by xry111.site (Postfix) with ESMTPSA id 7B9716680F; Tue, 16 Aug 2022 04:08:11 -0400 (EDT) Message-ID: <829912f321dc5cf93e5edf55529586b9660fce17.camel@xry111.site> Subject: [PATCH] LoongArch: Provide fmin/fmax RTL pattern To: gcc-patches@gcc.gnu.org Date: Tue, 16 Aug 2022 16:08:08 +0800 User-Agent: Evolution 3.45.2 MIME-Version: 1.0 X-Spam-Status: No, score=-5.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FROM_SUSPICIOUS_NTLD, FROM_SUSPICIOUS_NTLD_FP, GIT_PATCH_0, KAM_SHORT, LIKELY_SPAM_FROM, PDS_OTHER_BAD_TLD, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Xi Ruoyao via Gcc-patches From: Xi Ruoyao Reply-To: Xi Ruoyao Cc: Chenghua Xu , Lulu Cheng , Wang Xuerui Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" A simple optimization. Ok for trunk? -- >8 -- We already had smin/smax RTL pattern using fmin/fmax instruction. But for smin/smax, it's unspecified what will happen if either operand is NaN. So we would generate calls to libc fmin/fmax functions with -fno-finite-math-only (the default for all optimization levels expect -Ofast). But, LoongArch fmin/fmax instruction is IEEE-754-2008 conformant so we can also use the instruction for fmin/fmax pattern and avoid the library function call. gcc/ChangeLog: * config/loongarch/loongarch.md (fmax3): New RTL pattern. (fmin3): Likewise. gcc/testsuite/ChangeLog: * gcc.target/loongarch/fmax-fmin.c: New test. --- gcc/config/loongarch/loongarch.md | 18 +++++++++++ .../gcc.target/loongarch/fmax-fmin.c | 30 +++++++++++++++++++ 2 files changed, 48 insertions(+) create mode 100644 gcc/testsuite/gcc.target/loongarch/fmax-fmin.c diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index 6b6df22a5f1..8e8868de9f5 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -1023,6 +1023,24 @@ (define_insn "smin3" [(set_attr "type" "fmove") (set_attr "mode" "")]) +(define_insn "fmax3" + [(set (match_operand:ANYF 0 "register_operand" "=f") + (smax:ANYF (match_operand:ANYF 1 "register_operand" "f") + (match_operand:ANYF 2 "register_operand" "f")))] + "" + "fmax.\t%0,%1,%2" + [(set_attr "type" "fmove") + (set_attr "mode" "")]) + +(define_insn "fmin3" + [(set (match_operand:ANYF 0 "register_operand" "=f") + (smin:ANYF (match_operand:ANYF 1 "register_operand" "f") + (match_operand:ANYF 2 "register_operand" "f")))] + "" + "fmin.\t%0,%1,%2" + [(set_attr "type" "fmove") + (set_attr "mode" "")]) + (define_insn "smaxa3" [(set (match_operand:ANYF 0 "register_operand" "=f") (if_then_else:ANYF diff --git a/gcc/testsuite/gcc.target/loongarch/fmax-fmin.c b/gcc/testsuite/gcc.target/loongarch/fmax-fmin.c new file mode 100644 index 00000000000..92cf8a1501d --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/fmax-fmin.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-mdouble-float -fno-finite-math-only" } */ +/* { dg-final { scan-assembler "fmin\\.s" } } */ +/* { dg-final { scan-assembler "fmin\\.d" } } */ +/* { dg-final { scan-assembler "fmax\\.s" } } */ +/* { dg-final { scan-assembler "fmax\\.d" } } */ + +double +_fmax(double a, double b) +{ + return __builtin_fmax(a, b); +} + +float +_fmaxf(float a, float b) +{ + return __builtin_fmaxf(a, b); +} + +double +_fmin(double a, double b) +{ + return __builtin_fmin(a, b); +} + +float +_fminf(float a, float b) +{ + return __builtin_fminf(a, b); +}