From patchwork Thu Jul 28 19:51:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Maciej W. Rozycki" X-Patchwork-Id: 56401 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 564E53856DF7 for ; Thu, 28 Jul 2022 19:52:00 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by sourceware.org (Postfix) with ESMTPS id 975BA3857C6D for ; Thu, 28 Jul 2022 19:51:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 975BA3857C6D Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embecosm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=embecosm.com Received: by mail-lj1-x235.google.com with SMTP id z13so3026194ljj.6 for ; Thu, 28 Jul 2022 12:51:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; h=date:from:to:cc:subject:message-id:user-agent:mime-version; bh=mQHaRGfX00rAK050zjexPZtxsYG3/KyP5U1581QcusA=; b=dh4i2+KNMSDwTZq1DOhcq1sR+4Jv9sdEyD9SOemg+OQHtopN4nww8dHdFIFkE8UshT Yx4idOA2a2HxFQpZfmYpI36FkuJ9l6elmBuenGAT4AkPk49k77QMZQR9ZIDH4Mghmg+u 7X9awLiX/AQcF/iYMQ0Ub32eaHaMbzi2BRZM1kQYG0yq0UKDM+y6H+/MGW533UIVjNdI f3B2lgermyMLUQ68+1kTj4CyKiwXkhKCWO5Y7crqroUlXrd0Widsf7xFx6gudWQ8HGlK S9OronmftwAhBvRGnLLu0puC0ssGSLiZl8ORuRoCcQwJywQ4nu7TFiZIiRv0/oJDUai2 kKBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:user-agent :mime-version; bh=mQHaRGfX00rAK050zjexPZtxsYG3/KyP5U1581QcusA=; b=IPQ8Kl8xTGTz+z2Eda72kCDd88QsS5oz97Dh60FCTpgeA7rVTGDtmowvnkwdxKmMcV DoSHfIz8WMZudL+zCcLBiegFmRMgp+2MhF0AvfCLYPgqXFebyZwFa1tZuih6lBtgsvb8 4+qahv79522iFkArYvVFDJsqIQuqvo+1qQvhECQaM0+Ygs/BgaxnGndrZuTtwNU5zODa 2U7leg98IWhGHRFTGPcl+RlaraLCMO96HMrC6r0iNxfFNoJs5dzMqHQpCrqwZok9xVnI PRsVdYosZCsUirgPujNPk8pBMJIgS/Gspc4mA33pCgmmQ3/SNlSurc7e7+nyuIbtb4tx ax/w== X-Gm-Message-State: AJIora8qtToDloc1hYVmH9PkuZQBPnX0lWwBkFLF6hnyKYhRPifvddUj 5eSbi18qG1DJtoDGKtg/7OT9n4xJBBacQORn X-Google-Smtp-Source: AGRyM1uNLALVAv5PhLz10l+yTFJDRXp8nr2QjPn3VsFR7zL/9T/W2iUXde5rs9TGqkRjh5TY/tH+/A== X-Received: by 2002:a05:651c:1542:b0:249:a87f:8a34 with SMTP id y2-20020a05651c154200b00249a87f8a34mr124166ljp.442.1659037878017; Thu, 28 Jul 2022 12:51:18 -0700 (PDT) Received: from [192.168.219.3] ([78.8.192.131]) by smtp.gmail.com with ESMTPSA id r22-20020ac25f96000000b0048a74608f16sm330422lfe.308.2022.07.28.12.51.16 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Jul 2022 12:51:17 -0700 (PDT) Date: Thu, 28 Jul 2022 20:51:12 +0100 (BST) From: "Maciej W. Rozycki" To: gcc-patches@gcc.gnu.org Subject: [PATCH] RISC-V/testsuite: Restrict remaining `fmin'/`fmax' tests to hard float Message-ID: User-Agent: Alpine 2.20 (DEB 67 2015-01-07) MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, KAM_ASCII_DIVIDERS, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Waterman , Kito Cheng Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Complement commit 7915f6551343 ("RISC-V/testsuite: constraint some of tests to hard_float") and also restrict the remaining `fmin'/`fmax' tests to hard-float test configurations. gcc/testsuite/ * gcc.target/riscv/fmax-snan.c: Add `dg-require-effective-target hard_float'. * gcc.target/riscv/fmaxf-snan.c: Likewise. * gcc.target/riscv/fmin-snan.c: Likewise. * gcc.target/riscv/fminf-snan.c: Likewise. --- gcc/testsuite/gcc.target/riscv/fmax-snan.c | 1 + gcc/testsuite/gcc.target/riscv/fmaxf-snan.c | 1 + gcc/testsuite/gcc.target/riscv/fmin-snan.c | 1 + gcc/testsuite/gcc.target/riscv/fminf-snan.c | 1 + 4 files changed, 4 insertions(+) gcc-riscv-fmin-fmax-test-hard-float.diff Index: gcc/gcc/testsuite/gcc.target/riscv/fmax-snan.c =================================================================== --- gcc.orig/gcc/testsuite/gcc.target/riscv/fmax-snan.c +++ gcc/gcc/testsuite/gcc.target/riscv/fmax-snan.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-require-effective-target hard_float } */ /* { dg-options "-fno-finite-math-only -fsigned-zeros -fsignaling-nans -dp" } */ double Index: gcc/gcc/testsuite/gcc.target/riscv/fmaxf-snan.c =================================================================== --- gcc.orig/gcc/testsuite/gcc.target/riscv/fmaxf-snan.c +++ gcc/gcc/testsuite/gcc.target/riscv/fmaxf-snan.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-require-effective-target hard_float } */ /* { dg-options "-fno-finite-math-only -fsigned-zeros -fsignaling-nans -dp" } */ float Index: gcc/gcc/testsuite/gcc.target/riscv/fmin-snan.c =================================================================== --- gcc.orig/gcc/testsuite/gcc.target/riscv/fmin-snan.c +++ gcc/gcc/testsuite/gcc.target/riscv/fmin-snan.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-require-effective-target hard_float } */ /* { dg-options "-fno-finite-math-only -fsigned-zeros -fsignaling-nans -dp" } */ double Index: gcc/gcc/testsuite/gcc.target/riscv/fminf-snan.c =================================================================== --- gcc.orig/gcc/testsuite/gcc.target/riscv/fminf-snan.c +++ gcc/gcc/testsuite/gcc.target/riscv/fminf-snan.c @@ -1,4 +1,5 @@ /* { dg-do compile } */ +/* { dg-require-effective-target hard_float } */ /* { dg-options "-fno-finite-math-only -fsigned-zeros -fsignaling-nans -dp" } */ float