From patchwork Wed Jul 13 02:13:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liao Shihua X-Patchwork-Id: 55995 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 036843851C1F for ; Wed, 13 Jul 2022 02:14:05 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) by sourceware.org (Postfix) with ESMTP id B11433858418 for ; Wed, 13 Jul 2022 02:13:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org B11433858418 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [180.102.239.252]) by APP-01 (Coremail) with SMTP id qwCowACnPVpPKs5i4I8mDw--.4882S3; Wed, 13 Jul 2022 10:13:38 +0800 (CST) From: shihua@iscas.ac.cn To: gcc-patches@gcc.gnu.org Subject: [PATCH 1/1 V5] RISC-V: Support Zmmul extension Date: Wed, 13 Jul 2022 10:13:26 +0800 Message-Id: <20220713021326.1235-2-shihua@iscas.ac.cn> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20220713021326.1235-1-shihua@iscas.ac.cn> References: <20220713021326.1235-1-shihua@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: qwCowACnPVpPKs5i4I8mDw--.4882S3 X-Coremail-Antispam: 1UD129KBjvJXoW3ArW3Ar47Ar1fAw4UZw1xAFb_yoWDGF18pF 4DGw4FyryrXFZagws3KFyUXw1Ykrn2gr4Y9r9xurWDA348JrWkJ3Wvk342ya4UXF45Zry7 uF4Ikw13C3yYkw7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmj14x267AKxVW5JVWrJwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r1I6r4UM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gr1j6F4U JwAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUAVWUtwAv7VC2z280aVAFwI0_Cr0_Gr1UMcvjeVCFs4IE7xkEbVWUJVW8 JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2Y2 ka0xkIwI1lw4CEc2x0rVAKj4xxMxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j 6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7 AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE 2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcV C2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2Kfnx nUUI43ZEXa7VUbQzVUUUUUU== X-Originating-IP: [180.102.239.252] X-CM-SenderInfo: xvklx33d6l2u1dvotugofq/1tbiAwoGEWKY1kYVQQAAsg X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cmuellner@ventanamicro.com, shiyulong@iscas.ac.cn, kito.cheng@gmail.com, jiawei@iscas.ac.cn, anku.anand@gmail.com, LiaoShihua Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: LiaoShihua gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add Zmmul. * config/riscv/riscv-opts.h (MASK_ZMMUL): New. (TARGET_ZMMUL): Ditto. * config/riscv/riscv.cc (riscv_option_override):Ditto. * config/riscv/riscv.md: Add Zmmul * config/riscv/riscv.opt: Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/zmmul-1.c: New test. * gcc.target/riscv/zmmul-2.c: New test. --- gcc/common/config/riscv/riscv-common.cc | 3 +++ gcc/config/riscv/riscv-opts.h | 3 +++ gcc/config/riscv/riscv.cc | 8 +++++-- gcc/config/riscv/riscv.md | 28 ++++++++++++------------ gcc/config/riscv/riscv.opt | 3 +++ gcc/testsuite/gcc.target/riscv/zmmul-1.c | 20 +++++++++++++++++ gcc/testsuite/gcc.target/riscv/zmmul-2.c | 20 +++++++++++++++++ 7 files changed, 69 insertions(+), 16 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/zmmul-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/zmmul-2.c diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 0e5be2ce105..20acc590b30 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -193,6 +193,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zvl32768b", ISA_SPEC_CLASS_NONE, 1, 0}, {"zvl65536b", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zmmul", ISA_SPEC_CLASS_NONE, 1, 0}, + /* Terminate the list. */ {NULL, ISA_SPEC_CLASS_NONE, 0, 0} }; @@ -1148,6 +1150,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zvl32768b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL32768B}, {"zvl65536b", &gcc_options::x_riscv_zvl_flags, MASK_ZVL65536B}, + {"zmmul", &gcc_options::x_riscv_zm_subext, MASK_ZMMUL}, {NULL, NULL, 0} }; diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 1e153b3a6e7..9c7d69a6ea3 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -153,6 +153,9 @@ enum stack_protector_guard { #define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0) #define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0) +#define MASK_ZMMUL (1 << 0) +#define TARGET_ZMMUL ((riscv_zm_subext & MASK_ZMMUL) != 0) + /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is set, e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use popcount to caclulate the minimal VLEN. */ diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 2e83ca07394..9ad4181f35f 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4999,10 +4999,14 @@ riscv_option_override (void) /* The presence of the M extension implies that division instructions are present, so include them unless explicitly disabled. */ if (TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0) - target_flags |= MASK_DIV; + if(!TARGET_ZMMUL) + target_flags |= MASK_DIV; else if (!TARGET_MUL && TARGET_DIV) error ("%<-mdiv%> requires %<-march%> to subsume the % extension"); - + + if(TARGET_ZMMUL && !TARGET_MUL && TARGET_DIV) + warning (0, "%<-mdiv%> cannot be used when % extension is present"); + /* Likewise floating-point division and square root. */ if (TARGET_HARD_FLOAT && (target_flags_explicit & MASK_FDIV) == 0) target_flags |= MASK_FDIV; diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 308b64dd30d..d4e171464ea 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -763,7 +763,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (mult:SI (match_operand:SI 1 "register_operand" " r") (match_operand:SI 2 "register_operand" " r")))] - "TARGET_MUL" + "TARGET_ZMMUL || TARGET_MUL" { return TARGET_64BIT ? "mulw\t%0,%1,%2" : "mul\t%0,%1,%2"; } [(set_attr "type" "imul") (set_attr "mode" "SI")]) @@ -772,7 +772,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (match_operand:DI 1 "register_operand" " r") (match_operand:DI 2 "register_operand" " r")))] - "TARGET_MUL && TARGET_64BIT" + "TARGET_ZMMUL || TARGET_MUL && TARGET_64BIT" "mul\t%0,%1,%2" [(set_attr "type" "imul") (set_attr "mode" "DI")]) @@ -782,7 +782,7 @@ (mult:GPR (match_operand:GPR 1 "register_operand" " r") (match_operand:GPR 2 "register_operand" " r"))) (label_ref (match_operand 3 "" ""))] - "TARGET_MUL" + "TARGET_ZMMUL || TARGET_MUL" { if (TARGET_64BIT && mode == SImode) { @@ -827,7 +827,7 @@ (mult:GPR (match_operand:GPR 1 "register_operand" " r") (match_operand:GPR 2 "register_operand" " r"))) (label_ref (match_operand 3 "" ""))] - "TARGET_MUL" + "TARGET_ZMMUL || TARGET_MUL" { if (TARGET_64BIT && mode == SImode) { @@ -873,7 +873,7 @@ (sign_extend:DI (mult:SI (match_operand:SI 1 "register_operand" " r") (match_operand:SI 2 "register_operand" " r"))))] - "TARGET_MUL && TARGET_64BIT" + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT" "mulw\t%0,%1,%2" [(set_attr "type" "imul") (set_attr "mode" "SI")]) @@ -884,7 +884,7 @@ (match_operator:SI 3 "subreg_lowpart_operator" [(mult:DI (match_operand:DI 1 "register_operand" " r") (match_operand:DI 2 "register_operand" " r"))])))] - "TARGET_MUL && TARGET_64BIT" + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT" "mulw\t%0,%1,%2" [(set_attr "type" "imul") (set_attr "mode" "SI")]) @@ -902,7 +902,7 @@ [(set (match_operand:TI 0 "register_operand") (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand")) (any_extend:TI (match_operand:DI 2 "register_operand"))))] - "TARGET_MUL && TARGET_64BIT" + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT" { rtx low = gen_reg_rtx (DImode); emit_insn (gen_muldi3 (low, operands[1], operands[2])); @@ -924,7 +924,7 @@ (any_extend:TI (match_operand:DI 2 "register_operand" " r"))) (const_int 64))))] - "TARGET_MUL && TARGET_64BIT" + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT" "mulh\t%0,%1,%2" [(set_attr "type" "imul") (set_attr "mode" "DI")]) @@ -933,7 +933,7 @@ [(set (match_operand:TI 0 "register_operand") (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand")) (sign_extend:TI (match_operand:DI 2 "register_operand"))))] - "TARGET_MUL && TARGET_64BIT" + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT" { rtx low = gen_reg_rtx (DImode); emit_insn (gen_muldi3 (low, operands[1], operands[2])); @@ -955,7 +955,7 @@ (sign_extend:TI (match_operand:DI 2 "register_operand" " r"))) (const_int 64))))] - "TARGET_MUL && TARGET_64BIT" + "(TARGET_ZMMUL || TARGET_MUL) && TARGET_64BIT" "mulhsu\t%0,%2,%1" [(set_attr "type" "imul") (set_attr "mode" "DI")]) @@ -966,7 +966,7 @@ (match_operand:SI 1 "register_operand" " r")) (any_extend:DI (match_operand:SI 2 "register_operand" " r"))))] - "TARGET_MUL && !TARGET_64BIT" + "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT" { rtx temp = gen_reg_rtx (SImode); emit_insn (gen_mulsi3 (temp, operands[1], operands[2])); @@ -985,7 +985,7 @@ (any_extend:DI (match_operand:SI 2 "register_operand" " r"))) (const_int 32))))] - "TARGET_MUL && !TARGET_64BIT" + "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT" "mulh\t%0,%1,%2" [(set_attr "type" "imul") (set_attr "mode" "SI")]) @@ -997,7 +997,7 @@ (match_operand:SI 1 "register_operand" " r")) (sign_extend:DI (match_operand:SI 2 "register_operand" " r"))))] - "TARGET_MUL && !TARGET_64BIT" + "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT" { rtx temp = gen_reg_rtx (SImode); emit_insn (gen_mulsi3 (temp, operands[1], operands[2])); @@ -1016,7 +1016,7 @@ (sign_extend:DI (match_operand:SI 2 "register_operand" " r"))) (const_int 32))))] - "TARGET_MUL && !TARGET_64BIT" + "(TARGET_ZMMUL || TARGET_MUL) && !TARGET_64BIT" "mulhsu\t%0,%2,%1" [(set_attr "type" "imul") (set_attr "mode" "SI")]) diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 9e9fe6d8ccd..f93521c1e70 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -212,6 +212,9 @@ int riscv_zvl_flags TargetVariable int riscv_zicmo_subext +TargetVariable +int riscv_zm_subext + Enum Name(isa_spec_class) Type(enum riscv_isa_spec_class) Supported ISA specs (for use with the -misa-spec= option): diff --git a/gcc/testsuite/gcc.target/riscv/zmmul-1.c b/gcc/testsuite/gcc.target/riscv/zmmul-1.c new file mode 100644 index 00000000000..cdae2cb55df --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zmmul-1.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64iafdc_zmmul -mabi=lp64" } */ +int foo1(int a, int b) +{ + return a*b; +} + +int foo2(int a, int b) +{ + return a/b; +} + +int foo3(int a, int b) +{ + return a%b; +} + +/* { dg-final { scan-assembler-times "mulw\t" 1 } } */ +/* { dg-final { scan-assembler-not "div\t" } } */ +/* { dg-final { scan-assembler-not "rem\t" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/zmmul-2.c b/gcc/testsuite/gcc.target/riscv/zmmul-2.c new file mode 100644 index 00000000000..dc6829da92e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zmmul-2.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32iafdc_zmmul -mabi=ilp32" } */ +int foo1(int a, int b) +{ + return a*b; +} + +int foo2(int a, int b) +{ + return a/b; +} + +int foo3(int a, int b) +{ + return a%b; +} + +/* { dg-final { scan-assembler-times "mul\t" 1 } } */ +/* { dg-final { scan-assembler-not "div\t" } } */ +/* { dg-final { scan-assembler-not "rem\t" } } */ \ No newline at end of file