From patchwork Mon Jul 4 19:11:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Sayle X-Patchwork-Id: 55708 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id DE86C3853543 for ; Mon, 4 Jul 2022 19:12:03 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id 36864385AE43 for ; Mon, 4 Jul 2022 19:11:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 36864385AE43 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:Cc:To:From:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=me4sMzEsnwkeTRfruuUCcmYgo1H/lZj0Cw8CVoQ8quI=; b=HSkl0V6kPBXOBJVlkV7fwWt4d1 /WvkCQSu+aUdBiZ4p7nk2aLAuLBGKi+BTtIAOTfOCxhp4LK7BSSbG2RuLRBd9eMxw4hi8uAXn+O8k kt1IjSTSx/xq/5Co3POo2w8MYr91R8fgiHiYR+LrdrrxM8JgFkiHq1nS7/TWTCRl0FU8TN/VztI3D BrZKXMUkGgeZsIB0e8HVNNCePJ/nac81qshgRkgq3hntrU/ETRcfqZThjkRzH6LAf86Qe38S/lbnM 2x9kt70NC16KbxAzH+XDtBVsLob/89gfxdpsJLI/Z0DZFjrInolXFmvYGnTFZBaWxu/dJABjlNZNt UiTD9IDg==; Received: from [185.62.158.67] (port=64287 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1o8RU3-0001Ek-JG; Mon, 04 Jul 2022 15:11:47 -0400 From: "Roger Sayle" To: "'GCC Patches'" Subject: [x86 PATCH take #2] Doubleword version of and; cmp to not; test optimization. Date: Mon, 4 Jul 2022 20:11:46 +0100 Message-ID: <00b501d88fd9$e89e6700$b9db3500$@nextmovesoftware.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AdiP18Mk/U4W5G8BRe2ddNXmwUmjaw== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This patch is the latest revision of the patch originally posted at: https://gcc.gnu.org/pipermail/gcc-patches/2022-June/596201.html This patch extends the earlier and;cmp to not;test optimization to also perform this transformation for TImode on TARGET_64BIT and DImode on -m32, One motivation for this is that it's a step to fixing the current failure of gcc.target/i386/pr65105-5.c on -m32. A more direct benefit for x86_64 is that the following code: int foo(__int128 x, __int128 y) { return (x & y) == y; } improves with -O2 from 15 instructions: movq %rdi, %r8 movq %rsi, %rax movq %rax, %rdi movq %r8, %rsi movq %rdx, %r8 andq %rdx, %rsi andq %rcx, %rdi movq %rsi, %rax movq %rdi, %rdx xorq %r8, %rax xorq %rcx, %rdx orq %rdx, %rax sete %al movzbl %al, %eax ret to the slightly better 13 instructions: movq %rdi, %r8 movq %rsi, %rax movq %r8, %rsi movq %rax, %rdi notq %rsi notq %rdi andq %rdx, %rsi andq %rcx, %rdi movq %rsi, %rax orq %rdi, %rax sete %al movzbl %al, %eax ret Now that all of the doubleword pieces are already in the tree, this patch is now much shorter (an rtx_costs improvement and a single new define_insn_and_split), however I couldn't resist including two very minor pattern naming tweaks/clean-ups to fix nits. This revised patch has been tested on x86_64-pc-linux-gnu with make bootstrap and make -k check, where on TARGET_64BIT there are no new failures, and on --target_board=unix{-m32} with a single new failure; the other dg-final in gcc.target/i386/pr65105-5.c now also fails (as that code diverges further from the expected vectorized output). This is progress as both FAILs in pr65105-5.c may now be fixed by changes localized to the STV pass. OK for mainline? 2022-07-04 Roger Sayle gcc/ChangeLog * config/i386/i386.cc (ix86_rtx_costs) : Provide costs for double word comparisons and tests (comparisons against zero). * config/i386/i386.md (*test_not_doubleword): Split DWI and;cmp into andn;cmp $0 as a pre-reload splitter. (*andn3_doubleword_bmi): Use instead of in name. (*3_doubleword): Likewise. gcc/testsuite/ChangeLog * gcc.target/i386/testnot-3.c: New test case. Thanks in advance, Roger diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index b15b489..70c9a27 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -20935,6 +20935,19 @@ ix86_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno, return true; } + if (SCALAR_INT_MODE_P (GET_MODE (op0)) + && GET_MODE_SIZE (GET_MODE (op0)) > UNITS_PER_WORD) + { + if (op1 == const0_rtx) + *total = cost->add + + rtx_cost (op0, GET_MODE (op0), outer_code, opno, speed); + else + *total = 3*cost->add + + rtx_cost (op0, GET_MODE (op0), outer_code, opno, speed) + + rtx_cost (op1, GET_MODE (op0), outer_code, opno, speed); + return true; + } + /* The embedded comparison operand is completely free. */ if (!general_operand (op0, GET_MODE (op0)) && op1 == const0_rtx) *total = 0; diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 20c3b9a..2492ad4 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -9792,7 +9792,25 @@ (set (reg:CCZ FLAGS_REG) (compare:CCZ (and:SWI (match_dup 2) (match_dup 1)) (const_int 0)))] + "operands[2] = gen_reg_rtx (mode);") + +;; Split and;cmp (as optimized by combine) into andn;cmp $0 +(define_insn_and_split "*test_not_doubleword" + [(set (reg:CCZ FLAGS_REG) + (compare:CCZ + (and:DWI + (not:DWI (match_operand:DWI 0 "nonimmediate_operand")) + (match_operand:DWI 1 "nonimmediate_operand")) + (const_int 0)))] + "ix86_pre_reload_split ()" + "#" + "&& 1" + [(parallel + [(set (match_dup 2) (and:DWI (not:DWI (match_dup 0)) (match_dup 1))) + (clobber (reg:CC FLAGS_REG))]) + (set (reg:CCZ FLAGS_REG) (compare:CCZ (match_dup 2) (const_int 0)))] { + operands[0] = force_reg (mode, operands[0]); operands[2] = gen_reg_rtx (mode); }) @@ -10404,7 +10422,7 @@ operands[2] = gen_int_mode (INTVAL (operands[2]), QImode); }) -(define_insn_and_split "*andn3_doubleword_bmi" +(define_insn_and_split "*andn3_doubleword_bmi" [(set (match_operand: 0 "register_operand" "=r") (and: (not: (match_operand: 1 "register_operand" "r")) @@ -10542,7 +10560,7 @@ DONE; }) -(define_insn_and_split "*3_doubleword" +(define_insn_and_split "*3_doubleword" [(set (match_operand: 0 "nonimmediate_operand" "=ro,r") (any_or: (match_operand: 1 "nonimmediate_operand" "%0,0") diff --git a/gcc/testsuite/gcc.target/i386/testnot-3.c b/gcc/testsuite/gcc.target/i386/testnot-3.c new file mode 100644 index 0000000..7c54dbc --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/testnot-3.c @@ -0,0 +1,9 @@ +/* { dg-do compile { target int128 } } */ +/* { dg-options "-O2" } */ + +int foo(__int128 x, __int128 y) +{ + return (x & y) == y; +} + +/* { dg-final { scan-assembler-not "xorq" } } */