From patchwork Thu Jun 30 05:59:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jiang, Haochen" X-Patchwork-Id: 55589 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id EA91E386CE5D for ; Thu, 30 Jun 2022 05:59:39 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org EA91E386CE5D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1656568780; bh=M+iqdYxY4Xy3aWsoeq9WuBXt5XUwitL74C5cTpiFdUA=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=sfbFWeN9MZTz7unvIZxilxxygCMFFfGls4EqembaLaO8infuhgCzGqtp2cw3r+8dQ jXhcdpijQDaHL434dczfpnetfakrCVykitTFgkuRleJnejGnm60lRssxxqG6POKi2c g4NZZcwjuZ6TZBlizSr8VX7ddINatX2e+BGn53h8= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by sourceware.org (Postfix) with ESMTPS id B294F384D1BC for ; Thu, 30 Jun 2022 05:59:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org B294F384D1BC X-IronPort-AV: E=McAfee;i="6400,9594,10393"; a="282988168" X-IronPort-AV: E=Sophos;i="5.92,233,1650956400"; d="scan'208";a="282988168" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Jun 2022 22:59:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.92,233,1650956400"; d="scan'208";a="591024904" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga002.jf.intel.com with ESMTP; 29 Jun 2022 22:59:08 -0700 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 599E810056AE; Thu, 30 Jun 2022 13:59:07 +0800 (CST) To: gcc-patches@gcc.gnu.org Subject: [PATCH] i386: Extend cvtps2pd to memory Date: Thu, 30 Jun 2022 13:59:07 +0800 Message-Id: <20220630055907.50030-1-haochen.jiang@intel.com> X-Mailer: git-send-email 2.18.1 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Haochen Jiang via Gcc-patches From: "Jiang, Haochen" Reply-To: Haochen Jiang Cc: hongtao.liu@intel.com Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Hi all, This patch aims to fix the cvtps2pd insn, which should also work on memory operand but currently does not. After this fix, when loop == 2, it will eliminate movq instruction. Regtested on x86_64-pc-linux-gnu. Ok for trunk? BRs, Haochen gcc/ChangeLog: PR target/43618 * config/i386/sse.md (extendv2sfv2df2): New define_expand. (sse2_cvtps2pd_load): Rename extendvsdfv2df2. gcc/testsuite/ChangeLog: PR target/43618 * gcc.target/i386/pr43618-1.c: New test. --- gcc/config/i386/sse.md | 24 ++++++++++++++++++----- gcc/testsuite/gcc.target/i386/pr43618-1.c | 13 ++++++++++++ 2 files changed, 32 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr43618-1.c diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 8b2602bfa79..f96bb3dc6c3 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -9175,11 +9175,25 @@ (set_attr "prefix" "evex") (set_attr "mode" "")]) +(define_expand "extendv2sfv2df2" + [(set (match_operand:V2DF 0 "register_operand") + (float_extend:V2DF + (match_operand:V2SF 1 "nonimmediate_operand")))] + "TARGET_MMX_WITH_SSE" +{ + if (!MEM_P (operands[1])) + { + operands[1] = lowpart_subreg (V4SFmode, operands[1], V2SFmode); + emit_insn (gen_sse2_cvtps2pd (operands[0], operands[1])); + DONE; + } +}) + (define_insn "sse2_cvtps2pd" [(set (match_operand:V2DF 0 "register_operand" "=v") (float_extend:V2DF (vec_select:V2SF - (match_operand:V4SF 1 "vector_operand" "vm") + (match_operand:V4SF 1 "register_operand" "v") (parallel [(const_int 0) (const_int 1)]))))] "TARGET_SSE2 && " "%vcvtps2pd\t{%1, %0|%0, %q1}" @@ -9191,12 +9205,12 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "V2DF")]) -(define_insn "extendv2sfv2df2" +(define_insn "sse2_cvtps2pd_load" [(set (match_operand:V2DF 0 "register_operand" "=v") (float_extend:V2DF - (match_operand:V2SF 1 "register_operand" "v")))] - "TARGET_MMX_WITH_SSE" - "%vcvtps2pd\t{%1, %0|%0, %1}" + (match_operand:V2SF 1 "memory_operand" "m")))] + "TARGET_MMX_WITH_SSE && " + "%vcvtps2pd\t{%1, %0|%0, %q1}" [(set_attr "type" "ssecvt") (set_attr "amdfam10_decode" "direct") (set_attr "athlon_decode" "double") diff --git a/gcc/testsuite/gcc.target/i386/pr43618-1.c b/gcc/testsuite/gcc.target/i386/pr43618-1.c new file mode 100644 index 00000000000..3c84ea444aa --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr43618-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-not "movq" } } */ +/* { dg-final { scan-assembler "cvtps2pd" } } */ + +void +foo (float a[2], double b[2]) +{ + int i; + for (i = 0; i < 2; i++) + b[i] = a[i]; +} +