From patchwork Wed Jun 29 23:07:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Noah Goldstein X-Patchwork-Id: 55568 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 65D813842AE1 for ; Wed, 29 Jun 2022 23:07:35 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 65D813842AE1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1656544055; bh=C+O91XW29QKXvSwzfUdifJOrBdk5vtW1lznun5/Pcao=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=NK1L4S4neye7w45iqpd4UZ6iCqQQkvMHREbcRjFig0wOu4rJzfZabhQjIsatClcd9 ZaE7KJabmRBmZaSxOcy4s4xEUw8tI5hPYGS201/QzmDSWHB9QO7HPA9eUiBeA2U0wM kO8dpcYvH8/rvad2pDsT8m9NZrtSDwokuyF4Uwq8= X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-pj1-x1033.google.com (mail-pj1-x1033.google.com [IPv6:2607:f8b0:4864:20::1033]) by sourceware.org (Postfix) with ESMTPS id 08D7D38485A1 for ; Wed, 29 Jun 2022 23:07:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 08D7D38485A1 Received: by mail-pj1-x1033.google.com with SMTP id b12-20020a17090a6acc00b001ec2b181c98so947848pjm.4 for ; Wed, 29 Jun 2022 16:07:13 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=C+O91XW29QKXvSwzfUdifJOrBdk5vtW1lznun5/Pcao=; b=4v4XxDmWal15UHtzi8UvZ/YYTfJ37QVhyzwprdN2SjuHoCzDXatZhYh9E/QyW5ybC/ xjl9Ef96siPI7sBBw01s1Nq/lm31nhbgtLH/GhErSQ9wuTSSG9j6DebXnd+5lXksBUuj XJadcD6DrPtRNG9jsKItf+McY3kkV4dnbroDypCdwGySrwj30aCRtpq7K8mPS81n6qY+ m3GVtCLHy+mCmFOZ2svqYpbVLjAgUc1fLgyPP+ajG5mjoHf+qlNMrOcInjpImM5P3WGa cRIAABo93I8UUSqCsZ6qp/1KxbyQa38KvFaFkjct/wVn2zwv9eKDfckeY2fueWKBQZnc fs4w== X-Gm-Message-State: AJIora9qKmlH8TDsciWN7LFTdaTSS+fe5Q31MrFvbEl+KjofyTzZX6nh phxvNyKWh5BXU5h3TQDjPFH5r58dI84= X-Google-Smtp-Source: AGRyM1tLJ/zett4py5eKWfni3ImmWuwz5vxULTJSsWJ6dNuBpQQ0ROMVfjKTDGmDbJ1dQmkgtcjtLg== X-Received: by 2002:a17:902:74c7:b0:16a:1be3:b7f2 with SMTP id f7-20020a17090274c700b0016a1be3b7f2mr11425258plt.42.1656544032967; Wed, 29 Jun 2022 16:07:12 -0700 (PDT) Received: from noah-tgl.. ([192.55.60.43]) by smtp.gmail.com with ESMTPSA id h13-20020aa79f4d000000b00525601ded18sm12370101pfr.92.2022.06.29.16.07.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jun 2022 16:07:12 -0700 (PDT) To: libc-alpha@sourceware.org Subject: [PATCH v3 1/3] x86: Add definition for __wmemset_chk AVX2 RTM in ifunc impl list Date: Wed, 29 Jun 2022 16:07:04 -0700 Message-Id: <20220629230706.1264225-1-goldstein.w.n@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628152735.17863-1-goldstein.w.n@gmail.com> References: <20220628152735.17863-1-goldstein.w.n@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Noah Goldstein via Libc-alpha From: Noah Goldstein Reply-To: Noah Goldstein Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org Sender: "Libc-alpha" This was simply missing and meant we weren't testing it properly. --- sysdeps/x86_64/multiarch/ifunc-impl-list.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c index e6418a5ba3..86e1054024 100644 --- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c +++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c @@ -1051,6 +1051,10 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, IFUNC_IMPL_ADD (array, i, __wmemset_chk, CPU_FEATURE_USABLE (AVX2), __wmemset_chk_avx2_unaligned) + IFUNC_IMPL_ADD (array, i, __wmemset_chk, + (CPU_FEATURE_USABLE (AVX2) + && CPU_FEATURE_USABLE (RTM)), + __wmemset_chk_avx2_unaligned_rtm) IFUNC_IMPL_ADD (array, i, __wmemset_chk, (CPU_FEATURE_USABLE (AVX512VL) && CPU_FEATURE_USABLE (AVX512BW) From patchwork Wed Jun 29 23:07:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Noah Goldstein X-Patchwork-Id: 55569 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0042D3841452 for ; Wed, 29 Jun 2022 23:07:37 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 0042D3841452 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1656544058; bh=wKyqMoXrZHrM8JPSiLwLmSc/EK9L3oeg9pCFQtYJu0M=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=JoqDSwCuBbMHg4MUQhtyI9Kns/iAPiXvwG3jkcCq66Gz8kXVKVRJqIPUpd1jod+tL r2jFxU7G9mjMDqnwbO66rQhsUimfbldhXVF3UsHQXJIbZQaJBjN4QZZ9+9q21+H5WE OulxuiCPFOzYWaQIFEaqojm4M+UsSQe17FXAv0ig= X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by sourceware.org (Postfix) with ESMTPS id 6A5AD38485AE for ; Wed, 29 Jun 2022 23:07:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 6A5AD38485AE Received: by mail-pl1-x62c.google.com with SMTP id k14so15450227plh.4 for ; Wed, 29 Jun 2022 16:07:15 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wKyqMoXrZHrM8JPSiLwLmSc/EK9L3oeg9pCFQtYJu0M=; b=xPLTZjmkPaO3S9/9rQSlu4p5izeCVN5dpBpTcqliVwQGsvCG5cn+01TC7asN9SOpG9 9qcTYJzheDY3lFElwvJf84dchWWNEjttfh09NJszCeWuXbnLU3X+GLnLhzij5VOp0rsS 5YG8bYd/jyYwMKZ9jDp5C7rcQwAGPEWygj7HwpAA8Kcd2+1sil06wuey/RqqREXJ5yRt oUfjPRuUJcHHwQ4d1lCi/eXMXk93BzxRhT+Sdh9UBhi9qjpThN5PX1q77NHPmhISMn9k 5QTSeiogfzADWOugB+9DR9vxtTWsIWz2L3mg3xNYShuq1fjYdjLqymw+lyc1mbwAhrAg NZsA== X-Gm-Message-State: AJIora85TBovTw6Sz2GYHrYCZfHqcaXkMnnFN6uuqtRc6VyNee69Y6se g0pYdCR7Hud4/GxY6XSYLyBlPJc4880= X-Google-Smtp-Source: AGRyM1uL7MXlwaR8bbrX1KAUi9O/HIlcOFyvBWXBnZ1ml0Fa+/NLw+9V/nqE7W8OdUcMv8Kwn54HtA== X-Received: by 2002:a17:902:f683:b0:16a:17d0:8a6a with SMTP id l3-20020a170902f68300b0016a17d08a6amr12803122plg.60.1656544034203; Wed, 29 Jun 2022 16:07:14 -0700 (PDT) Received: from noah-tgl.. ([192.55.60.43]) by smtp.gmail.com with ESMTPSA id h13-20020aa79f4d000000b00525601ded18sm12370101pfr.92.2022.06.29.16.07.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jun 2022 16:07:13 -0700 (PDT) To: libc-alpha@sourceware.org Subject: [PATCH v3 2/3] x86: Move and slightly improve memset_erms Date: Wed, 29 Jun 2022 16:07:05 -0700 Message-Id: <20220629230706.1264225-2-goldstein.w.n@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220629230706.1264225-1-goldstein.w.n@gmail.com> References: <20220628152735.17863-1-goldstein.w.n@gmail.com> <20220629230706.1264225-1-goldstein.w.n@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Noah Goldstein via Libc-alpha From: Noah Goldstein Reply-To: Noah Goldstein Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org Sender: "Libc-alpha" Implementation wise: 1. Remove the VZEROUPPER as memset_{impl}_unaligned_erms does not use the L(stosb) label that was previously defined. 2. Don't give the hotpath (fallthrough) to zero size. Code positioning wise: Move memset_{chk}_erms to its own file. Leaving it in between the memset_{impl}_unaligned both adds unnecessary complexity to the file and wastes space in a relatively hot cache section. --- sysdeps/x86_64/multiarch/Makefile | 1 + sysdeps/x86_64/multiarch/memset-erms.S | 44 +++++++++++++++++++ .../multiarch/memset-vec-unaligned-erms.S | 31 ------------- 3 files changed, 45 insertions(+), 31 deletions(-) create mode 100644 sysdeps/x86_64/multiarch/memset-erms.S diff --git a/sysdeps/x86_64/multiarch/Makefile b/sysdeps/x86_64/multiarch/Makefile index 62a4d96fb8..18cea04423 100644 --- a/sysdeps/x86_64/multiarch/Makefile +++ b/sysdeps/x86_64/multiarch/Makefile @@ -30,6 +30,7 @@ sysdep_routines += \ memset-avx2-unaligned-erms-rtm \ memset-avx512-no-vzeroupper \ memset-avx512-unaligned-erms \ + memset-erms \ memset-evex-unaligned-erms \ memset-sse2-unaligned-erms \ rawmemchr-avx2 \ diff --git a/sysdeps/x86_64/multiarch/memset-erms.S b/sysdeps/x86_64/multiarch/memset-erms.S new file mode 100644 index 0000000000..e83cccc731 --- /dev/null +++ b/sysdeps/x86_64/multiarch/memset-erms.S @@ -0,0 +1,44 @@ +/* memset implement with rep stosb + Copyright (C) 2022 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + + +#include + +#if defined USE_MULTIARCH && IS_IN (libc) + .text +ENTRY (__memset_chk_erms) + cmp %RDX_LP, %RCX_LP + jb HIDDEN_JUMPTARGET (__chk_fail) +END (__memset_chk_erms) + +/* Only used to measure performance of REP STOSB. */ +ENTRY (__memset_erms) + /* Skip zero length. */ + test %RDX_LP, %RDX_LP + jz L(stosb_return_zero) + mov %RDX_LP, %RCX_LP + movzbl %sil, %eax + mov %RDI_LP, %RDX_LP + rep stosb + mov %RDX_LP, %RAX_LP + ret +L(stosb_return_zero): + movq %rdi, %rax + ret +END (__memset_erms) +#endif diff --git a/sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S b/sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S index abc12d9cda..905d0fa464 100644 --- a/sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S +++ b/sysdeps/x86_64/multiarch/memset-vec-unaligned-erms.S @@ -156,37 +156,6 @@ L(entry_from_wmemset): #if defined USE_MULTIARCH && IS_IN (libc) END (MEMSET_SYMBOL (__memset, unaligned)) -# if VEC_SIZE == 16 -ENTRY (__memset_chk_erms) - cmp %RDX_LP, %RCX_LP - jb HIDDEN_JUMPTARGET (__chk_fail) -END (__memset_chk_erms) - -/* Only used to measure performance of REP STOSB. */ -ENTRY (__memset_erms) - /* Skip zero length. */ - test %RDX_LP, %RDX_LP - jnz L(stosb) - movq %rdi, %rax - ret -# else -/* Provide a hidden symbol to debugger. */ - .hidden MEMSET_SYMBOL (__memset, erms) -ENTRY (MEMSET_SYMBOL (__memset, erms)) -# endif -L(stosb): - mov %RDX_LP, %RCX_LP - movzbl %sil, %eax - mov %RDI_LP, %RDX_LP - rep stosb - mov %RDX_LP, %RAX_LP - VZEROUPPER_RETURN -# if VEC_SIZE == 16 -END (__memset_erms) -# else -END (MEMSET_SYMBOL (__memset, erms)) -# endif - # if defined SHARED && IS_IN (libc) ENTRY_CHK (MEMSET_CHK_SYMBOL (__memset_chk, unaligned_erms)) cmp %RDX_LP, %RCX_LP From patchwork Wed Jun 29 23:07:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Noah Goldstein X-Patchwork-Id: 55572 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 44CFF383F958 for ; Wed, 29 Jun 2022 23:08:21 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 44CFF383F958 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1656544101; bh=iddtk1Xl9uM4Lgh9rnNrSlQnd9GT0yZzKzkpONojEcw=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=bHigVUkzlq0CIdWutIV9dDhYMuKz64eCjQSyGKjmKL6kwk9tlNGOP7hpW6Ocq+uXY Qwvl5oLL7RF/U/1ne0wenA+rbWcQXzHXe6JHS5YVPyXtt2LpMZScVDW7r1uLsIzBk4 kMzg+JUGEKgnP3KPpwh/K5mYl6VUbFXCU10478yY= X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by sourceware.org (Postfix) with ESMTPS id 40E3D38485BF for ; Wed, 29 Jun 2022 23:07:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 40E3D38485BF Received: by mail-pl1-x632.google.com with SMTP id x20so9833731plx.6 for ; Wed, 29 Jun 2022 16:07:17 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iddtk1Xl9uM4Lgh9rnNrSlQnd9GT0yZzKzkpONojEcw=; b=mmQBSOGoOqVSzMB0pgRcF1lzsyflyOeswtOssjlEWIcqgxKWYMXqZHSVN72NYR3/lc s6Y+6kju5TYlnC1dg7gtpDjNn6lW9UvZwz5pC9v3ZhotvP3mDQJX2E/BOl7vJnw+BUnY iKXdFmwU5edUop1Zsidkf21tK4V5SGO8A/WOFhUdPNr0wCv3muoyQMdZsvb/m9s5PW5J rG2aE1+qVVmRoXSpG88RYa8p0WqWF9wkohTcq8n6UMEZ3c3mr5PZnzvT9aPfbod172X2 t72eYk+K4naE385h7bp7QAiI2iw7ItUVn6BLcHgzf03cRi339h2M6BWF6p836xRxq8Mw VRdA== X-Gm-Message-State: AJIora/LLwEcEMadCGJ96mWSoL8hRe2XEu1FovPOvW7trCB89QnBR9Vv +12v7lODR9skC18R6Uux8vgo/rSg7uw= X-Google-Smtp-Source: AGRyM1tKJqlxFaoE5sbI8d3S1BSPM+CCUZcERsKz8vLObeC0isx6l9AhaWdpNrRvsghkNkdBBS4FXg== X-Received: by 2002:a17:903:22c9:b0:16a:749b:16d6 with SMTP id y9-20020a17090322c900b0016a749b16d6mr11317688plg.32.1656544035882; Wed, 29 Jun 2022 16:07:15 -0700 (PDT) Received: from noah-tgl.. ([192.55.60.43]) by smtp.gmail.com with ESMTPSA id h13-20020aa79f4d000000b00525601ded18sm12370101pfr.92.2022.06.29.16.07.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Jun 2022 16:07:15 -0700 (PDT) To: libc-alpha@sourceware.org Subject: [PATCH v3 3/3] x86: Add support for building {w}memset{_chk} with explicit ISA level Date: Wed, 29 Jun 2022 16:07:06 -0700 Message-Id: <20220629230706.1264225-3-goldstein.w.n@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220629230706.1264225-1-goldstein.w.n@gmail.com> References: <20220628152735.17863-1-goldstein.w.n@gmail.com> <20220629230706.1264225-1-goldstein.w.n@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Noah Goldstein via Libc-alpha From: Noah Goldstein Reply-To: Noah Goldstein Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org Sender: "Libc-alpha" 1. Refactor files so that all implementations are in the multiarch directory - Moved the implementation portion of memset sse2 from memset.S to multiarch/memset-sse2.S - The non-multiarch file now only includes one of the implementations in the multiarch directory based on the compiled ISA level (only used for non-multiarch builds. Otherwise we go through the ifunc selector). 2. Add ISA level build guards to different implementations. - I.e memset-avx2-unaligned-erms.S which is ISA level 3 will only build if compiled ISA level <= 3. Otherwise there is no reason to include it as we will always use one of the ISA level 4 implementations (memset-evex-unaligned-erms.S). 3. Add new multiarch/rtld-memset.S that just include the non-multiarch memset.S which will in turn select the best implementation based on the compiled ISA level. 4. Refactor the ifunc selector and ifunc implementation list to use the ISA level aware wrapper macros that allow functions below the compiled ISA level (with a guranteed replacement) to be skipped. Tested with and without multiarch on x86_64 for ISA levels: {generic, x86-64-v2, x86-64-v3, x86-64-v4} And m32 with and without multiarch. --- sysdeps/x86_64/memset.S | 45 +--- sysdeps/x86_64/multiarch/ifunc-impl-list.c | 249 +++++++++--------- sysdeps/x86_64/multiarch/ifunc-memset.h | 45 ++-- sysdeps/x86_64/multiarch/ifunc-wmemset.h | 21 +- .../multiarch/memset-avx2-unaligned-erms.S | 5 +- .../multiarch/memset-avx512-no-vzeroupper.S | 4 +- .../multiarch/memset-avx512-unaligned-erms.S | 12 +- .../multiarch/memset-evex-unaligned-erms.S | 12 +- .../multiarch/memset-sse2-unaligned-erms.S | 57 +++- sysdeps/x86_64/multiarch/rtld-memset.S | 18 ++ 10 files changed, 265 insertions(+), 203 deletions(-) create mode 100644 sysdeps/x86_64/multiarch/rtld-memset.S diff --git a/sysdeps/x86_64/memset.S b/sysdeps/x86_64/memset.S index a6eea61a4d..f4e1bab601 100644 --- a/sysdeps/x86_64/memset.S +++ b/sysdeps/x86_64/memset.S @@ -18,47 +18,18 @@ . */ #include -#define USE_WITH_SSE2 1 -#define VEC_SIZE 16 -#define MOV_SIZE 3 -#define RET_SIZE 1 +#define MEMSET_SYMBOL(p,s) memset +#define MEMSET_CHK_SYMBOL(p,s) p -#define VEC(i) xmm##i -#define VMOVU movups -#define VMOVA movaps +#define WMEMSET_SYMBOL(p,s) __wmemset +#define WMEMSET_CHK_SYMBOL(p,s) p -# define MEMSET_SET_VEC0_AND_SET_RETURN(d, r) \ - movd d, %xmm0; \ - movq r, %rax; \ - punpcklbw %xmm0, %xmm0; \ - punpcklwd %xmm0, %xmm0; \ - pshufd $0, %xmm0, %xmm0 +#define DEFAULT_IMPL_V1 "multiarch/memset-sse2-unaligned-erms.S" +#define DEFAULT_IMPL_V3 "multiarch/memset-avx2-unaligned-erms.S" +#define DEFAULT_IMPL_V4 "multiarch/memset-evex-unaligned-erms.S" -# define WMEMSET_SET_VEC0_AND_SET_RETURN(d, r) \ - movd d, %xmm0; \ - pshufd $0, %xmm0, %xmm0; \ - movq r, %rax - -# define MEMSET_VDUP_TO_VEC0_HIGH() -# define MEMSET_VDUP_TO_VEC0_LOW() - -# define WMEMSET_VDUP_TO_VEC0_HIGH() -# define WMEMSET_VDUP_TO_VEC0_LOW() - -#define SECTION(p) p - -#ifndef MEMSET_SYMBOL -# define MEMSET_CHK_SYMBOL(p,s) p -# define MEMSET_SYMBOL(p,s) memset -#endif - -#ifndef WMEMSET_SYMBOL -# define WMEMSET_CHK_SYMBOL(p,s) p -# define WMEMSET_SYMBOL(p,s) __wmemset -#endif - -#include "multiarch/memset-vec-unaligned-erms.S" +#include "isa-default-impl.h" libc_hidden_builtin_def (memset) diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c index 86e1054024..c8f95eb940 100644 --- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c +++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c @@ -212,94 +212,99 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, IFUNC_IMPL (i, name, __memset_chk, IFUNC_IMPL_ADD (array, i, __memset_chk, 1, __memset_chk_erms) - IFUNC_IMPL_ADD (array, i, __memset_chk, 1, - __memset_chk_sse2_unaligned) - IFUNC_IMPL_ADD (array, i, __memset_chk, 1, - __memset_chk_sse2_unaligned_erms) - IFUNC_IMPL_ADD (array, i, __memset_chk, - CPU_FEATURE_USABLE (AVX2), - __memset_chk_avx2_unaligned) - IFUNC_IMPL_ADD (array, i, __memset_chk, - CPU_FEATURE_USABLE (AVX2), - __memset_chk_avx2_unaligned_erms) - IFUNC_IMPL_ADD (array, i, __memset_chk, - (CPU_FEATURE_USABLE (AVX2) - && CPU_FEATURE_USABLE (RTM)), - __memset_chk_avx2_unaligned_rtm) - IFUNC_IMPL_ADD (array, i, __memset_chk, - (CPU_FEATURE_USABLE (AVX2) - && CPU_FEATURE_USABLE (RTM)), - __memset_chk_avx2_unaligned_erms_rtm) - IFUNC_IMPL_ADD (array, i, __memset_chk, - (CPU_FEATURE_USABLE (AVX512VL) - && CPU_FEATURE_USABLE (AVX512BW) - && CPU_FEATURE_USABLE (BMI2)), - __memset_chk_evex_unaligned) - IFUNC_IMPL_ADD (array, i, __memset_chk, - (CPU_FEATURE_USABLE (AVX512VL) - && CPU_FEATURE_USABLE (AVX512BW) - && CPU_FEATURE_USABLE (BMI2)), - __memset_chk_evex_unaligned_erms) - IFUNC_IMPL_ADD (array, i, __memset_chk, - (CPU_FEATURE_USABLE (AVX512VL) - && CPU_FEATURE_USABLE (AVX512BW) - && CPU_FEATURE_USABLE (BMI2)), - __memset_chk_avx512_unaligned_erms) - IFUNC_IMPL_ADD (array, i, __memset_chk, - (CPU_FEATURE_USABLE (AVX512VL) - && CPU_FEATURE_USABLE (AVX512BW) - && CPU_FEATURE_USABLE (BMI2)), - __memset_chk_avx512_unaligned) - IFUNC_IMPL_ADD (array, i, __memset_chk, - CPU_FEATURE_USABLE (AVX512F), - __memset_chk_avx512_no_vzeroupper) + X86_IFUNC_IMPL_ADD_V4 (array, i, __memset_chk, + (CPU_FEATURE_USABLE (AVX512VL) + && CPU_FEATURE_USABLE (AVX512BW) + && CPU_FEATURE_USABLE (BMI2)), + __memset_chk_avx512_unaligned_erms) + X86_IFUNC_IMPL_ADD_V4 (array, i, __memset_chk, + (CPU_FEATURE_USABLE (AVX512VL) + && CPU_FEATURE_USABLE (AVX512BW) + && CPU_FEATURE_USABLE (BMI2)), + __memset_chk_avx512_unaligned) + X86_IFUNC_IMPL_ADD_V4 (array, i, __memset_chk, + CPU_FEATURE_USABLE (AVX512F), + __memset_chk_avx512_no_vzeroupper) + X86_IFUNC_IMPL_ADD_V4 (array, i, __memset_chk, + (CPU_FEATURE_USABLE (AVX512VL) + && CPU_FEATURE_USABLE (AVX512BW) + && CPU_FEATURE_USABLE (BMI2)), + __memset_chk_evex_unaligned) + X86_IFUNC_IMPL_ADD_V4 (array, i, __memset_chk, + (CPU_FEATURE_USABLE (AVX512VL) + && CPU_FEATURE_USABLE (AVX512BW) + && CPU_FEATURE_USABLE (BMI2)), + __memset_chk_evex_unaligned_erms) + X86_IFUNC_IMPL_ADD_V3 (array, i, __memset_chk, + CPU_FEATURE_USABLE (AVX2), + __memset_chk_avx2_unaligned) + X86_IFUNC_IMPL_ADD_V3 (array, i, __memset_chk, + CPU_FEATURE_USABLE (AVX2), + __memset_chk_avx2_unaligned_erms) + X86_IFUNC_IMPL_ADD_V3 (array, i, __memset_chk, + (CPU_FEATURE_USABLE (AVX2) + && CPU_FEATURE_USABLE (RTM)), + __memset_chk_avx2_unaligned_rtm) + X86_IFUNC_IMPL_ADD_V3 (array, i, __memset_chk, + (CPU_FEATURE_USABLE (AVX2) + && CPU_FEATURE_USABLE (RTM)), + __memset_chk_avx2_unaligned_erms_rtm) + /* ISA V2 wrapper for SSE2 implementation because the SSE2 + implementation is also used at ISA level 2. */ + X86_IFUNC_IMPL_ADD_V2 (array, i, __memset_chk, 1, + __memset_chk_sse2_unaligned) + X86_IFUNC_IMPL_ADD_V2 (array, i, __memset_chk, 1, + __memset_chk_sse2_unaligned_erms) ) #endif /* Support sysdeps/x86_64/multiarch/memset.c. */ IFUNC_IMPL (i, name, memset, IFUNC_IMPL_ADD (array, i, memset, 1, - __memset_sse2_unaligned) - IFUNC_IMPL_ADD (array, i, memset, 1, - __memset_sse2_unaligned_erms) - IFUNC_IMPL_ADD (array, i, memset, 1, __memset_erms) - IFUNC_IMPL_ADD (array, i, memset, - CPU_FEATURE_USABLE (AVX2), - __memset_avx2_unaligned) - IFUNC_IMPL_ADD (array, i, memset, - CPU_FEATURE_USABLE (AVX2), - __memset_avx2_unaligned_erms) - IFUNC_IMPL_ADD (array, i, memset, - (CPU_FEATURE_USABLE (AVX2) - && CPU_FEATURE_USABLE (RTM)), - __memset_avx2_unaligned_rtm) - IFUNC_IMPL_ADD (array, i, memset, - (CPU_FEATURE_USABLE (AVX2) - && CPU_FEATURE_USABLE (RTM)), - __memset_avx2_unaligned_erms_rtm) - IFUNC_IMPL_ADD (array, i, memset, - (CPU_FEATURE_USABLE (AVX512VL) - && CPU_FEATURE_USABLE (AVX512BW) - && CPU_FEATURE_USABLE (BMI2)), - __memset_evex_unaligned) - IFUNC_IMPL_ADD (array, i, memset, - (CPU_FEATURE_USABLE (AVX512VL) - && CPU_FEATURE_USABLE (AVX512BW) - && CPU_FEATURE_USABLE (BMI2)), - __memset_evex_unaligned_erms) - IFUNC_IMPL_ADD (array, i, memset, - (CPU_FEATURE_USABLE (AVX512VL) - && CPU_FEATURE_USABLE (AVX512BW) - && CPU_FEATURE_USABLE (BMI2)), - __memset_avx512_unaligned_erms) - IFUNC_IMPL_ADD (array, i, memset, - (CPU_FEATURE_USABLE (AVX512VL) - && CPU_FEATURE_USABLE (AVX512BW) - && CPU_FEATURE_USABLE (BMI2)), - __memset_avx512_unaligned) - IFUNC_IMPL_ADD (array, i, memset, - CPU_FEATURE_USABLE (AVX512F), - __memset_avx512_no_vzeroupper) + __memset_erms) + X86_IFUNC_IMPL_ADD_V4 (array, i, memset, + (CPU_FEATURE_USABLE (AVX512VL) + && CPU_FEATURE_USABLE (AVX512BW) + && CPU_FEATURE_USABLE (BMI2)), + __memset_avx512_unaligned_erms) + X86_IFUNC_IMPL_ADD_V4 (array, i, memset, + (CPU_FEATURE_USABLE (AVX512VL) + && CPU_FEATURE_USABLE (AVX512BW) + && CPU_FEATURE_USABLE (BMI2)), + __memset_avx512_unaligned) + X86_IFUNC_IMPL_ADD_V4 (array, i, memset, + CPU_FEATURE_USABLE (AVX512F), + __memset_avx512_no_vzeroupper) + X86_IFUNC_IMPL_ADD_V4 (array, i, memset, + (CPU_FEATURE_USABLE (AVX512VL) + && CPU_FEATURE_USABLE (AVX512BW) + && CPU_FEATURE_USABLE (BMI2)), + __memset_evex_unaligned) + X86_IFUNC_IMPL_ADD_V4 (array, i, memset, + (CPU_FEATURE_USABLE (AVX512VL) + && CPU_FEATURE_USABLE (AVX512BW) + && CPU_FEATURE_USABLE (BMI2)), + __memset_evex_unaligned_erms) + X86_IFUNC_IMPL_ADD_V3 (array, i, memset, + CPU_FEATURE_USABLE (AVX2), + __memset_avx2_unaligned) + X86_IFUNC_IMPL_ADD_V3 (array, i, memset, + CPU_FEATURE_USABLE (AVX2), + __memset_avx2_unaligned_erms) + X86_IFUNC_IMPL_ADD_V3 (array, i, memset, + (CPU_FEATURE_USABLE (AVX2) + && CPU_FEATURE_USABLE (RTM)), + __memset_avx2_unaligned_rtm) + X86_IFUNC_IMPL_ADD_V3 (array, i, memset, + (CPU_FEATURE_USABLE (AVX2) + && CPU_FEATURE_USABLE (RTM)), + __memset_avx2_unaligned_erms_rtm) + /* ISA V2 wrapper for SSE2 implementation because the SSE2 + implementation is also used at ISA level 2. */ + X86_IFUNC_IMPL_ADD_V2 (array, i, memset, 1, + __memset_sse2_unaligned) + X86_IFUNC_IMPL_ADD_V2 (array, i, memset, 1, + __memset_sse2_unaligned_erms) ) /* Support sysdeps/x86_64/multiarch/rawmemchr.c. */ @@ -818,25 +823,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, /* Support sysdeps/x86_64/multiarch/wmemset.c. */ IFUNC_IMPL (i, name, wmemset, - IFUNC_IMPL_ADD (array, i, wmemset, 1, - __wmemset_sse2_unaligned) - IFUNC_IMPL_ADD (array, i, wmemset, - CPU_FEATURE_USABLE (AVX2), - __wmemset_avx2_unaligned) - IFUNC_IMPL_ADD (array, i, wmemset, - (CPU_FEATURE_USABLE (AVX2) - && CPU_FEATURE_USABLE (RTM)), - __wmemset_avx2_unaligned_rtm) - IFUNC_IMPL_ADD (array, i, wmemset, - (CPU_FEATURE_USABLE (AVX512VL) - && CPU_FEATURE_USABLE (AVX512BW) - && CPU_FEATURE_USABLE (BMI2)), - __wmemset_evex_unaligned) - IFUNC_IMPL_ADD (array, i, wmemset, - (CPU_FEATURE_USABLE (AVX512VL) - && CPU_FEATURE_USABLE (AVX512BW) - && CPU_FEATURE_USABLE (BMI2)), - __wmemset_avx512_unaligned)) + X86_IFUNC_IMPL_ADD_V4 (array, i, wmemset, + (CPU_FEATURE_USABLE (AVX512VL) + && CPU_FEATURE_USABLE (AVX512BW) + && CPU_FEATURE_USABLE (BMI2)), + __wmemset_evex_unaligned) + X86_IFUNC_IMPL_ADD_V4 (array, i, wmemset, + (CPU_FEATURE_USABLE (AVX512VL) + && CPU_FEATURE_USABLE (AVX512BW) + && CPU_FEATURE_USABLE (BMI2)), + __wmemset_avx512_unaligned) + X86_IFUNC_IMPL_ADD_V3 (array, i, wmemset, + CPU_FEATURE_USABLE (AVX2), + __wmemset_avx2_unaligned) + X86_IFUNC_IMPL_ADD_V3 (array, i, wmemset, + (CPU_FEATURE_USABLE (AVX2) + && CPU_FEATURE_USABLE (RTM)), + __wmemset_avx2_unaligned_rtm) + /* ISA V2 wrapper for SSE2 implementation because the SSE2 + implementation is also used at ISA level 2. */ + X86_IFUNC_IMPL_ADD_V2 (array, i, wmemset, 1, + __wmemset_sse2_unaligned)) #ifdef SHARED /* Support sysdeps/x86_64/multiarch/memcpy_chk.c. */ @@ -1046,25 +1053,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, #ifdef SHARED /* Support sysdeps/x86_64/multiarch/wmemset_chk.c. */ IFUNC_IMPL (i, name, __wmemset_chk, - IFUNC_IMPL_ADD (array, i, __wmemset_chk, 1, - __wmemset_chk_sse2_unaligned) - IFUNC_IMPL_ADD (array, i, __wmemset_chk, - CPU_FEATURE_USABLE (AVX2), - __wmemset_chk_avx2_unaligned) - IFUNC_IMPL_ADD (array, i, __wmemset_chk, - (CPU_FEATURE_USABLE (AVX2) - && CPU_FEATURE_USABLE (RTM)), - __wmemset_chk_avx2_unaligned_rtm) - IFUNC_IMPL_ADD (array, i, __wmemset_chk, - (CPU_FEATURE_USABLE (AVX512VL) - && CPU_FEATURE_USABLE (AVX512BW) - && CPU_FEATURE_USABLE (BMI2)), - __wmemset_chk_evex_unaligned) - IFUNC_IMPL_ADD (array, i, __wmemset_chk, - (CPU_FEATURE_USABLE (AVX512VL) - && CPU_FEATURE_USABLE (AVX512BW) - && CPU_FEATURE_USABLE (BMI2)), - __wmemset_chk_avx512_unaligned)) + X86_IFUNC_IMPL_ADD_V4 (array, i, __wmemset_chk, + (CPU_FEATURE_USABLE (AVX512VL) + && CPU_FEATURE_USABLE (AVX512BW) + && CPU_FEATURE_USABLE (BMI2)), + __wmemset_chk_evex_unaligned) + X86_IFUNC_IMPL_ADD_V4 (array, i, __wmemset_chk, + (CPU_FEATURE_USABLE (AVX512VL) + && CPU_FEATURE_USABLE (AVX512BW) + && CPU_FEATURE_USABLE (BMI2)), + __wmemset_chk_avx512_unaligned) + X86_IFUNC_IMPL_ADD_V3 (array, i, __wmemset_chk, + CPU_FEATURE_USABLE (AVX2), + __wmemset_chk_avx2_unaligned) + X86_IFUNC_IMPL_ADD_V3 (array, i, __wmemset_chk, + (CPU_FEATURE_USABLE (AVX2) + && CPU_FEATURE_USABLE (RTM)), + __wmemset_chk_avx2_unaligned_rtm) + /* ISA V2 wrapper for SSE2 implementation because the SSE2 + implementation is also used at ISA level 2. */ + X86_IFUNC_IMPL_ADD_V2 (array, i, __wmemset_chk, 1, + __wmemset_chk_sse2_unaligned)) #endif return 0; diff --git a/sysdeps/x86_64/multiarch/ifunc-memset.h b/sysdeps/x86_64/multiarch/ifunc-memset.h index 64d179913c..ed514976aa 100644 --- a/sysdeps/x86_64/multiarch/ifunc-memset.h +++ b/sysdeps/x86_64/multiarch/ifunc-memset.h @@ -20,10 +20,19 @@ #include extern __typeof (REDIRECT_NAME) OPTIMIZE (erms) attribute_hidden; -extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2_unaligned) + +extern __typeof (REDIRECT_NAME) OPTIMIZE (avx512_unaligned) attribute_hidden; -extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2_unaligned_erms) +extern __typeof (REDIRECT_NAME) OPTIMIZE (avx512_unaligned_erms) + attribute_hidden; +extern __typeof (REDIRECT_NAME) OPTIMIZE (avx512_no_vzeroupper) + attribute_hidden; + +extern __typeof (REDIRECT_NAME) OPTIMIZE (evex_unaligned) + attribute_hidden; +extern __typeof (REDIRECT_NAME) OPTIMIZE (evex_unaligned_erms) attribute_hidden; + extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_unaligned) attribute_hidden; extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_unaligned_erms) attribute_hidden; @@ -31,31 +40,26 @@ extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_unaligned_rtm) attribute_hidden; extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_unaligned_erms_rtm) attribute_hidden; -extern __typeof (REDIRECT_NAME) OPTIMIZE (evex_unaligned) - attribute_hidden; -extern __typeof (REDIRECT_NAME) OPTIMIZE (evex_unaligned_erms) - attribute_hidden; -extern __typeof (REDIRECT_NAME) OPTIMIZE (avx512_unaligned) - attribute_hidden; -extern __typeof (REDIRECT_NAME) OPTIMIZE (avx512_unaligned_erms) + +extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2_unaligned) attribute_hidden; -extern __typeof (REDIRECT_NAME) OPTIMIZE (avx512_no_vzeroupper) +extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2_unaligned_erms) attribute_hidden; static inline void * IFUNC_SELECTOR (void) { - const struct cpu_features* cpu_features = __get_cpu_features (); + const struct cpu_features *cpu_features = __get_cpu_features (); if (CPU_FEATURES_ARCH_P (cpu_features, Prefer_ERMS)) return OPTIMIZE (erms); - if (CPU_FEATURE_USABLE_P (cpu_features, AVX512F) + if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512F) && !CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_AVX512)) { - if (CPU_FEATURE_USABLE_P (cpu_features, AVX512VL) - && CPU_FEATURE_USABLE_P (cpu_features, AVX512BW) - && CPU_FEATURE_USABLE_P (cpu_features, BMI2)) + if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512VL) + && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512BW) + && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2)) { if (CPU_FEATURE_USABLE_P (cpu_features, ERMS)) return OPTIMIZE (avx512_unaligned_erms); @@ -66,11 +70,11 @@ IFUNC_SELECTOR (void) return OPTIMIZE (avx512_no_vzeroupper); } - if (CPU_FEATURE_USABLE_P (cpu_features, AVX2)) + if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX2)) { - if (CPU_FEATURE_USABLE_P (cpu_features, AVX512VL) - && CPU_FEATURE_USABLE_P (cpu_features, AVX512BW) - && CPU_FEATURE_USABLE_P (cpu_features, BMI2)) + if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512VL) + && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512BW) + && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2)) { if (CPU_FEATURE_USABLE_P (cpu_features, ERMS)) return OPTIMIZE (evex_unaligned_erms); @@ -86,7 +90,8 @@ IFUNC_SELECTOR (void) return OPTIMIZE (avx2_unaligned_rtm); } - if (!CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_VZEROUPPER)) + if (X86_ISA_CPU_FEATURES_ARCH_P (cpu_features, + Prefer_No_VZEROUPPER, !)) { if (CPU_FEATURE_USABLE_P (cpu_features, ERMS)) return OPTIMIZE (avx2_unaligned_erms); diff --git a/sysdeps/x86_64/multiarch/ifunc-wmemset.h b/sysdeps/x86_64/multiarch/ifunc-wmemset.h index 87c48e2387..3810c719c6 100644 --- a/sysdeps/x86_64/multiarch/ifunc-wmemset.h +++ b/sysdeps/x86_64/multiarch/ifunc-wmemset.h @@ -18,22 +18,26 @@ #include -extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2_unaligned) attribute_hidden; +extern __typeof (REDIRECT_NAME) OPTIMIZE (avx512_unaligned) attribute_hidden; + +extern __typeof (REDIRECT_NAME) OPTIMIZE (evex_unaligned) attribute_hidden; + extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_unaligned) attribute_hidden; extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_unaligned_rtm) attribute_hidden; -extern __typeof (REDIRECT_NAME) OPTIMIZE (evex_unaligned) attribute_hidden; -extern __typeof (REDIRECT_NAME) OPTIMIZE (avx512_unaligned) attribute_hidden; + +extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2_unaligned) attribute_hidden; static inline void * IFUNC_SELECTOR (void) { - const struct cpu_features* cpu_features = __get_cpu_features (); + const struct cpu_features *cpu_features = __get_cpu_features (); - if (CPU_FEATURE_USABLE_P (cpu_features, AVX2) - && CPU_FEATURES_ARCH_P (cpu_features, AVX_Fast_Unaligned_Load)) + if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX2) + && X86_ISA_CPU_FEATURES_ARCH_P (cpu_features, + AVX_Fast_Unaligned_Load, !)) { - if (CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)) + if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512VL)) { if (!CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_AVX512)) return OPTIMIZE (avx512_unaligned); @@ -44,7 +48,8 @@ IFUNC_SELECTOR (void) if (CPU_FEATURE_USABLE_P (cpu_features, RTM)) return OPTIMIZE (avx2_unaligned_rtm); - if (!CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_VZEROUPPER)) + if (X86_ISA_CPU_FEATURES_ARCH_P (cpu_features, + Prefer_No_VZEROUPPER, !)) return OPTIMIZE (avx2_unaligned); } diff --git a/sysdeps/x86_64/multiarch/memset-avx2-unaligned-erms.S b/sysdeps/x86_64/multiarch/memset-avx2-unaligned-erms.S index c0bf2875d0..a9054a9122 100644 --- a/sysdeps/x86_64/multiarch/memset-avx2-unaligned-erms.S +++ b/sysdeps/x86_64/multiarch/memset-avx2-unaligned-erms.S @@ -1,4 +1,7 @@ -#if IS_IN (libc) +#include + +#if ISA_SHOULD_BUILD (3) + # define USE_WITH_AVX2 1 # define VEC_SIZE 32 diff --git a/sysdeps/x86_64/multiarch/memset-avx512-no-vzeroupper.S b/sysdeps/x86_64/multiarch/memset-avx512-no-vzeroupper.S index c5be8f57ef..8cc9c16d73 100644 --- a/sysdeps/x86_64/multiarch/memset-avx512-no-vzeroupper.S +++ b/sysdeps/x86_64/multiarch/memset-avx512-no-vzeroupper.S @@ -17,8 +17,10 @@ . */ #include +#include + +#if ISA_SHOULD_BUILD (4) -#if IS_IN (libc) #include "asm-syntax.h" #ifndef MEMSET diff --git a/sysdeps/x86_64/multiarch/memset-avx512-unaligned-erms.S b/sysdeps/x86_64/multiarch/memset-avx512-unaligned-erms.S index 5241216a77..47623b8ee8 100644 --- a/sysdeps/x86_64/multiarch/memset-avx512-unaligned-erms.S +++ b/sysdeps/x86_64/multiarch/memset-avx512-unaligned-erms.S @@ -1,4 +1,7 @@ -#if IS_IN (libc) +#include + +#if ISA_SHOULD_BUILD (4) + # define USE_WITH_AVX512 1 # define VEC_SIZE 64 @@ -30,8 +33,15 @@ # define WMEMSET_VDUP_TO_VEC0_LOW() # define SECTION(p) p##.evex512 + +#ifndef MEMSET_SYMBOL # define MEMSET_SYMBOL(p,s) p##_avx512_##s +#endif +#ifndef WMEMSET_SYMBOL # define WMEMSET_SYMBOL(p,s) p##_avx512_##s +#endif + + # define USE_LESS_VEC_MASK_STORE 1 # include "memset-vec-unaligned-erms.S" #endif diff --git a/sysdeps/x86_64/multiarch/memset-evex-unaligned-erms.S b/sysdeps/x86_64/multiarch/memset-evex-unaligned-erms.S index 6370021506..ac4b2d2d50 100644 --- a/sysdeps/x86_64/multiarch/memset-evex-unaligned-erms.S +++ b/sysdeps/x86_64/multiarch/memset-evex-unaligned-erms.S @@ -1,4 +1,7 @@ -#if IS_IN (libc) +#include + +#if ISA_SHOULD_BUILD (4) + # define USE_WITH_EVEX 1 # define VEC_SIZE 32 @@ -30,8 +33,15 @@ # define WMEMSET_VDUP_TO_VEC0_LOW() # define SECTION(p) p##.evex + +#ifndef MEMSET_SYMBOL # define MEMSET_SYMBOL(p,s) p##_evex_##s +#endif +#ifndef WMEMSET_SYMBOL # define WMEMSET_SYMBOL(p,s) p##_evex_##s +#endif + + # define USE_LESS_VEC_MASK_STORE 1 # include "memset-vec-unaligned-erms.S" #endif diff --git a/sysdeps/x86_64/multiarch/memset-sse2-unaligned-erms.S b/sysdeps/x86_64/multiarch/memset-sse2-unaligned-erms.S index 3d92f6993a..44f9b8888b 100644 --- a/sysdeps/x86_64/multiarch/memset-sse2-unaligned-erms.S +++ b/sysdeps/x86_64/multiarch/memset-sse2-unaligned-erms.S @@ -17,22 +17,51 @@ License along with the GNU C Library; if not, see . */ -#include -#include +#include -#if IS_IN (libc) -# define MEMSET_SYMBOL(p,s) p##_sse2_##s -# define WMEMSET_SYMBOL(p,s) p##_sse2_##s +/* MINIMUM_X86_ISA_LEVEL <= 2 because there is no V2 implementation + so we need this to build for ISA V2 builds. */ +#if ISA_SHOULD_BUILD (2) -# ifdef SHARED -# undef libc_hidden_builtin_def -# define libc_hidden_builtin_def(name) +# include +# define USE_WITH_SSE2 1 + +# define VEC_SIZE 16 +# define MOV_SIZE 3 +# define RET_SIZE 1 + +# define VEC(i) xmm##i +# define VMOVU movups +# define VMOVA movaps + +# define MEMSET_SET_VEC0_AND_SET_RETURN(d, r) \ + movd d, %xmm0; \ + movq r, %rax; \ + punpcklbw %xmm0, %xmm0; \ + punpcklwd %xmm0, %xmm0; \ + pshufd $0, %xmm0, %xmm0 + +# define WMEMSET_SET_VEC0_AND_SET_RETURN(d, r) \ + movd d, %xmm0; \ + pshufd $0, %xmm0, %xmm0; \ + movq r, %rax + +# define MEMSET_VDUP_TO_VEC0_HIGH() +# define MEMSET_VDUP_TO_VEC0_LOW() + +# define WMEMSET_VDUP_TO_VEC0_HIGH() +# define WMEMSET_VDUP_TO_VEC0_LOW() + +# define SECTION(p) p + +# ifndef MEMSET_SYMBOL +# define MEMSET_SYMBOL(p,s) p##_sse2_##s # endif -# undef weak_alias -# define weak_alias(original, alias) -# undef strong_alias -# define strong_alias(ignored1, ignored2) -#endif +# ifndef WMEMSET_SYMBOL +# define WMEMSET_SYMBOL(p,s) p##_sse2_##s +# endif + +# include "memset-vec-unaligned-erms.S" -#include +#endif diff --git a/sysdeps/x86_64/multiarch/rtld-memset.S b/sysdeps/x86_64/multiarch/rtld-memset.S new file mode 100644 index 0000000000..d912bfa7cc --- /dev/null +++ b/sysdeps/x86_64/multiarch/rtld-memset.S @@ -0,0 +1,18 @@ +/* Copyright (C) 2022 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include "../memset.S"