From patchwork Tue Jun 28 11:34:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Sayle X-Patchwork-Id: 55490 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9DBC7399E0FB for ; Tue, 28 Jun 2022 14:37:00 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id 114D7383878F for ; Tue, 28 Jun 2022 11:34:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 114D7383878F Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:Cc:To:From:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=qz1gNXyKs9PfJOW5Oi4An4nbIfR1HVc3mZKvVts/RkM=; b=HHfl220NUnYF98/2q//XrAAtf2 tz6GMIro0zWF5CMblEQcNGz+yEQZg9+0bXBLQrL261rlEYC1KQZNB0B4sdK0EqQ/MgHYejT6BZD4o Qla9VtqexjuHt+VrLARn1EWLa4MKNaAqfiB1Agi3a7aGxONd5czq14aRVTj+ROcGwAeoNF/20do+e mrebxBHUFwkUQPiWbwG91gXvUh/mRpnNMUqRSQOAAvqraYNV88TipfkVnvKTCsWvSUjpLBeVSPKHj G4wvXs15w3OdB4zGoFoOW6jVItVCJR67V16Zhqe9DFrjHobBcjcprVbSfJtwyTL09BYVNLTybtZj5 6Z/Q9Y+g==; Received: from global-5-14.nat-1.net.cam.ac.uk ([131.111.5.14]:49821 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1o69UX-0004S7-AQ; Tue, 28 Jun 2022 07:34:49 -0400 From: "Roger Sayle" To: Subject: [x86 PATCH] Double word logical operation clean-ups in i386.md. Date: Tue, 28 Jun 2022 12:34:46 +0100 Message-ID: <009501d88ae3$13aeed30$3b0cc790$@nextmovesoftware.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AdiK4a8GTmCqkLtWS7u7uHKgfp8Mtg== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-9.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, MEDICAL_SUBJECT, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Hi Uros, As you've requested/suggested, here's a patch that tidies up and unifies doubleword handling in i386.md; converting all doubleword splitters for logic operations to post-reload form, generalizing their define_insn_and_split templates to form (supporting TARGET_64BIT ? TImode : DImode), and where required tweaking the corresponding expanders to use SDWIM to support TImode doubleword operations. These changes incorporate your feedback from https://gcc.gnu.org/pipermail/gcc-patches/2022-June/596205.html where I included many/several of these clean-ups, in a patch to add a new optimization. I agree, it's better to split these out (this patch), and I'll resubmit the (smaller) optimization patch as a follow-up. This patch has been tested on x86_64-pc-linux-gnu with make bootstrap and make -k check, both with and without --target_board=unix{-m32}, with no new failures. Ok for mainline? 2022-06-28 Roger Sayle gcc/ChangeLog * config/i386/i386.md (general_szext_operand): Add TImode support using x86_64_hilo_general_operand predicate. (*cmp_doubleword): Use x86_64_hilo_general_operand predicate. (*add3_doubleword): Improved optimization of zero addition. (and3): Use SDWIM mode iterator to add support for double word bit-wise AND in TImode. Use force_reg when double word immediate operand isn't x86_64_hilo_general_operand. (and3_doubleword): Generalized from anddi3_doubleword and converted into a post-reload splitter. (*andn3_doubleword): Generalized from *andndi3_doubleword. (define_split): Generalize DImode splitters for andn to . One splitter for TARGET_BMI, the other for !TARGET_BMI. (3): Use SDWIM mode iterator to add suppport for double word bit-wise XOR and bit-wise IOR in TImode. Use force_reg when double word immediate operand isn't x86_64_hilo_general_operand. (*di3_doubleword): Generalized from di3_doubleword. (one_cmpl2): Use SDWIM mode iterator to add support for double word bit-wise NOT in TImode. (one_cmpl2_doubleword): Generalize from one_cmpldi2_doubleword and converted into a post-reload splitter. Thanks again, Roger diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index dd173f7..11d3756 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -1192,7 +1192,8 @@ [(QI "general_operand") (HI "general_operand") (SI "x86_64_szext_general_operand") - (DI "x86_64_szext_general_operand")]) + (DI "x86_64_szext_general_operand") + (TI "x86_64_hilo_general_operand")]) (define_mode_attr nonmemory_szext_operand [(QI "nonmemory_operand") @@ -1509,7 +1510,7 @@ (define_insn_and_split "*cmp_doubleword" [(set (reg:CCZ FLAGS_REG) (compare:CCZ (match_operand: 0 "nonimmediate_operand") - (match_operand: 1 "x86_64_general_operand")))] + (match_operand: 1 "x86_64_hilo_general_operand")))] "ix86_pre_reload_split ()" "#" "&& 1" @@ -5802,7 +5803,12 @@ split_double_mode (mode, &operands[0], 3, &operands[0], &operands[3]); if (operands[2] == const0_rtx) { - ix86_expand_binary_operator (PLUS, mode, &operands[3]); + if (operands[5] != const0_rtx) + ix86_expand_binary_operator (PLUS, mode, &operands[3]); + else if (!rtx_equal_p (operands[3], operands[4])) + emit_move_insn (operands[3], operands[4]); + else + emit_note (NOTE_INSN_DELETED); DONE; } }) @@ -9846,19 +9852,22 @@ ;; it should be done with splitters. (define_expand "and3" - [(set (match_operand:SWIM1248x 0 "nonimmediate_operand") - (and:SWIM1248x (match_operand:SWIM1248x 1 "nonimmediate_operand") - (match_operand:SWIM1248x 2 "")))] + [(set (match_operand:SDWIM 0 "nonimmediate_operand") + (and:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand") + (match_operand:SDWIM 2 "")))] "" { machine_mode mode = mode; - if (mode == DImode && !TARGET_64BIT) - ; - else if (const_int_operand (operands[2], mode) - && register_operand (operands[0], mode) - && !(TARGET_ZERO_EXTEND_WITH_AND - && optimize_function_for_speed_p (cfun))) + if (GET_MODE_SIZE (mode) > UNITS_PER_WORD + && !x86_64_hilo_general_operand (operands[2], mode)) + operands[2] = force_reg (mode, operands[2]); + + if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD + && const_int_operand (operands[2], mode) + && register_operand (operands[0], mode) + && !(TARGET_ZERO_EXTEND_WITH_AND + && optimize_function_for_speed_p (cfun))) { unsigned HOST_WIDE_INT ival = UINTVAL (operands[2]); @@ -9880,34 +9889,44 @@ DONE; }) -(define_insn_and_split "*anddi3_doubleword" - [(set (match_operand:DI 0 "nonimmediate_operand") - (and:DI - (match_operand:DI 1 "nonimmediate_operand") - (match_operand:DI 2 "x86_64_szext_general_operand"))) +(define_insn_and_split "*and3_doubleword" + [(set (match_operand: 0 "nonimmediate_operand" "=ro,r") + (and: + (match_operand: 1 "nonimmediate_operand" "%0,0") + (match_operand: 2 "x86_64_hilo_general_operand" "r,o"))) (clobber (reg:CC FLAGS_REG))] - "!TARGET_64BIT - && ix86_binary_operator_ok (AND, DImode, operands) - && ix86_pre_reload_split ()" + "ix86_binary_operator_ok (AND, mode, operands)" "#" - "&& 1" - [(const_int 0)] + "&& reload_completed" + [(const_int:DWIH 0)] { - split_double_mode (DImode, &operands[0], 3, &operands[0], &operands[3]); + bool emit_insn_deleted_note_p = false; + + split_double_mode (mode, &operands[0], 3, &operands[0], &operands[3]); if (operands[2] == const0_rtx) emit_move_insn (operands[0], const0_rtx); else if (operands[2] == constm1_rtx) - emit_move_insn (operands[0], operands[1]); + { + if (!rtx_equal_p (operands[0], operands[1])) + emit_move_insn (operands[0], operands[1]); + else + emit_insn_deleted_note_p = true; + } else - emit_insn (gen_andsi3 (operands[0], operands[1], operands[2])); + ix86_expand_binary_operator (AND, mode, &operands[0]); if (operands[5] == const0_rtx) emit_move_insn (operands[3], const0_rtx); else if (operands[5] == constm1_rtx) - emit_move_insn (operands[3], operands[4]); + { + if (!rtx_equal_p (operands[3], operands[4])) + emit_move_insn (operands[3], operands[4]); + else if (emit_insn_deleted_note_p) + emit_note (NOTE_INSN_DELETED); + } else - emit_insn (gen_andsi3 (operands[3], operands[4], operands[5])); + ix86_expand_binary_operator (AND, mode, &operands[3]); DONE; }) @@ -10391,54 +10410,43 @@ operands[2] = gen_int_mode (INTVAL (operands[2]), QImode); }) -(define_insn "*andndi3_doubleword" - [(set (match_operand:DI 0 "register_operand") - (and:DI - (not:DI (match_operand:DI 1 "register_operand")) - (match_operand:DI 2 "nonimmediate_operand"))) +(define_insn "*andn3_doubleword" + [(set (match_operand:DWI 0 "register_operand") + (and:DWI + (not:DWI (match_operand:DWI 1 "register_operand")) + (match_operand:DWI 2 "nonimmediate_operand"))) (clobber (reg:CC FLAGS_REG))] - "!TARGET_64BIT && TARGET_STV && TARGET_SSE2 - && ix86_pre_reload_split ()" + "ix86_pre_reload_split ()" "#") (define_split - [(set (match_operand:DI 0 "register_operand") - (and:DI - (not:DI (match_operand:DI 1 "register_operand")) - (match_operand:DI 2 "nonimmediate_operand"))) + [(set (match_operand: 0 "register_operand") + (and: + (not: (match_operand: 1 "register_operand")) + (match_operand: 2 "nonimmediate_operand"))) (clobber (reg:CC FLAGS_REG))] - "!TARGET_64BIT && TARGET_BMI && TARGET_STV && TARGET_SSE2 - && can_create_pseudo_p ()" + "TARGET_BMI" [(parallel [(set (match_dup 0) - (and:SI (not:SI (match_dup 1)) (match_dup 2))) + (and:DWIH (not:DWIH (match_dup 1)) (match_dup 2))) (clobber (reg:CC FLAGS_REG))]) (parallel [(set (match_dup 3) - (and:SI (not:SI (match_dup 4)) (match_dup 5))) + (and:DWIH (not:DWIH (match_dup 4)) (match_dup 5))) (clobber (reg:CC FLAGS_REG))])] - "split_double_mode (DImode, &operands[0], 3, &operands[0], &operands[3]);") + "split_double_mode (mode, &operands[0], 3, &operands[0], &operands[3]);") (define_split - [(set (match_operand:DI 0 "register_operand") - (and:DI - (not:DI (match_operand:DI 1 "register_operand")) - (match_operand:DI 2 "nonimmediate_operand"))) + [(set (match_operand:DWI 0 "register_operand") + (and:DWI + (not:DWI (match_operand:DWI 1 "register_operand")) + (match_operand:DWI 2 "nonimmediate_operand"))) (clobber (reg:CC FLAGS_REG))] - "!TARGET_64BIT && !TARGET_BMI && TARGET_STV && TARGET_SSE2 + "!TARGET_BMI && can_create_pseudo_p ()" - [(set (match_dup 6) (not:SI (match_dup 1))) + [(set (match_dup 3) (not:DWI (match_dup 1))) (parallel [(set (match_dup 0) - (and:SI (match_dup 6) (match_dup 2))) - (clobber (reg:CC FLAGS_REG))]) - (set (match_dup 7) (not:SI (match_dup 4))) - (parallel [(set (match_dup 3) - (and:SI (match_dup 7) (match_dup 5))) + (and:DWI (match_dup 3) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])] -{ - operands[6] = gen_reg_rtx (SImode); - operands[7] = gen_reg_rtx (SImode); - - split_double_mode (DImode, &operands[0], 3, &operands[0], &operands[3]); -}) + "operands[3] = gen_reg_rtx (mode);") (define_insn "*andn_1" [(set (match_operand:SWI48 0 "register_operand" "=r,r,?k") @@ -10532,29 +10540,36 @@ ;; If this is considered useful, it should be done with splitters. (define_expand "3" - [(set (match_operand:SWIM1248x 0 "nonimmediate_operand") - (any_or:SWIM1248x (match_operand:SWIM1248x 1 "nonimmediate_operand") - (match_operand:SWIM1248x 2 "")))] + [(set (match_operand:SDWIM 0 "nonimmediate_operand") + (any_or:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand") + (match_operand:SDWIM 2 "")))] "" - "ix86_expand_binary_operator (, mode, operands); DONE;") +{ -(define_insn_and_split "*di3_doubleword" - [(set (match_operand:DI 0 "nonimmediate_operand" "=ro,r") - (any_or:DI - (match_operand:DI 1 "nonimmediate_operand" "0,0") - (match_operand:DI 2 "x86_64_szext_general_operand" "re,o"))) + if (GET_MODE_SIZE (mode) > UNITS_PER_WORD + && !x86_64_hilo_general_operand (operands[2], mode)) + operands[2] = force_reg (mode, operands[2]); + + ix86_expand_binary_operator (, mode, operands); + DONE; +}) + +(define_insn_and_split "*3_doubleword" + [(set (match_operand: 0 "nonimmediate_operand" "=ro,r") + (any_or: + (match_operand: 1 "nonimmediate_operand" "%0,0") + (match_operand: 2 "x86_64_hilo_general_operand" "r,o"))) (clobber (reg:CC FLAGS_REG))] - "!TARGET_64BIT - && ix86_binary_operator_ok (, DImode, operands)" + "ix86_binary_operator_ok (, mode, operands)" "#" "&& reload_completed" - [(const_int 0)] + [(const_int:DWIH 0)] { /* This insn may disappear completely when operands[2] == const0_rtx and operands[0] == operands[1], which requires a NOTE_INSN_DELETED. */ bool emit_insn_deleted_note_p = false; - split_double_mode (DImode, &operands[0], 3, &operands[0], &operands[3]); + split_double_mode (mode, &operands[0], 3, &operands[0], &operands[3]); if (operands[2] == const0_rtx) { @@ -10568,10 +10583,10 @@ if ( == IOR) emit_move_insn (operands[0], constm1_rtx); else - ix86_expand_unary_operator (NOT, SImode, &operands[0]); + ix86_expand_unary_operator (NOT, mode, &operands[0]); } else - ix86_expand_binary_operator (, SImode, &operands[0]); + ix86_expand_binary_operator (, mode, &operands[0]); if (operands[5] == const0_rtx) { @@ -10585,10 +10600,10 @@ if ( == IOR) emit_move_insn (operands[3], constm1_rtx); else - ix86_expand_unary_operator (NOT, SImode, &operands[3]); + ix86_expand_unary_operator (NOT, mode, &operands[3]); } else - ix86_expand_binary_operator (, SImode, &operands[3]); + ix86_expand_binary_operator (, mode, &operands[3]); DONE; }) @@ -11727,24 +11742,22 @@ ;; One complement instructions (define_expand "one_cmpl2" - [(set (match_operand:SWIM1248x 0 "nonimmediate_operand") - (not:SWIM1248x (match_operand:SWIM1248x 1 "nonimmediate_operand")))] + [(set (match_operand:SDWIM 0 "nonimmediate_operand") + (not:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand")))] "" "ix86_expand_unary_operator (NOT, mode, operands); DONE;") -(define_insn_and_split "*one_cmpldi2_doubleword" - [(set (match_operand:DI 0 "nonimmediate_operand") - (not:DI (match_operand:DI 1 "nonimmediate_operand")))] - "!TARGET_64BIT - && ix86_unary_operator_ok (NOT, DImode, operands) - && ix86_pre_reload_split ()" +(define_insn_and_split "*one_cmpl2_doubleword" + [(set (match_operand: 0 "nonimmediate_operand" "=ro") + (not: (match_operand: 1 "nonimmediate_operand" "0")))] + "ix86_unary_operator_ok (NOT, mode, operands)" "#" - "&& 1" + "&& reload_completed" [(set (match_dup 0) - (not:SI (match_dup 1))) + (not:DWIH (match_dup 1))) (set (match_dup 2) - (not:SI (match_dup 3)))] - "split_double_mode (DImode, &operands[0], 2, &operands[0], &operands[2]);") + (not:DWIH (match_dup 3)))] + "split_double_mode (mode, &operands[0], 2, &operands[0], &operands[2]);") (define_insn "*one_cmpl2_1" [(set (match_operand:SWI248 0 "nonimmediate_operand" "=rm,?k")