From patchwork Tue Jun 28 02:03:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Noah Goldstein X-Patchwork-Id: 55464 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 55BE33857827 for ; Tue, 28 Jun 2022 02:04:12 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 55BE33857827 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1656381852; bh=TBovxDvMa0tq+Tk/mXRvn+LiLm67Y1xF8/P8QvMgRNc=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=BC9EVOGxKO8Og7cW9sjkRkYFnw+JZqfANBxgve59rQ+VyOHAsL6WBKs8S3dsT1UuC tR2fhNRGQNQdq0A7/lkGoNRWE7QlFCS8NtdKrhWY8KroymG+8W9G8NxmTf/UkKpOzA WJ0JlwZxg4DVtfenV6dE/LcyuVsnaovtvbWRQUXE= X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by sourceware.org (Postfix) with ESMTPS id B97273858036 for ; Tue, 28 Jun 2022 02:03:46 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org B97273858036 Received: by mail-pl1-x62f.google.com with SMTP id jh14so9785423plb.1 for ; Mon, 27 Jun 2022 19:03:46 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TBovxDvMa0tq+Tk/mXRvn+LiLm67Y1xF8/P8QvMgRNc=; b=IsljgIUs36u3PEMmUT5AZt8wDE249Wn3ClW7q2fey1yCQIPls4wFNx8dPKzhf9T6lw XZlJYsfnCuKspIklaECJDzmsC17paDBNVoi6I+NJNSOZ4Xu2hsAq/RyymnHyOk97Xe5q iZbObdhpmVPsd+wr0DcfWa5561p5DM/h2EZMaA6LQe01ysi5MO12YJ270tefZusoUr9x 7v1iy4zsZl/T7Ttq3WT9V+/NXyCEUX2CJb3S/FtfDU7ZDlJoN7/+BLYJVw7sNphVZ4hj 8nygeydwA7UwfC0/dF6B2h3llLxkI7/A9VTALbcjvUuJrm0FPHNpQvHrUSwAUbgOJFgY Vnig== X-Gm-Message-State: AJIora8BDqBLa6WnItXUy2FTISz/RLWHEvivzUkOwECAv622JNMs7kfW hlQOprOY+ECVX1d3ybgkvVIAFcmGREk= X-Google-Smtp-Source: AGRyM1sll3vqkajni2bW46wvahSKF0EH48soC2f/f/8yKhZ8hYAUpMm2zkD7FfpfyBjuGCgyf+iSMQ== X-Received: by 2002:a17:902:db0c:b0:16a:4b7e:af5e with SMTP id m12-20020a170902db0c00b0016a4b7eaf5emr2376888plx.145.1656381825605; Mon, 27 Jun 2022 19:03:45 -0700 (PDT) Received: from noah-tgl.. ([2600:1010:b016:fb15:ad7e:a465:b31a:6f06]) by smtp.gmail.com with ESMTPSA id x34-20020a634a22000000b0040ca587fe0fsm7698260pga.63.2022.06.27.19.03.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Jun 2022 19:03:45 -0700 (PDT) To: libc-alpha@sourceware.org Subject: [PATCH v2] x86: Add more feature definitions to isa-level.h Date: Mon, 27 Jun 2022 19:03:42 -0700 Message-Id: <20220628020342.213807-1-goldstein.w.n@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220628010446.3464287-1-goldstein.w.n@gmail.com> References: <20220628010446.3464287-1-goldstein.w.n@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Noah Goldstein via Libc-alpha From: Noah Goldstein Reply-To: Noah Goldstein Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org Sender: "Libc-alpha" This commit doesn't change anything in itself. It is just to add definitions that will be needed by future patches. --- sysdeps/x86/isa-level.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h index f293aea906..024d1deb80 100644 --- a/sysdeps/x86/isa-level.h +++ b/sysdeps/x86/isa-level.h @@ -71,11 +71,13 @@ #define AVX512F_X86_ISA_LEVEL 4 #define AVX512VL_X86_ISA_LEVEL 4 #define AVX512BW_X86_ISA_LEVEL 4 +#define AVX512DQ_X86_ISA_LEVEL 4 /* ISA level >= 3 guaranteed includes. */ #define AVX_X86_ISA_LEVEL 3 #define AVX2_X86_ISA_LEVEL 3 #define BMI2_X86_ISA_LEVEL 3 +#define MOVBE_X86_ISA_LEVEL 3 /* NB: This feature is enabled when ISA level >= 3, which was disabled for the following CPUs: @@ -89,6 +91,14 @@ when ISA level < 3. */ #define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3 +/* ISA level >= 2 guaranteed includes. */ +#define SSE4_2_X86_ISA_LEVEL 2 +#define SSSE3_X86_ISA_LEVEL 2 + +/* NB: This feature is enabled when ISA level >= 2. No CPUs should be + affected by this. */ +#define Fast_Unaligned_Load_X86_ISA_LEVEL 2 + /* Both X86_ISA_CPU_FEATURE_USABLE_P and X86_ISA_CPU_FEATURES_ARCH_P macros are wrappers for the respective CPU_FEATURE{S}_{USABLE|ARCH}_P runtime checks. They differ in two ways.