From patchwork Sun Jun 26 11:12:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Sayle X-Patchwork-Id: 55407 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 53F9A386CE67 for ; Sun, 26 Jun 2022 11:13:05 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id EF4EF3850858 for ; Sun, 26 Jun 2022 11:12:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org EF4EF3850858 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:Cc:To:From:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=mae4nONBNTEY0R23uUdRJj7a94ZxfdVsoKhfXZX7/ok=; b=FfkX+tVXy038BX+pxlPpkJ7LT9 EryF6qnQwbltiy81yq/WFdqnnKLqcvEdbfXWzk1PhH6jhjLmeCU2M0u4C8M92+P6D/Pquz4yXKeLY HK+lwTKVyvtWvCtfaoNEvvBpWIJi0MW6DfuRJ4hzlNoqRnSR8lX407kH9jBmkFFHU6gx7MXFdbuCN Tz/3jLixOuiXcc47cSdpAUk9d/U+QkzXcGD6UFwkVrz8yYH4GXheVb6wi0gQdGyVGhpLFpAn7VC4e B8EC+v53P3K4loGbxWO3KoJb/UV7D3hLKa4GzV7afei13u76s9rh4k9o5pPPRYLW+UFBkjBvZVP2V tHRold+w==; Received: from host86-130-134-60.range86-130.btcentralplus.com ([86.130.134.60]:51652 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1o5QC7-0007j1-Tv; Sun, 26 Jun 2022 07:12:48 -0400 From: "Roger Sayle" To: Subject: [x86_64 PATCH] Implement __imag__ of float _Complex using shufps. Date: Sun, 26 Jun 2022 12:12:45 +0100 Message-ID: <022001d8894d$aa3a6370$feaf2a50$@nextmovesoftware.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AdiJTKiX9ZWZxkWOTdi/ln9hFp101w== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This patch is a follow-up improvement to my recent patch for PR rtl-optimization/7061. That patch added the test case gcc.target/i386/pr7061-2.c: float im(float _Complex a) { return __imag__ a; } For which GCC on x86_64 currently generates: movq %xmm0, %rax shrq $32, %rax movd %eax, %xmm0 ret but with this patch we now generate (the same as LLVM): shufps $85, %xmm0, %xmm0 ret This is achieved by providing a define_insn_and_split that allows truncated lshiftrt:DI by 32 to be performed on either SSE or general regs, where if the register allocator prefers to use SSE, we split to a shufps_v4si, or if not, we use a regular shrq. This patch has been tested on x86_64-pc-linux-gnu with make bootstrap and make -k check, with no new failures. Ok for mainline? 2022-06-26 Roger Sayle gcc/ChangeLog PR rtl-optimization/7061 * config/i386/i386.md (*highpartdisi2): New define_insn_and_split. gcc/testsuite/ChangeLog PR rtl-optimization/7061 * gcc.target/i386/pr7061-2.c: Update to look for shufps. Roger diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 5b53841..709598c 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -13234,6 +13234,31 @@ (const_string "*"))) (set_attr "mode" "")]) +;; Specialization of *lshr3_1 below, extracting the SImode +;; highpart of a DI to be extracted, but allowing it to be clobbered. +(define_insn_and_split "*highpartdisi2" + [(set (subreg:DI (match_operand:SI 0 "register_operand" "=r,x,?k") 0) + (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0,k") + (const_int 32))) + (clobber (reg:CC FLAGS_REG))] + "TARGET_64BIT" + "#" + "&& reload_completed" + [(parallel + [(set (match_dup 0) (lshiftrt:DI (match_dup 1) (const_int 32))) + (clobber (reg:CC FLAGS_REG))])] +{ + if (SSE_REG_P (operands[0])) + { + rtx tmp = gen_rtx_REG (V4SImode, REGNO (operands[0])); + emit_insn (gen_sse_shufps_v4si (tmp, tmp, tmp, + const1_rtx, const1_rtx, + GEN_INT (5), GEN_INT (5))); + DONE; + } + operands[0] = gen_rtx_REG (DImode, REGNO (operands[0])); +}) + (define_insn "*lshr3_1" [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r,?k") (lshiftrt:SWI48 diff --git a/gcc/testsuite/gcc.target/i386/pr7061-2.c b/gcc/testsuite/gcc.target/i386/pr7061-2.c index ac33340..837cd83 100644 --- a/gcc/testsuite/gcc.target/i386/pr7061-2.c +++ b/gcc/testsuite/gcc.target/i386/pr7061-2.c @@ -1,5 +1,9 @@ /* { dg-do compile { target { ! ia32 } } } */ /* { dg-options "-O2" } */ float im(float _Complex a) { return __imag__ a; } +/* { dg-final { scan-assembler "shufps" } } */ +/* { dg-final { scan-assembler-not "movd" } } */ +/* { dg-final { scan-assembler-not "movq" } } */ /* { dg-final { scan-assembler-not "movss" } } */ /* { dg-final { scan-assembler-not "rsp" } } */ +/* { dg-final { scan-assembler-not "shr" } } */