From patchwork Wed Jun 22 18:11:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Noah Goldstein X-Patchwork-Id: 55290 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 34F6D3831C97 for ; Wed, 22 Jun 2022 18:12:12 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 34F6D3831C97 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1655921532; bh=3Uuf8vegm3RfQyH1mhvdb7F11UsSXx2Rot29oxc3WOA=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=VnpzJpfmltU5QToXmxy+j+CExtYbPhJUKI04a7GzL5NHD04HlkFmKTNeq4AAlYYGD CV1AyBXriP83Bh0QvMfXuKLn5JqE7t4AqFUfIbgORYnyLPEEIp7LrqFgnYi7gil97z sV1Ay8nqzaHEh8pXz30OspMBIZMn1yeBh1Mbkhrg= X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-pg1-x52c.google.com (mail-pg1-x52c.google.com [IPv6:2607:f8b0:4864:20::52c]) by sourceware.org (Postfix) with ESMTPS id 09E733857B99 for ; Wed, 22 Jun 2022 18:11:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 09E733857B99 Received: by mail-pg1-x52c.google.com with SMTP id h192so16807434pgc.4 for ; Wed, 22 Jun 2022 11:11:48 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3Uuf8vegm3RfQyH1mhvdb7F11UsSXx2Rot29oxc3WOA=; b=gK3T8BQrE5oTerocD+P6Js7lNoxp3IiG2DplxWFgxw6XCbHfoakRITGTexO/Pkakeh g+OhrxhbV6+AcragGS8zca8+6e+j/p3FxBgrQ7IjcwSZCCdq+9AqQXYH2mboo891ZMLF yu47KsV17GoSK/zAgXlivgZbvzg6bf3DIXxsTYwaUF3TSbi6pCAZR0kzZCcGO+X4jC3c wDXMMxINWI45GC4g4dG6hx9dSoZ6NMD5RuKI0zjuSALKgvHKUuNR+A4iUvefbYkZ8DyE GOipIL5heutAvQkTChJ5rLjrZFHdbFGzW24mvvZqUNvVhJf8qcm3T7FR3v8CKDK6fjMK PL5A== X-Gm-Message-State: AJIora+1qAfaAK5LwX+SYRJCrWei2lZeurliaTPgZf9zFRW9aJXM/bqO foNKrg9lOa8rcGRZMXmCJNjb7gC6ZqQ= X-Google-Smtp-Source: AGRyM1sgmnTXbjzoi32oS4tIQQz2qc0m79Gq+t2kVzg2NN2T5CC60zFSWN+cnZvXZZbrMoHsQVg3lQ== X-Received: by 2002:a63:9b01:0:b0:408:ddc7:1056 with SMTP id r1-20020a639b01000000b00408ddc71056mr4031269pgd.155.1655921507159; Wed, 22 Jun 2022 11:11:47 -0700 (PDT) Received: from noah-tgl.. ([2600:1010:b051:c9b1:28ad:233d:7d27:487a]) by smtp.gmail.com with ESMTPSA id f16-20020a17090a121000b001ec8c8300f8sm57715pja.52.2022.06.22.11.11.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jun 2022 11:11:46 -0700 (PDT) To: libc-alpha@sourceware.org Subject: [PATCH v9 1/2] x86: Add defines / utilities for making ISA specific x86 builds Date: Wed, 22 Jun 2022 11:11:40 -0700 Message-Id: <20220622181141.773121-1-goldstein.w.n@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220621161821.2940071-1-goldstein.w.n@gmail.com> References: <20220621161821.2940071-1-goldstein.w.n@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Noah Goldstein via Libc-alpha From: Noah Goldstein Reply-To: Noah Goldstein Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org Sender: "Libc-alpha" 1. Factor out some of the ISA level defines in isa-level.c to standalone header isa-level.h 2. Add new headers with ISA level dependent macros for handling ifuncs. Note, this file does not change any code. Tested with and without multiarch on x86_64 for ISA levels: {generic, x86-64-v2, x86-64-v3, x86-64-v4} --- sysdeps/x86/init-arch.h | 4 +- sysdeps/x86/isa-ifunc-macros.h | 70 ++++++++++++++++++++++ sysdeps/x86/isa-level.c | 17 ++---- sysdeps/x86/isa-level.h | 99 +++++++++++++++++++++++++++++++ sysdeps/x86_64/isa-default-impl.h | 49 +++++++++++++++ 5 files changed, 226 insertions(+), 13 deletions(-) create mode 100644 sysdeps/x86/isa-ifunc-macros.h create mode 100644 sysdeps/x86/isa-level.h create mode 100644 sysdeps/x86_64/isa-default-impl.h diff --git a/sysdeps/x86/init-arch.h b/sysdeps/x86/init-arch.h index 277c15f116..a2886a2532 100644 --- a/sysdeps/x86/init-arch.h +++ b/sysdeps/x86/init-arch.h @@ -19,7 +19,9 @@ #include #include -#ifndef __x86_64__ +#ifdef __x86_64__ +# include +#else /* Due to the reordering and the other nifty extensions in i686, it is not really good to use heavily i586 optimized code on an i686. It's better to use i486 code if it isn't an i586. */ diff --git a/sysdeps/x86/isa-ifunc-macros.h b/sysdeps/x86/isa-ifunc-macros.h new file mode 100644 index 0000000000..ba6826d518 --- /dev/null +++ b/sysdeps/x86/isa-ifunc-macros.h @@ -0,0 +1,70 @@ +/* Common ifunc selection utils + All versions must be listed in ifunc-impl-list.c. + Copyright (C) 2022 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#ifndef _ISA_IFUNC_MACROS_H +#define _ISA_IFUNC_MACROS_H 1 + +#include +#include +#include + +/* Only include at the level of the minimum build ISA or higher. I.e + if built with ISA=V1, then include all implementations. On the + other hand if built with ISA=V3 only include V3/V4 + implementations. If there is no implementation at or above the + minimum build ISA level, then include the highest ISA level + implementation. */ +#if MINIMUM_X86_ISA_LEVEL <= 4 +# define X86_IFUNC_IMPL_ADD_V4(...) IFUNC_IMPL_ADD (__VA_ARGS__) +#endif +#if MINIMUM_X86_ISA_LEVEL <= 3 +# define X86_IFUNC_IMPL_ADD_V3(...) IFUNC_IMPL_ADD (__VA_ARGS__) +#endif +#if MINIMUM_X86_ISA_LEVEL <= 2 +# define X86_IFUNC_IMPL_ADD_V2(...) IFUNC_IMPL_ADD (__VA_ARGS__) +#endif +#if MINIMUM_X86_ISA_LEVEL <= 1 +# define X86_IFUNC_IMPL_ADD_V1(...) IFUNC_IMPL_ADD (__VA_ARGS__) +#endif + +#ifndef X86_IFUNC_IMPL_ADD_V4 +# define X86_IFUNC_IMPL_ADD_V4(...) +#endif +#ifndef X86_IFUNC_IMPL_ADD_V3 +# define X86_IFUNC_IMPL_ADD_V3(...) +#endif +#ifndef X86_IFUNC_IMPL_ADD_V2 +# define X86_IFUNC_IMPL_ADD_V2(...) +#endif +#ifndef X86_IFUNC_IMPL_ADD_V1 +# define X86_IFUNC_IMPL_ADD_V1(...) +#endif + +#define X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED(name) \ + ((name##_X86_ISA_LEVEL) <= MINIMUM_X86_ISA_LEVEL) + +#define X86_ISA_CPU_FEATURE_USABLE_P(ptr, name) \ + (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \ + || CPU_FEATURE_USABLE_P (ptr, name)) + +#define X86_ISA_CPU_FEATURES_ARCH_P(ptr, name) \ + (X86_ISA_CPU_FEATURE_CONST_CHECK_ENABLED (name) \ + || CPU_FEATURES_ARCH_P (ptr, name)) + +#endif diff --git a/sysdeps/x86/isa-level.c b/sysdeps/x86/isa-level.c index 09cd72ab20..5b7a2da870 100644 --- a/sysdeps/x86/isa-level.c +++ b/sysdeps/x86/isa-level.c @@ -26,38 +26,31 @@ . */ #include - +#include /* ELF program property for x86 ISA level. */ #ifdef INCLUDE_X86_ISA_LEVEL -# if defined __SSE__ && defined __SSE2__ +# if MINIMUM_X86_ISA_LEVEL >= 1 /* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */ # define ISA_BASELINE GNU_PROPERTY_X86_ISA_1_BASELINE # else # define ISA_BASELINE 0 # endif -# if ISA_BASELINE && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \ - && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ \ - && defined __SSE3__ && defined __SSSE3__ && defined __SSE4_1__ \ - && defined __SSE4_2__ +# if MINIMUM_X86_ISA_LEVEL >= 2 /* NB: ISAs in x86-64 ISA level v2 are used. */ # define ISA_V2 GNU_PROPERTY_X86_ISA_1_V2 # else # define ISA_V2 0 # endif -# if ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \ - && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \ - && defined __BMI__ && defined __BMI2__ +# if MINIMUM_X86_ISA_LEVEL >= 3 /* NB: ISAs in x86-64 ISA level v3 are used. */ # define ISA_V3 GNU_PROPERTY_X86_ISA_1_V3 # else # define ISA_V3 0 # endif -# if ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \ - && defined __AVX512CD__ && defined __AVX512DQ__ \ - && defined __AVX512VL__ +# if MINIMUM_X86_ISA_LEVEL >= 4 /* NB: ISAs in x86-64 ISA level v4 are used. */ # define ISA_V4 GNU_PROPERTY_X86_ISA_1_V4 # else diff --git a/sysdeps/x86/isa-level.h b/sysdeps/x86/isa-level.h new file mode 100644 index 0000000000..21366b3132 --- /dev/null +++ b/sysdeps/x86/isa-level.h @@ -0,0 +1,99 @@ +/* Header defining the minimum x86 ISA level + Copyright (C) 2022 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + In addition to the permissions in the GNU Lesser General Public + License, the Free Software Foundation gives you unlimited + permission to link the compiled version of this file with other + programs, and to distribute those programs without any restriction + coming from the use of this file. (The Lesser General Public + License restrictions do apply in other respects; for example, they + cover modification of the file, and distribution when not linked + into another program.) + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#ifndef _ISA_LEVEL_H +#define _ISA_LEVEL_H + +#if defined __SSE__ && defined __SSE2__ +/* NB: ISAs, excluding MMX, in x86-64 ISA level baseline are used. */ +# define __X86_ISA_V1 1 +#else +# define __X86_ISA_V1 0 +#endif + +#if __X86_ISA_V1 && defined __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 \ + && defined HAVE_X86_LAHF_SAHF && defined __POPCNT__ && defined __SSE3__ \ + && defined __SSSE3__ && defined __SSE4_1__ && defined __SSE4_2__ +/* NB: ISAs in x86-64 ISA level v2 are used. */ +# define __X86_ISA_V2 1 +#else +# define __X86_ISA_V2 0 +#endif + +#if __X86_ISA_V2 && defined __AVX__ && defined __AVX2__ && defined __F16C__ \ + && defined __FMA__ && defined __LZCNT__ && defined HAVE_X86_MOVBE \ + && defined __BMI__ && defined __BMI2__ +/* NB: ISAs in x86-64 ISA level v3 are used. */ +# define __X86_ISA_V3 1 +#else +# define __X86_ISA_V3 0 +#endif + +#if __X86_ISA_V3 && defined __AVX512F__ && defined __AVX512BW__ \ + && defined __AVX512CD__ && defined __AVX512DQ__ && defined __AVX512VL__ +/* NB: ISAs in x86-64 ISA level v4 are used. */ +# define __X86_ISA_V4 1 +#else +# define __X86_ISA_V4 0 +#endif + +#define MINIMUM_X86_ISA_LEVEL \ + (__X86_ISA_V1 + __X86_ISA_V2 + __X86_ISA_V3 + __X86_ISA_V4) + + +/* + * CPU Features that are hard coded as enabled depending on ISA build + * level. + * - Values > 0 features are always ENABLED if: + * Value >= MINIMUM_X86_ISA_LEVEL + */ + + +/* ISA level >= 4 guaranteed includes. */ +#define AVX512VL_X86_ISA_LEVEL 4 +#define AVX512BW_X86_ISA_LEVEL 4 + +/* ISA level >= 3 guaranteed includes. */ +#define AVX2_X86_ISA_LEVEL 3 +#define BMI2_X86_ISA_LEVEL 3 + +/* + * NB: This may not be fully assumable for ISA level >= 3. From + * looking over the architectures supported in cpu-features.h the + * following CPUs may have an issue with this being default set: + * - AMD Excavator + */ +#define AVX_Fast_Unaligned_Load_X86_ISA_LEVEL 3 + +/* + * KNL (the only cpu that sets this supported in cpu-features.h) + * builds with ISA V1 so this shouldn't harm any architectures. + */ +#define Prefer_No_VZEROUPPER_X86_ISA_LEVEL 3 + + +#endif diff --git a/sysdeps/x86_64/isa-default-impl.h b/sysdeps/x86_64/isa-default-impl.h new file mode 100644 index 0000000000..34634668e5 --- /dev/null +++ b/sysdeps/x86_64/isa-default-impl.h @@ -0,0 +1,49 @@ +/* Utility for including proper default function based on ISA level + Copyright (C) 2022 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include + +#ifndef DEFAULT_IMPL_V1 +# error "Must have at least ISA V1 Version" +#endif + +#ifndef DEFAULT_IMPL_V2 +# define DEFAULT_IMPL_V2 DEFAULT_IMPL_V1 +#endif + +#ifndef DEFAULT_IMPL_V3 +# define DEFAULT_IMPL_V3 DEFAULT_IMPL_V2 +#endif + +#ifndef DEFAULT_IMPL_V4 +# define DEFAULT_IMPL_V4 DEFAULT_IMPL_V3 +#endif + +#if MINIMUM_X86_ISA_LEVEL == 1 +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V1 +#elif MINIMUM_X86_ISA_LEVEL == 2 +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V2 +#elif MINIMUM_X86_ISA_LEVEL == 3 +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V3 +#elif MINIMUM_X86_ISA_LEVEL == 4 +# define ISA_DEFAULT_IMPL DEFAULT_IMPL_V4 +#else +# error "Unsupported ISA Level!" +#endif + +#include ISA_DEFAULT_IMPL From patchwork Wed Jun 22 18:11:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Noah Goldstein X-Patchwork-Id: 55291 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 824063831CB7 for ; Wed, 22 Jun 2022 18:12:54 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 824063831CB7 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1655921574; bh=v1p1dv9NH1xFd8Mr/wVGl3IK7G3r/OUJpO80Fj4WxfE=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=YJysJcusom+W5sbjIDTmpzrPfOw4vuTaqM2FfGVapApUeQNNhk1WtqwnKpYGA7u8O 8w5cGCDlwZMHUDhMxONz1wTDCva20RPhTpFS0xi11ls0m8osR7lO9CxA2AihnFIPOI ebUTD8c1GNAmrEELg8XEuBqAGS5U7b/K0WVliit0= X-Original-To: libc-alpha@sourceware.org Delivered-To: libc-alpha@sourceware.org Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by sourceware.org (Postfix) with ESMTPS id 091E138582BE for ; Wed, 22 Jun 2022 18:11:53 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 091E138582BE Received: by mail-pl1-x631.google.com with SMTP id jb13so2466993plb.9 for ; Wed, 22 Jun 2022 11:11:52 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v1p1dv9NH1xFd8Mr/wVGl3IK7G3r/OUJpO80Fj4WxfE=; b=R9Y9OjOaBcRiooLjE3HhyssSLV8Xwozy50oFiS6boR2ZEEFM39TrWEthUmKCOeE0d4 F/TVxtRMbUOLKB++30Qst9ndbMrHTY8Iy7zn9wWSw8bpa366mLLk4Oo3bu/O04NpQu6F EVht98Qu6XK6yUDywAEaF9skIgy/fT0mdxUAl4mmEJ39KlBhMxnGVNGWr4jJiIptk16n uyfbJBgk8tTNeR/CMltuqDvwtABrqve8q4CdZlup9gUPemGxUwuc3GFXh4G25h9f/Xjz 5H/lQbrydD93HR2ya20yyf0YP3yKdib8XZPWwFc7ZhJquZf8m/L3orOwkdGHzPyclWVA wVYA== X-Gm-Message-State: AJIora+2glisZ9hN00tMkI4eQspFAkG+3uDM9ILA7WWPLNGn6WfyepUZ BT0pIU0CMHv1GmsPMzpulxTxRn5oq2M= X-Google-Smtp-Source: AGRyM1tOyuOMqdaxLSvmDhxEah3/l9M/2ThffAWlY4P/nBxuXHbrggOqVmyudWzbK7Nx7jxnSDVFFg== X-Received: by 2002:a17:90b:3ec3:b0:1e8:844f:6d43 with SMTP id rm3-20020a17090b3ec300b001e8844f6d43mr50498912pjb.112.1655921510926; Wed, 22 Jun 2022 11:11:50 -0700 (PDT) Received: from noah-tgl.. ([2600:1010:b051:c9b1:28ad:233d:7d27:487a]) by smtp.gmail.com with ESMTPSA id f16-20020a17090a121000b001ec8c8300f8sm57715pja.52.2022.06.22.11.11.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jun 2022 11:11:50 -0700 (PDT) To: libc-alpha@sourceware.org Subject: [PATCH v9 2/2] x86: Add support for compiling {raw|w}memchr with high ISA level Date: Wed, 22 Jun 2022 11:11:41 -0700 Message-Id: <20220622181141.773121-2-goldstein.w.n@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220622181141.773121-1-goldstein.w.n@gmail.com> References: <20220621161821.2940071-1-goldstein.w.n@gmail.com> <20220622181141.773121-1-goldstein.w.n@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: libc-alpha@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Libc-alpha mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Noah Goldstein via Libc-alpha From: Noah Goldstein Reply-To: Noah Goldstein Errors-To: libc-alpha-bounces+patchwork=sourceware.org@sourceware.org Sender: "Libc-alpha" 1. Refactor files so that all implementations for in the multiarch directory. - Essentially moved sse2 {raw|w}memchr.S implementation to multiarch/{raw|w}memchr-sse2.S - The non-multiarch {raw|w}memchr.S file now only includes one of the implementations in the multiarch directory based on the compiled ISA level (only used for non-multiarch builds. Otherwise we go through the ifunc selector). 2. Add ISA level build guards to different implementations. - I.e memchr-avx2.S which is ISA level 3 will only build if compiled ISA level <= 3. Otherwise there is no reason to include it as we will always use one of the ISA level 4 implementations (memchr-evex{-rtm}.S). 3. Add new multiarch/rtld-{raw}memchr.S that just include the non-multiarch {raw}memchr.S which will in turn select the best implementation based on the compiled ISA level. 4. Refactor the ifunc selector and ifunc implementation list to use the ISA level aware wrapper macros that allow functions below the compiled ISA level (with a guranteed replacement) to be skipped. - Guranteed replacement essentially means that for any ISA level build there must be a function that the baseline of the ISA supports. So for {raw|w}memchr.S since there is not ISA level 2 function, the ISA level 2 build still includes the ISA level 1 (sse2) function. Once we reach the ISA level 3 build, however, {raw|w}memchr-avx2{-rtm}.S will always be sufficient so the ISA level 1 implementation ({raw|w}memchr-sse2.S) will not be built. Tested with and without multiarch on x86_64 for ISA levels: {generic, x86-64-v2, x86-64-v3, x86-64-v4} --- sysdeps/x86_64/memchr.S | 355 +---------------- sysdeps/x86_64/multiarch/ifunc-evex.h | 29 +- sysdeps/x86_64/multiarch/ifunc-impl-list.c | 72 ++-- sysdeps/x86_64/multiarch/memchr-avx2.S | 10 +- sysdeps/x86_64/multiarch/memchr-evex.S | 10 +- sysdeps/x86_64/multiarch/memchr-sse2.S | 368 +++++++++++++++++- sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S | 7 +- sysdeps/x86_64/multiarch/rawmemchr-avx2.S | 7 +- sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S | 8 +- sysdeps/x86_64/multiarch/rawmemchr-evex.S | 7 +- sysdeps/x86_64/multiarch/rawmemchr-sse2.S | 203 +++++++++- sysdeps/x86_64/multiarch/rtld-memchr.S | 18 + sysdeps/x86_64/multiarch/rtld-rawmemchr.S | 18 + sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S | 7 +- sysdeps/x86_64/multiarch/wmemchr-avx2.S | 7 +- sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S | 8 +- sysdeps/x86_64/multiarch/wmemchr-evex.S | 7 +- sysdeps/x86_64/multiarch/wmemchr-sse2.S | 27 +- sysdeps/x86_64/rawmemchr.S | 186 +-------- sysdeps/x86_64/wmemchr.S | 24 ++ 20 files changed, 770 insertions(+), 608 deletions(-) create mode 100644 sysdeps/x86_64/multiarch/rtld-memchr.S create mode 100644 sysdeps/x86_64/multiarch/rtld-rawmemchr.S create mode 100644 sysdeps/x86_64/wmemchr.S diff --git a/sysdeps/x86_64/memchr.S b/sysdeps/x86_64/memchr.S index a160fd9b00..018bb06f04 100644 --- a/sysdeps/x86_64/memchr.S +++ b/sysdeps/x86_64/memchr.S @@ -15,358 +15,13 @@ License along with the GNU C Library; if not, see . */ -#include +#define MEMCHR memchr -#ifdef USE_AS_WMEMCHR -# define MEMCHR wmemchr -# define PCMPEQ pcmpeqd -# define CHAR_PER_VEC 4 -#else -# define MEMCHR memchr -# define PCMPEQ pcmpeqb -# define CHAR_PER_VEC 16 -#endif +#define DEFAULT_IMPL_V1 "multiarch/memchr-sse2.S" +#define DEFAULT_IMPL_V3 "multiarch/memchr-avx2.S" +#define DEFAULT_IMPL_V4 "multiarch/memchr-evex.S" -/* fast SSE2 version with using pmaxub and 64 byte loop */ +#include "isa-default-impl.h" - .text -ENTRY(MEMCHR) - movd %esi, %xmm1 - mov %edi, %ecx - -#ifdef __ILP32__ - /* Clear the upper 32 bits. */ - movl %edx, %edx -#endif -#ifdef USE_AS_WMEMCHR - test %RDX_LP, %RDX_LP - jz L(return_null) -#else - punpcklbw %xmm1, %xmm1 - test %RDX_LP, %RDX_LP - jz L(return_null) - punpcklbw %xmm1, %xmm1 -#endif - - and $63, %ecx - pshufd $0, %xmm1, %xmm1 - - cmp $48, %ecx - ja L(crosscache) - - movdqu (%rdi), %xmm0 - PCMPEQ %xmm1, %xmm0 - pmovmskb %xmm0, %eax - test %eax, %eax - - jnz L(matches_1) - sub $CHAR_PER_VEC, %rdx - jbe L(return_null) - add $16, %rdi - and $15, %ecx - and $-16, %rdi -#ifdef USE_AS_WMEMCHR - shr $2, %ecx -#endif - add %rcx, %rdx - sub $(CHAR_PER_VEC * 4), %rdx - jbe L(exit_loop) - jmp L(loop_prolog) - - .p2align 4 -L(crosscache): - and $15, %ecx - and $-16, %rdi - movdqa (%rdi), %xmm0 - - PCMPEQ %xmm1, %xmm0 - /* Check if there is a match. */ - pmovmskb %xmm0, %eax - /* Remove the leading bytes. */ - sar %cl, %eax - test %eax, %eax - je L(unaligned_no_match) - /* Check which byte is a match. */ - bsf %eax, %eax -#ifdef USE_AS_WMEMCHR - mov %eax, %esi - shr $2, %esi - sub %rsi, %rdx -#else - sub %rax, %rdx -#endif - jbe L(return_null) - add %rdi, %rax - add %rcx, %rax - ret - - .p2align 4 -L(unaligned_no_match): - /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using - "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void - possible addition overflow. */ - neg %rcx - add $16, %rcx -#ifdef USE_AS_WMEMCHR - shr $2, %ecx -#endif - sub %rcx, %rdx - jbe L(return_null) - add $16, %rdi - sub $(CHAR_PER_VEC * 4), %rdx - jbe L(exit_loop) - - .p2align 4 -L(loop_prolog): - movdqa (%rdi), %xmm0 - PCMPEQ %xmm1, %xmm0 - pmovmskb %xmm0, %eax - test %eax, %eax - jnz L(matches) - - movdqa 16(%rdi), %xmm2 - PCMPEQ %xmm1, %xmm2 - pmovmskb %xmm2, %eax - test %eax, %eax - jnz L(matches16) - - movdqa 32(%rdi), %xmm3 - PCMPEQ %xmm1, %xmm3 - pmovmskb %xmm3, %eax - test %eax, %eax - jnz L(matches32) - - movdqa 48(%rdi), %xmm4 - PCMPEQ %xmm1, %xmm4 - add $64, %rdi - pmovmskb %xmm4, %eax - test %eax, %eax - jnz L(matches0) - - test $0x3f, %rdi - jz L(align64_loop) - - sub $(CHAR_PER_VEC * 4), %rdx - jbe L(exit_loop) - - movdqa (%rdi), %xmm0 - PCMPEQ %xmm1, %xmm0 - pmovmskb %xmm0, %eax - test %eax, %eax - jnz L(matches) - - movdqa 16(%rdi), %xmm2 - PCMPEQ %xmm1, %xmm2 - pmovmskb %xmm2, %eax - test %eax, %eax - jnz L(matches16) - - movdqa 32(%rdi), %xmm3 - PCMPEQ %xmm1, %xmm3 - pmovmskb %xmm3, %eax - test %eax, %eax - jnz L(matches32) - - movdqa 48(%rdi), %xmm3 - PCMPEQ %xmm1, %xmm3 - pmovmskb %xmm3, %eax - - add $64, %rdi - test %eax, %eax - jnz L(matches0) - - mov %rdi, %rcx - and $-64, %rdi - and $63, %ecx -#ifdef USE_AS_WMEMCHR - shr $2, %ecx -#endif - add %rcx, %rdx - - .p2align 4 -L(align64_loop): - sub $(CHAR_PER_VEC * 4), %rdx - jbe L(exit_loop) - movdqa (%rdi), %xmm0 - movdqa 16(%rdi), %xmm2 - movdqa 32(%rdi), %xmm3 - movdqa 48(%rdi), %xmm4 - - PCMPEQ %xmm1, %xmm0 - PCMPEQ %xmm1, %xmm2 - PCMPEQ %xmm1, %xmm3 - PCMPEQ %xmm1, %xmm4 - - pmaxub %xmm0, %xmm3 - pmaxub %xmm2, %xmm4 - pmaxub %xmm3, %xmm4 - pmovmskb %xmm4, %eax - - add $64, %rdi - - test %eax, %eax - jz L(align64_loop) - - sub $64, %rdi - - pmovmskb %xmm0, %eax - test %eax, %eax - jnz L(matches) - - pmovmskb %xmm2, %eax - test %eax, %eax - jnz L(matches16) - - movdqa 32(%rdi), %xmm3 - PCMPEQ %xmm1, %xmm3 - - PCMPEQ 48(%rdi), %xmm1 - pmovmskb %xmm3, %eax - test %eax, %eax - jnz L(matches32) - - pmovmskb %xmm1, %eax - bsf %eax, %eax - lea 48(%rdi, %rax), %rax - ret - - .p2align 4 -L(exit_loop): - add $(CHAR_PER_VEC * 2), %edx - jle L(exit_loop_32) - - movdqa (%rdi), %xmm0 - PCMPEQ %xmm1, %xmm0 - pmovmskb %xmm0, %eax - test %eax, %eax - jnz L(matches) - - movdqa 16(%rdi), %xmm2 - PCMPEQ %xmm1, %xmm2 - pmovmskb %xmm2, %eax - test %eax, %eax - jnz L(matches16) - - movdqa 32(%rdi), %xmm3 - PCMPEQ %xmm1, %xmm3 - pmovmskb %xmm3, %eax - test %eax, %eax - jnz L(matches32_1) - sub $CHAR_PER_VEC, %edx - jle L(return_null) - - PCMPEQ 48(%rdi), %xmm1 - pmovmskb %xmm1, %eax - test %eax, %eax - jnz L(matches48_1) - xor %eax, %eax - ret - - .p2align 4 -L(exit_loop_32): - add $(CHAR_PER_VEC * 2), %edx - movdqa (%rdi), %xmm0 - PCMPEQ %xmm1, %xmm0 - pmovmskb %xmm0, %eax - test %eax, %eax - jnz L(matches_1) - sub $CHAR_PER_VEC, %edx - jbe L(return_null) - - PCMPEQ 16(%rdi), %xmm1 - pmovmskb %xmm1, %eax - test %eax, %eax - jnz L(matches16_1) - xor %eax, %eax - ret - - .p2align 4 -L(matches0): - bsf %eax, %eax - lea -16(%rax, %rdi), %rax - ret - - .p2align 4 -L(matches): - bsf %eax, %eax - add %rdi, %rax - ret - - .p2align 4 -L(matches16): - bsf %eax, %eax - lea 16(%rax, %rdi), %rax - ret - - .p2align 4 -L(matches32): - bsf %eax, %eax - lea 32(%rax, %rdi), %rax - ret - - .p2align 4 -L(matches_1): - bsf %eax, %eax -#ifdef USE_AS_WMEMCHR - mov %eax, %esi - shr $2, %esi - sub %rsi, %rdx -#else - sub %rax, %rdx -#endif - jbe L(return_null) - add %rdi, %rax - ret - - .p2align 4 -L(matches16_1): - bsf %eax, %eax -#ifdef USE_AS_WMEMCHR - mov %eax, %esi - shr $2, %esi - sub %rsi, %rdx -#else - sub %rax, %rdx -#endif - jbe L(return_null) - lea 16(%rdi, %rax), %rax - ret - - .p2align 4 -L(matches32_1): - bsf %eax, %eax -#ifdef USE_AS_WMEMCHR - mov %eax, %esi - shr $2, %esi - sub %rsi, %rdx -#else - sub %rax, %rdx -#endif - jbe L(return_null) - lea 32(%rdi, %rax), %rax - ret - - .p2align 4 -L(matches48_1): - bsf %eax, %eax -#ifdef USE_AS_WMEMCHR - mov %eax, %esi - shr $2, %esi - sub %rsi, %rdx -#else - sub %rax, %rdx -#endif - jbe L(return_null) - lea 48(%rdi, %rax), %rax - ret - - .p2align 4 -L(return_null): - xor %eax, %eax - ret -END(MEMCHR) - -#ifndef USE_AS_WMEMCHR strong_alias (memchr, __memchr) libc_hidden_builtin_def(memchr) -#endif diff --git a/sysdeps/x86_64/multiarch/ifunc-evex.h b/sysdeps/x86_64/multiarch/ifunc-evex.h index b8f7a12ea2..856c6261f8 100644 --- a/sysdeps/x86_64/multiarch/ifunc-evex.h +++ b/sysdeps/x86_64/multiarch/ifunc-evex.h @@ -19,24 +19,28 @@ #include -extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden; -extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden; -extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden; extern __typeof (REDIRECT_NAME) OPTIMIZE (evex) attribute_hidden; extern __typeof (REDIRECT_NAME) OPTIMIZE (evex_rtm) attribute_hidden; +extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2) attribute_hidden; +extern __typeof (REDIRECT_NAME) OPTIMIZE (avx2_rtm) attribute_hidden; + +extern __typeof (REDIRECT_NAME) OPTIMIZE (sse2) attribute_hidden; static inline void * IFUNC_SELECTOR (void) { - const struct cpu_features* cpu_features = __get_cpu_features (); - - if (CPU_FEATURE_USABLE_P (cpu_features, AVX2) - && CPU_FEATURE_USABLE_P (cpu_features, BMI2) - && CPU_FEATURES_ARCH_P (cpu_features, AVX_Fast_Unaligned_Load)) + const struct cpu_features *cpu_features = __get_cpu_features (); + + /* NB: The X86_ISA_* feature check macros are evaluated at + compile time. */ + if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX2) + && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, BMI2) + && X86_ISA_CPU_FEATURES_ARCH_P (cpu_features, + AVX_Fast_Unaligned_Load)) { - if (CPU_FEATURE_USABLE_P (cpu_features, AVX512VL) - && CPU_FEATURE_USABLE_P (cpu_features, AVX512BW)) + if (X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512VL) + && X86_ISA_CPU_FEATURE_USABLE_P (cpu_features, AVX512BW)) { if (CPU_FEATURE_USABLE_P (cpu_features, RTM)) return OPTIMIZE (evex_rtm); @@ -47,9 +51,12 @@ IFUNC_SELECTOR (void) if (CPU_FEATURE_USABLE_P (cpu_features, RTM)) return OPTIMIZE (avx2_rtm); - if (!CPU_FEATURES_ARCH_P (cpu_features, Prefer_No_VZEROUPPER)) + if (X86_ISA_CPU_FEATURES_ARCH_P (cpu_features, + Prefer_No_VZEROUPPER)) return OPTIMIZE (avx2); } + /* This is unreachable (compile time checked) if ISA level >= 3 + so no need for a robust fallback here. */ return OPTIMIZE (sse2); } diff --git a/sysdeps/x86_64/multiarch/ifunc-impl-list.c b/sysdeps/x86_64/multiarch/ifunc-impl-list.c index 883362f63d..bf52cf96d0 100644 --- a/sysdeps/x86_64/multiarch/ifunc-impl-list.c +++ b/sysdeps/x86_64/multiarch/ifunc-impl-list.c @@ -25,7 +25,8 @@ /* Fill ARRAY of MAX elements with IFUNC implementations for function NAME supported on target machine and return the number of valid - entries. */ + entries. Each set of implementations for a given function is sorted in + descending order by ISA level. */ size_t __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, @@ -53,24 +54,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, /* Support sysdeps/x86_64/multiarch/memchr.c. */ IFUNC_IMPL (i, name, memchr, - IFUNC_IMPL_ADD (array, i, memchr, - CPU_FEATURE_USABLE (AVX2), - __memchr_avx2) - IFUNC_IMPL_ADD (array, i, memchr, - (CPU_FEATURE_USABLE (AVX2) - && CPU_FEATURE_USABLE (RTM)), - __memchr_avx2_rtm) - IFUNC_IMPL_ADD (array, i, memchr, + X86_IFUNC_IMPL_ADD_V4 (array, i, memchr, (CPU_FEATURE_USABLE (AVX512VL) && CPU_FEATURE_USABLE (AVX512BW) && CPU_FEATURE_USABLE (BMI2)), __memchr_evex) - IFUNC_IMPL_ADD (array, i, memchr, + X86_IFUNC_IMPL_ADD_V4 (array, i, memchr, (CPU_FEATURE_USABLE (AVX512VL) && CPU_FEATURE_USABLE (AVX512BW) && CPU_FEATURE_USABLE (BMI2)), __memchr_evex_rtm) - IFUNC_IMPL_ADD (array, i, memchr, 1, __memchr_sse2)) + X86_IFUNC_IMPL_ADD_V3 (array, i, memchr, + CPU_FEATURE_USABLE (AVX2), + __memchr_avx2) + X86_IFUNC_IMPL_ADD_V3 (array, i, memchr, + (CPU_FEATURE_USABLE (AVX2) + && CPU_FEATURE_USABLE (RTM)), + __memchr_avx2_rtm) + /* Can be lowered to V1 if a V2 implementation is added. */ + X86_IFUNC_IMPL_ADD_V2 (array, i, memchr, + 1, + __memchr_sse2)) /* Support sysdeps/x86_64/multiarch/memcmp.c. */ IFUNC_IMPL (i, name, memcmp, @@ -288,24 +292,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, /* Support sysdeps/x86_64/multiarch/rawmemchr.c. */ IFUNC_IMPL (i, name, rawmemchr, - IFUNC_IMPL_ADD (array, i, rawmemchr, - CPU_FEATURE_USABLE (AVX2), - __rawmemchr_avx2) - IFUNC_IMPL_ADD (array, i, rawmemchr, - (CPU_FEATURE_USABLE (AVX2) - && CPU_FEATURE_USABLE (RTM)), - __rawmemchr_avx2_rtm) - IFUNC_IMPL_ADD (array, i, rawmemchr, + X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr, (CPU_FEATURE_USABLE (AVX512VL) && CPU_FEATURE_USABLE (AVX512BW) && CPU_FEATURE_USABLE (BMI2)), __rawmemchr_evex) - IFUNC_IMPL_ADD (array, i, rawmemchr, + X86_IFUNC_IMPL_ADD_V4 (array, i, rawmemchr, (CPU_FEATURE_USABLE (AVX512VL) && CPU_FEATURE_USABLE (AVX512BW) && CPU_FEATURE_USABLE (BMI2)), __rawmemchr_evex_rtm) - IFUNC_IMPL_ADD (array, i, rawmemchr, 1, __rawmemchr_sse2)) + X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr, + CPU_FEATURE_USABLE (AVX2), + __rawmemchr_avx2) + X86_IFUNC_IMPL_ADD_V3 (array, i, rawmemchr, + (CPU_FEATURE_USABLE (AVX2) + && CPU_FEATURE_USABLE (RTM)), + __rawmemchr_avx2_rtm) + /* Can be lowered to V1 if a V2 implementation is added. */ + X86_IFUNC_IMPL_ADD_V2 (array, i, rawmemchr, + 1, + __rawmemchr_sse2)) /* Support sysdeps/x86_64/multiarch/strlen.c. */ IFUNC_IMPL (i, name, strlen, @@ -748,24 +755,27 @@ __libc_ifunc_impl_list (const char *name, struct libc_ifunc_impl *array, /* Support sysdeps/x86_64/multiarch/wmemchr.c. */ IFUNC_IMPL (i, name, wmemchr, - IFUNC_IMPL_ADD (array, i, wmemchr, - CPU_FEATURE_USABLE (AVX2), - __wmemchr_avx2) - IFUNC_IMPL_ADD (array, i, wmemchr, - (CPU_FEATURE_USABLE (AVX2) - && CPU_FEATURE_USABLE (RTM)), - __wmemchr_avx2_rtm) - IFUNC_IMPL_ADD (array, i, wmemchr, + X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr, (CPU_FEATURE_USABLE (AVX512VL) && CPU_FEATURE_USABLE (AVX512BW) && CPU_FEATURE_USABLE (BMI2)), __wmemchr_evex) - IFUNC_IMPL_ADD (array, i, wmemchr, + X86_IFUNC_IMPL_ADD_V4 (array, i, wmemchr, (CPU_FEATURE_USABLE (AVX512VL) && CPU_FEATURE_USABLE (AVX512BW) && CPU_FEATURE_USABLE (BMI2)), __wmemchr_evex_rtm) - IFUNC_IMPL_ADD (array, i, wmemchr, 1, __wmemchr_sse2)) + X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr, + CPU_FEATURE_USABLE (AVX2), + __wmemchr_avx2) + X86_IFUNC_IMPL_ADD_V3 (array, i, wmemchr, + (CPU_FEATURE_USABLE (AVX2) + && CPU_FEATURE_USABLE (RTM)), + __wmemchr_avx2_rtm) + /* Can be lowered to V1 if a V2 implementation is added. */ + X86_IFUNC_IMPL_ADD_V2 (array, i, wmemchr, + 1, + __wmemchr_sse2)) /* Support sysdeps/x86_64/multiarch/wmemcmp.c. */ IFUNC_IMPL (i, name, wmemcmp, diff --git a/sysdeps/x86_64/multiarch/memchr-avx2.S b/sysdeps/x86_64/multiarch/memchr-avx2.S index c5a256eb37..691662f0fb 100644 --- a/sysdeps/x86_64/multiarch/memchr-avx2.S +++ b/sysdeps/x86_64/multiarch/memchr-avx2.S @@ -16,7 +16,15 @@ License along with the GNU C Library; if not, see . */ -#if IS_IN (libc) +#include + +#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL +# error "Multiarch build should never default include!" +#endif + +#if (MINIMUM_X86_ISA_LEVEL <= 3 && IS_IN (libc)) \ + || defined ISA_DEFAULT_IMPL + # include diff --git a/sysdeps/x86_64/multiarch/memchr-evex.S b/sysdeps/x86_64/multiarch/memchr-evex.S index 0fd11b7632..10ed0434ae 100644 --- a/sysdeps/x86_64/multiarch/memchr-evex.S +++ b/sysdeps/x86_64/multiarch/memchr-evex.S @@ -16,7 +16,15 @@ License along with the GNU C Library; if not, see . */ -#if IS_IN (libc) +#include + +#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL +# error "Multiarch build should never default include!" +#endif + +#if (MINIMUM_X86_ISA_LEVEL <= 4 && IS_IN (libc)) \ + || defined ISA_DEFAULT_IMPL + # include diff --git a/sysdeps/x86_64/multiarch/memchr-sse2.S b/sysdeps/x86_64/multiarch/memchr-sse2.S index 2c6fdd41d6..acd5c15e22 100644 --- a/sysdeps/x86_64/multiarch/memchr-sse2.S +++ b/sysdeps/x86_64/multiarch/memchr-sse2.S @@ -16,13 +16,367 @@ License along with the GNU C Library; if not, see . */ -#if IS_IN (libc) -# define memchr __memchr_sse2 +#include -# undef strong_alias -# define strong_alias(memchr, __memchr) -# undef libc_hidden_builtin_def -# define libc_hidden_builtin_def(memchr) +#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL +# error "Multiarch build should never default include!" #endif -#include "../memchr.S" +/* __X86_ISA_LEVEL <= 2 because there is no V2 implementation so we + need this to build for ISA V2 builds. */ +#if (MINIMUM_X86_ISA_LEVEL <= 2 && IS_IN (libc)) \ + || defined ISA_DEFAULT_IMPL + + +# include + +# ifndef MEMCHR +# define MEMCHR __memchr_sse2 +# endif +# ifdef USE_AS_WMEMCHR +# define PCMPEQ pcmpeqd +# define CHAR_PER_VEC 4 +# else +# define PCMPEQ pcmpeqb +# define CHAR_PER_VEC 16 +# endif + +/* fast SSE2 version with using pmaxub and 64 byte loop */ + + .text +ENTRY(MEMCHR) + movd %esi, %xmm1 + mov %edi, %ecx + +# ifdef __ILP32__ + /* Clear the upper 32 bits. */ + movl %edx, %edx +# endif +# ifdef USE_AS_WMEMCHR + test %RDX_LP, %RDX_LP + jz L(return_null) +# else + punpcklbw %xmm1, %xmm1 + test %RDX_LP, %RDX_LP + jz L(return_null) + punpcklbw %xmm1, %xmm1 +# endif + + and $63, %ecx + pshufd $0, %xmm1, %xmm1 + + cmp $48, %ecx + ja L(crosscache) + + movdqu (%rdi), %xmm0 + PCMPEQ %xmm1, %xmm0 + pmovmskb %xmm0, %eax + test %eax, %eax + + jnz L(matches_1) + sub $CHAR_PER_VEC, %rdx + jbe L(return_null) + add $16, %rdi + and $15, %ecx + and $-16, %rdi +# ifdef USE_AS_WMEMCHR + shr $2, %ecx +# endif + add %rcx, %rdx + sub $(CHAR_PER_VEC * 4), %rdx + jbe L(exit_loop) + jmp L(loop_prolog) + + .p2align 4 +L(crosscache): + and $15, %ecx + and $-16, %rdi + movdqa (%rdi), %xmm0 + + PCMPEQ %xmm1, %xmm0 + /* Check if there is a match. */ + pmovmskb %xmm0, %eax + /* Remove the leading bytes. */ + sar %cl, %eax + test %eax, %eax + je L(unaligned_no_match) + /* Check which byte is a match. */ + bsf %eax, %eax +# ifdef USE_AS_WMEMCHR + mov %eax, %esi + shr $2, %esi + sub %rsi, %rdx +# else + sub %rax, %rdx +# endif + jbe L(return_null) + add %rdi, %rax + add %rcx, %rax + ret + + .p2align 4 +L(unaligned_no_match): + /* "rcx" is less than 16. Calculate "rdx + rcx - 16" by using + "rdx - (16 - rcx)" instead of "(rdx + rcx) - 16" to void + possible addition overflow. */ + neg %rcx + add $16, %rcx +# ifdef USE_AS_WMEMCHR + shr $2, %ecx +# endif + sub %rcx, %rdx + jbe L(return_null) + add $16, %rdi + sub $(CHAR_PER_VEC * 4), %rdx + jbe L(exit_loop) + + .p2align 4 +L(loop_prolog): + movdqa (%rdi), %xmm0 + PCMPEQ %xmm1, %xmm0 + pmovmskb %xmm0, %eax + test %eax, %eax + jnz L(matches) + + movdqa 16(%rdi), %xmm2 + PCMPEQ %xmm1, %xmm2 + pmovmskb %xmm2, %eax + test %eax, %eax + jnz L(matches16) + + movdqa 32(%rdi), %xmm3 + PCMPEQ %xmm1, %xmm3 + pmovmskb %xmm3, %eax + test %eax, %eax + jnz L(matches32) + + movdqa 48(%rdi), %xmm4 + PCMPEQ %xmm1, %xmm4 + add $64, %rdi + pmovmskb %xmm4, %eax + test %eax, %eax + jnz L(matches0) + + test $0x3f, %rdi + jz L(align64_loop) + + sub $(CHAR_PER_VEC * 4), %rdx + jbe L(exit_loop) + + movdqa (%rdi), %xmm0 + PCMPEQ %xmm1, %xmm0 + pmovmskb %xmm0, %eax + test %eax, %eax + jnz L(matches) + + movdqa 16(%rdi), %xmm2 + PCMPEQ %xmm1, %xmm2 + pmovmskb %xmm2, %eax + test %eax, %eax + jnz L(matches16) + + movdqa 32(%rdi), %xmm3 + PCMPEQ %xmm1, %xmm3 + pmovmskb %xmm3, %eax + test %eax, %eax + jnz L(matches32) + + movdqa 48(%rdi), %xmm3 + PCMPEQ %xmm1, %xmm3 + pmovmskb %xmm3, %eax + + add $64, %rdi + test %eax, %eax + jnz L(matches0) + + mov %rdi, %rcx + and $-64, %rdi + and $63, %ecx +# ifdef USE_AS_WMEMCHR + shr $2, %ecx +# endif + add %rcx, %rdx + + .p2align 4 +L(align64_loop): + sub $(CHAR_PER_VEC * 4), %rdx + jbe L(exit_loop) + movdqa (%rdi), %xmm0 + movdqa 16(%rdi), %xmm2 + movdqa 32(%rdi), %xmm3 + movdqa 48(%rdi), %xmm4 + + PCMPEQ %xmm1, %xmm0 + PCMPEQ %xmm1, %xmm2 + PCMPEQ %xmm1, %xmm3 + PCMPEQ %xmm1, %xmm4 + + pmaxub %xmm0, %xmm3 + pmaxub %xmm2, %xmm4 + pmaxub %xmm3, %xmm4 + pmovmskb %xmm4, %eax + + add $64, %rdi + + test %eax, %eax + jz L(align64_loop) + + sub $64, %rdi + + pmovmskb %xmm0, %eax + test %eax, %eax + jnz L(matches) + + pmovmskb %xmm2, %eax + test %eax, %eax + jnz L(matches16) + + movdqa 32(%rdi), %xmm3 + PCMPEQ %xmm1, %xmm3 + + PCMPEQ 48(%rdi), %xmm1 + pmovmskb %xmm3, %eax + test %eax, %eax + jnz L(matches32) + + pmovmskb %xmm1, %eax + bsf %eax, %eax + lea 48(%rdi, %rax), %rax + ret + + .p2align 4 +L(exit_loop): + add $(CHAR_PER_VEC * 2), %edx + jle L(exit_loop_32) + + movdqa (%rdi), %xmm0 + PCMPEQ %xmm1, %xmm0 + pmovmskb %xmm0, %eax + test %eax, %eax + jnz L(matches) + + movdqa 16(%rdi), %xmm2 + PCMPEQ %xmm1, %xmm2 + pmovmskb %xmm2, %eax + test %eax, %eax + jnz L(matches16) + + movdqa 32(%rdi), %xmm3 + PCMPEQ %xmm1, %xmm3 + pmovmskb %xmm3, %eax + test %eax, %eax + jnz L(matches32_1) + sub $CHAR_PER_VEC, %edx + jle L(return_null) + + PCMPEQ 48(%rdi), %xmm1 + pmovmskb %xmm1, %eax + test %eax, %eax + jnz L(matches48_1) + xor %eax, %eax + ret + + .p2align 4 +L(exit_loop_32): + add $(CHAR_PER_VEC * 2), %edx + movdqa (%rdi), %xmm0 + PCMPEQ %xmm1, %xmm0 + pmovmskb %xmm0, %eax + test %eax, %eax + jnz L(matches_1) + sub $CHAR_PER_VEC, %edx + jbe L(return_null) + + PCMPEQ 16(%rdi), %xmm1 + pmovmskb %xmm1, %eax + test %eax, %eax + jnz L(matches16_1) + xor %eax, %eax + ret + + .p2align 4 +L(matches0): + bsf %eax, %eax + lea -16(%rax, %rdi), %rax + ret + + .p2align 4 +L(matches): + bsf %eax, %eax + add %rdi, %rax + ret + + .p2align 4 +L(matches16): + bsf %eax, %eax + lea 16(%rax, %rdi), %rax + ret + + .p2align 4 +L(matches32): + bsf %eax, %eax + lea 32(%rax, %rdi), %rax + ret + + .p2align 4 +L(matches_1): + bsf %eax, %eax +# ifdef USE_AS_WMEMCHR + mov %eax, %esi + shr $2, %esi + sub %rsi, %rdx +# else + sub %rax, %rdx +# endif + jbe L(return_null) + add %rdi, %rax + ret + + .p2align 4 +L(matches16_1): + bsf %eax, %eax +# ifdef USE_AS_WMEMCHR + mov %eax, %esi + shr $2, %esi + sub %rsi, %rdx +# else + sub %rax, %rdx +# endif + jbe L(return_null) + lea 16(%rdi, %rax), %rax + ret + + .p2align 4 +L(matches32_1): + bsf %eax, %eax +# ifdef USE_AS_WMEMCHR + mov %eax, %esi + shr $2, %esi + sub %rsi, %rdx +# else + sub %rax, %rdx +# endif + jbe L(return_null) + lea 32(%rdi, %rax), %rax + ret + + .p2align 4 +L(matches48_1): + bsf %eax, %eax +# ifdef USE_AS_WMEMCHR + mov %eax, %esi + shr $2, %esi + sub %rsi, %rdx +# else + sub %rax, %rdx +# endif + jbe L(return_null) + lea 48(%rdi, %rax), %rax + ret + + .p2align 4 +L(return_null): + xor %eax, %eax + ret +END(MEMCHR) +#endif diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S index acc5f6e2fb..5c1dcd3ca7 100644 --- a/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S +++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2-rtm.S @@ -1,4 +1,7 @@ -#define MEMCHR __rawmemchr_avx2_rtm -#define USE_AS_RAWMEMCHR 1 +#ifndef RAWMEMCHR +# define RAWMEMCHR __rawmemchr_avx2_rtm +#endif +#define USE_AS_RAWMEMCHR 1 +#define MEMCHR RAWMEMCHR #include "memchr-avx2-rtm.S" diff --git a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S index 128f9ea637..d6bff28757 100644 --- a/sysdeps/x86_64/multiarch/rawmemchr-avx2.S +++ b/sysdeps/x86_64/multiarch/rawmemchr-avx2.S @@ -1,4 +1,7 @@ -#define MEMCHR __rawmemchr_avx2 -#define USE_AS_RAWMEMCHR 1 +#ifndef RAWMEMCHR +# define RAWMEMCHR __rawmemchr_avx2 +#endif +#define USE_AS_RAWMEMCHR 1 +#define MEMCHR RAWMEMCHR #include "memchr-avx2.S" diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S index deda1ca395..8ff7f27c9c 100644 --- a/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S +++ b/sysdeps/x86_64/multiarch/rawmemchr-evex-rtm.S @@ -1,3 +1,7 @@ -#define MEMCHR __rawmemchr_evex_rtm -#define USE_AS_RAWMEMCHR 1 +#ifndef RAWMEMCHR +# define RAWMEMCHR __rawmemchr_evex_rtm +#endif +#define USE_AS_RAWMEMCHR 1 +#define MEMCHR RAWMEMCHR + #include "memchr-evex-rtm.S" diff --git a/sysdeps/x86_64/multiarch/rawmemchr-evex.S b/sysdeps/x86_64/multiarch/rawmemchr-evex.S index ec942b77ba..dc1c450699 100644 --- a/sysdeps/x86_64/multiarch/rawmemchr-evex.S +++ b/sysdeps/x86_64/multiarch/rawmemchr-evex.S @@ -1,4 +1,7 @@ -#define MEMCHR __rawmemchr_evex -#define USE_AS_RAWMEMCHR 1 +#ifndef RAWMEMCHR +# define RAWMEMCHR __rawmemchr_evex +#endif +#define USE_AS_RAWMEMCHR 1 +#define MEMCHR RAWMEMCHR #include "memchr-evex.S" diff --git a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S index 3841c14c34..73f4fa9589 100644 --- a/sysdeps/x86_64/multiarch/rawmemchr-sse2.S +++ b/sysdeps/x86_64/multiarch/rawmemchr-sse2.S @@ -16,14 +16,199 @@ License along with the GNU C Library; if not, see . */ -/* Define multiple versions only for the definition in libc. */ -#if IS_IN (libc) -# define __rawmemchr __rawmemchr_sse2 - -# undef weak_alias -# define weak_alias(__rawmemchr, rawmemchr) -# undef libc_hidden_def -# define libc_hidden_def(__rawmemchr) +#include + +#if defined IS_MULTIARCH && defined ISA_DEFAULT_IMPL +# error "Multiarch build should never default include!" #endif -#include "../rawmemchr.S" +/* __X86_ISA_LEVEL <= 2 because there is no V2 implementation so we + need this to build for ISA V2 builds. */ +#if (MINIMUM_X86_ISA_LEVEL <= 2 && IS_IN (libc)) \ + || defined ISA_DEFAULT_IMPL + + +# include + +# ifndef RAWMEMCHR +# define RAWMEMCHR __rawmemchr_sse2 +# endif + + .text +ENTRY (RAWMEMCHR) + movd %rsi, %xmm1 + mov %rdi, %rcx + + punpcklbw %xmm1, %xmm1 + punpcklbw %xmm1, %xmm1 + + and $63, %rcx + pshufd $0, %xmm1, %xmm1 + + cmp $48, %rcx + ja L(crosscache) + + movdqu (%rdi), %xmm0 + pcmpeqb %xmm1, %xmm0 +/* Check if there is a match. */ + pmovmskb %xmm0, %eax + test %eax, %eax + + jnz L(matches) + add $16, %rdi + and $-16, %rdi + jmp L(loop_prolog) + + .p2align 4 +L(crosscache): + and $15, %rcx + and $-16, %rdi + movdqa (%rdi), %xmm0 + + pcmpeqb %xmm1, %xmm0 +/* Check if there is a match. */ + pmovmskb %xmm0, %eax +/* Remove the leading bytes. */ + sar %cl, %eax + test %eax, %eax + je L(unaligned_no_match) +/* Check which byte is a match. */ + bsf %eax, %eax + + add %rdi, %rax + add %rcx, %rax + ret + + .p2align 4 +L(unaligned_no_match): + add $16, %rdi + + .p2align 4 +L(loop_prolog): + movdqa (%rdi), %xmm0 + pcmpeqb %xmm1, %xmm0 + pmovmskb %xmm0, %eax + test %eax, %eax + jnz L(matches) + + movdqa 16(%rdi), %xmm2 + pcmpeqb %xmm1, %xmm2 + pmovmskb %xmm2, %eax + test %eax, %eax + jnz L(matches16) + + movdqa 32(%rdi), %xmm3 + pcmpeqb %xmm1, %xmm3 + pmovmskb %xmm3, %eax + test %eax, %eax + jnz L(matches32) + + movdqa 48(%rdi), %xmm4 + pcmpeqb %xmm1, %xmm4 + add $64, %rdi + pmovmskb %xmm4, %eax + test %eax, %eax + jnz L(matches0) + + test $0x3f, %rdi + jz L(align64_loop) + + movdqa (%rdi), %xmm0 + pcmpeqb %xmm1, %xmm0 + pmovmskb %xmm0, %eax + test %eax, %eax + jnz L(matches) + + movdqa 16(%rdi), %xmm2 + pcmpeqb %xmm1, %xmm2 + pmovmskb %xmm2, %eax + test %eax, %eax + jnz L(matches16) + + movdqa 32(%rdi), %xmm3 + pcmpeqb %xmm1, %xmm3 + pmovmskb %xmm3, %eax + test %eax, %eax + jnz L(matches32) + + movdqa 48(%rdi), %xmm3 + pcmpeqb %xmm1, %xmm3 + pmovmskb %xmm3, %eax + + add $64, %rdi + test %eax, %eax + jnz L(matches0) + + and $-64, %rdi + + .p2align 4 +L(align64_loop): + movdqa (%rdi), %xmm0 + movdqa 16(%rdi), %xmm2 + movdqa 32(%rdi), %xmm3 + movdqa 48(%rdi), %xmm4 + + pcmpeqb %xmm1, %xmm0 + pcmpeqb %xmm1, %xmm2 + pcmpeqb %xmm1, %xmm3 + pcmpeqb %xmm1, %xmm4 + + pmaxub %xmm0, %xmm3 + pmaxub %xmm2, %xmm4 + pmaxub %xmm3, %xmm4 + pmovmskb %xmm4, %eax + + add $64, %rdi + + test %eax, %eax + jz L(align64_loop) + + sub $64, %rdi + + pmovmskb %xmm0, %eax + test %eax, %eax + jnz L(matches) + + pmovmskb %xmm2, %eax + test %eax, %eax + jnz L(matches16) + + movdqa 32(%rdi), %xmm3 + pcmpeqb %xmm1, %xmm3 + + pcmpeqb 48(%rdi), %xmm1 + pmovmskb %xmm3, %eax + test %eax, %eax + jnz L(matches32) + + pmovmskb %xmm1, %eax + bsf %eax, %eax + lea 48(%rdi, %rax), %rax + ret + + .p2align 4 +L(matches0): + bsf %eax, %eax + lea -16(%rax, %rdi), %rax + ret + + .p2align 4 +L(matches): + bsf %eax, %eax + add %rdi, %rax + ret + + .p2align 4 +L(matches16): + bsf %eax, %eax + lea 16(%rax, %rdi), %rax + ret + + .p2align 4 +L(matches32): + bsf %eax, %eax + lea 32(%rax, %rdi), %rax + ret + +END (RAWMEMCHR) +#endif diff --git a/sysdeps/x86_64/multiarch/rtld-memchr.S b/sysdeps/x86_64/multiarch/rtld-memchr.S new file mode 100644 index 0000000000..a14b192bed --- /dev/null +++ b/sysdeps/x86_64/multiarch/rtld-memchr.S @@ -0,0 +1,18 @@ +/* Copyright (C) 2022 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include "../memchr.S" diff --git a/sysdeps/x86_64/multiarch/rtld-rawmemchr.S b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S new file mode 100644 index 0000000000..5d4110a052 --- /dev/null +++ b/sysdeps/x86_64/multiarch/rtld-rawmemchr.S @@ -0,0 +1,18 @@ +/* Copyright (C) 2022 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#include "../rawmemchr.S" diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S index 58ed21db01..2a1cff5b05 100644 --- a/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S +++ b/sysdeps/x86_64/multiarch/wmemchr-avx2-rtm.S @@ -1,4 +1,7 @@ -#define MEMCHR __wmemchr_avx2_rtm -#define USE_AS_WMEMCHR 1 +#ifndef WMEMCHR +# define WMEMCHR __wmemchr_avx2_rtm +#endif +#define USE_AS_WMEMCHR 1 +#define MEMCHR WMEMCHR #include "memchr-avx2-rtm.S" diff --git a/sysdeps/x86_64/multiarch/wmemchr-avx2.S b/sysdeps/x86_64/multiarch/wmemchr-avx2.S index 282854f1a1..2bf93fd84b 100644 --- a/sysdeps/x86_64/multiarch/wmemchr-avx2.S +++ b/sysdeps/x86_64/multiarch/wmemchr-avx2.S @@ -1,4 +1,7 @@ -#define MEMCHR __wmemchr_avx2 -#define USE_AS_WMEMCHR 1 +#ifndef WMEMCHR +# define WMEMCHR __wmemchr_avx2 +#endif +#define USE_AS_WMEMCHR 1 +#define MEMCHR WMEMCHR #include "memchr-avx2.S" diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S index a346cd35a1..c67309e8a1 100644 --- a/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S +++ b/sysdeps/x86_64/multiarch/wmemchr-evex-rtm.S @@ -1,3 +1,7 @@ -#define MEMCHR __wmemchr_evex_rtm -#define USE_AS_WMEMCHR 1 +#ifndef WMEMCHR +# define WMEMCHR __wmemchr_evex_rtm +#endif +#define USE_AS_WMEMCHR 1 +#define MEMCHR WMEMCHR + #include "memchr-evex-rtm.S" diff --git a/sysdeps/x86_64/multiarch/wmemchr-evex.S b/sysdeps/x86_64/multiarch/wmemchr-evex.S index 06cd0f9f5a..5512d5cdc3 100644 --- a/sysdeps/x86_64/multiarch/wmemchr-evex.S +++ b/sysdeps/x86_64/multiarch/wmemchr-evex.S @@ -1,4 +1,7 @@ -#define MEMCHR __wmemchr_evex -#define USE_AS_WMEMCHR 1 +#ifndef WMEMCHR +# define WMEMCHR __wmemchr_evex +#endif +#define USE_AS_WMEMCHR 1 +#define MEMCHR WMEMCHR #include "memchr-evex.S" diff --git a/sysdeps/x86_64/multiarch/wmemchr-sse2.S b/sysdeps/x86_64/multiarch/wmemchr-sse2.S index 70a965d552..3081fb6821 100644 --- a/sysdeps/x86_64/multiarch/wmemchr-sse2.S +++ b/sysdeps/x86_64/multiarch/wmemchr-sse2.S @@ -1,4 +1,25 @@ -#define USE_AS_WMEMCHR 1 -#define wmemchr __wmemchr_sse2 +/* wmemchr optimized with SSE2 + Copyright (C) 2022 Free Software Foundation, Inc. + This file is part of the GNU C Library. -#include "../memchr.S" + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#ifndef WMEMCHR +# define WMEMCHR __wmemchr_sse2 +#endif +#define USE_AS_WMEMCHR 1 +#define MEMCHR WMEMCHR + +#include "memchr-sse2.S" diff --git a/sysdeps/x86_64/rawmemchr.S b/sysdeps/x86_64/rawmemchr.S index 4c1a3383b9..e401a2ac53 100644 --- a/sysdeps/x86_64/rawmemchr.S +++ b/sysdeps/x86_64/rawmemchr.S @@ -17,185 +17,13 @@ License along with the GNU C Library; if not, see . */ -#include +#define RAWMEMCHR rawmemchr - .text -ENTRY (__rawmemchr) - movd %rsi, %xmm1 - mov %rdi, %rcx +#define DEFAULT_IMPL_V1 "multiarch/rawmemchr-sse2.S" +#define DEFAULT_IMPL_V3 "multiarch/rawmemchr-avx2.S" +#define DEFAULT_IMPL_V4 "multiarch/rawmemchr-evex.S" - punpcklbw %xmm1, %xmm1 - punpcklbw %xmm1, %xmm1 +#include "isa-default-impl.h" - and $63, %rcx - pshufd $0, %xmm1, %xmm1 - - cmp $48, %rcx - ja L(crosscache) - - movdqu (%rdi), %xmm0 - pcmpeqb %xmm1, %xmm0 -/* Check if there is a match. */ - pmovmskb %xmm0, %eax - test %eax, %eax - - jnz L(matches) - add $16, %rdi - and $-16, %rdi - jmp L(loop_prolog) - - .p2align 4 -L(crosscache): - and $15, %rcx - and $-16, %rdi - movdqa (%rdi), %xmm0 - - pcmpeqb %xmm1, %xmm0 -/* Check if there is a match. */ - pmovmskb %xmm0, %eax -/* Remove the leading bytes. */ - sar %cl, %eax - test %eax, %eax - je L(unaligned_no_match) -/* Check which byte is a match. */ - bsf %eax, %eax - - add %rdi, %rax - add %rcx, %rax - ret - - .p2align 4 -L(unaligned_no_match): - add $16, %rdi - - .p2align 4 -L(loop_prolog): - movdqa (%rdi), %xmm0 - pcmpeqb %xmm1, %xmm0 - pmovmskb %xmm0, %eax - test %eax, %eax - jnz L(matches) - - movdqa 16(%rdi), %xmm2 - pcmpeqb %xmm1, %xmm2 - pmovmskb %xmm2, %eax - test %eax, %eax - jnz L(matches16) - - movdqa 32(%rdi), %xmm3 - pcmpeqb %xmm1, %xmm3 - pmovmskb %xmm3, %eax - test %eax, %eax - jnz L(matches32) - - movdqa 48(%rdi), %xmm4 - pcmpeqb %xmm1, %xmm4 - add $64, %rdi - pmovmskb %xmm4, %eax - test %eax, %eax - jnz L(matches0) - - test $0x3f, %rdi - jz L(align64_loop) - - movdqa (%rdi), %xmm0 - pcmpeqb %xmm1, %xmm0 - pmovmskb %xmm0, %eax - test %eax, %eax - jnz L(matches) - - movdqa 16(%rdi), %xmm2 - pcmpeqb %xmm1, %xmm2 - pmovmskb %xmm2, %eax - test %eax, %eax - jnz L(matches16) - - movdqa 32(%rdi), %xmm3 - pcmpeqb %xmm1, %xmm3 - pmovmskb %xmm3, %eax - test %eax, %eax - jnz L(matches32) - - movdqa 48(%rdi), %xmm3 - pcmpeqb %xmm1, %xmm3 - pmovmskb %xmm3, %eax - - add $64, %rdi - test %eax, %eax - jnz L(matches0) - - and $-64, %rdi - - .p2align 4 -L(align64_loop): - movdqa (%rdi), %xmm0 - movdqa 16(%rdi), %xmm2 - movdqa 32(%rdi), %xmm3 - movdqa 48(%rdi), %xmm4 - - pcmpeqb %xmm1, %xmm0 - pcmpeqb %xmm1, %xmm2 - pcmpeqb %xmm1, %xmm3 - pcmpeqb %xmm1, %xmm4 - - pmaxub %xmm0, %xmm3 - pmaxub %xmm2, %xmm4 - pmaxub %xmm3, %xmm4 - pmovmskb %xmm4, %eax - - add $64, %rdi - - test %eax, %eax - jz L(align64_loop) - - sub $64, %rdi - - pmovmskb %xmm0, %eax - test %eax, %eax - jnz L(matches) - - pmovmskb %xmm2, %eax - test %eax, %eax - jnz L(matches16) - - movdqa 32(%rdi), %xmm3 - pcmpeqb %xmm1, %xmm3 - - pcmpeqb 48(%rdi), %xmm1 - pmovmskb %xmm3, %eax - test %eax, %eax - jnz L(matches32) - - pmovmskb %xmm1, %eax - bsf %eax, %eax - lea 48(%rdi, %rax), %rax - ret - - .p2align 4 -L(matches0): - bsf %eax, %eax - lea -16(%rax, %rdi), %rax - ret - - .p2align 4 -L(matches): - bsf %eax, %eax - add %rdi, %rax - ret - - .p2align 4 -L(matches16): - bsf %eax, %eax - lea 16(%rax, %rdi), %rax - ret - - .p2align 4 -L(matches32): - bsf %eax, %eax - lea 32(%rax, %rdi), %rax - ret - -END (__rawmemchr) - -weak_alias (__rawmemchr, rawmemchr) -libc_hidden_builtin_def (__rawmemchr) +strong_alias (rawmemchr, __rawmemchr) +libc_hidden_builtin_def (rawmemchr) diff --git a/sysdeps/x86_64/wmemchr.S b/sysdeps/x86_64/wmemchr.S new file mode 100644 index 0000000000..dd0490f86b --- /dev/null +++ b/sysdeps/x86_64/wmemchr.S @@ -0,0 +1,24 @@ +/* Copyright (C) 2011-2022 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, see + . */ + +#define WMEMCHR wmemchr + +#define DEFAULT_IMPL_V1 "multiarch/wmemchr-sse2.S" +#define DEFAULT_IMPL_V3 "multiarch/wmemchr-avx2.S" +#define DEFAULT_IMPL_V4 "multiarch/wmemchr-evex.S" + +#include "isa-default-impl.h"