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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id s11-20020aa7d78b000000b0042bca34bd15sm9067640edq.95.2022.06.15.04.47.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jun 2022 04:47:31 -0700 (PDT) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Andrew Waterman , Philipp Tomsich , Christoph Muellner Subject: [PATCH v2 1/2] riscv-cores.def: Fix description of RISCV_CORE() macro Date: Wed, 15 Jun 2022 13:47:28 +0200 Message-Id: <20220615114729.826142-1-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.35.3 MIME-Version: 1.0 X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Christoph Müllner The current description of RISCV_CORE() does not match the implementation. This commit provides a fix for that. gcc/ChangeLog: * config/riscv/riscv-cores.def: Fix comment. Signed-off-by: Christoph Müllner --- gcc/config/riscv/riscv-cores.def | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index ecb5e213d98..60bcadbb034 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -21,15 +21,13 @@ Before using #include to read this file, define a macro: - RISCV_CORE(CORE_NAME, ARCH, MICRO_ARCH, TUNE_INFO) + RISCV_CORE(CORE_NAME, ARCH, TUNE_INFO) The CORE_NAME is the name of the core, represented as a string. - The ARCH is the default arch of the core, represented as a string, - can be NULL if no default arch. - The MICRO_ARCH is the name of the core for which scheduling decisions - will be made, represented as an identifier. - The TUNE_INFO is the detail cost model for this core, represented as an - identifier, reference to riscv-tunes.def. */ + The ARCH is a string describing the supported RISC-V ISA (e.g. "rv32i" + or "rv64gc_zifencei"). + The TUNE_INFO is a string that references the detail tuning information + for this core (refer to riscv_tune_info_table for possible values). */ RISCV_CORE("sifive-e20", "rv32imc", "rocket") RISCV_CORE("sifive-e21", "rv32imac", "rocket") From patchwork Wed Jun 15 11:47:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Christoph_M=C3=BCllner?= X-Patchwork-Id: 55099 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 238713838643 for ; Wed, 15 Jun 2022 11:48:20 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by sourceware.org (Postfix) with ESMTPS id 8B5293857371 for ; Wed, 15 Jun 2022 11:47:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 8B5293857371 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-ej1-x635.google.com with SMTP id o7so22703996eja.1 for ; Wed, 15 Jun 2022 04:47:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=zI39QhmEIH4mKiC+oNjWh2FkLVzPpvVqaXz+bwbd8Ew=; b=kTwzB5pFu672DCHE2avqeFxseSnv8mu7G1pEasE1jNn/ZJBtMc6BxF8gjlVu8YHioC xakdpZ1KSYufHJgiUSdCb8yK5Y0GHcpZP86yI12A8mmK1Pz8ToKOGMddhyMJZ+9ovGP9 IQKlFBO31/1hzjn4fwxpFu6Xda2NG++zB+mSBOfNJw08/j0v0OOh0DbXURsncr1QdfZk /TpJshwNl7fsZdxr/58FpcVguy2uhHd/2+zbiL71NUBYM5L4bWnRC8uvJFOvCm9KmK/i eEvznp/XxmjRkzh1AzWrdJiOck8vBp6H6WT4wV0ASYM7Sv+UiI1WaNJzApprzZXHZ5wi DyUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zI39QhmEIH4mKiC+oNjWh2FkLVzPpvVqaXz+bwbd8Ew=; b=PXCjWaC1ubZ1m/Ar8RTbcD3YGqNoXh261ZqDRT+/vHpUGKvzL8zNQAbYMetRaG7h9h szrp36kAHKlOQP8ngcLS+vEI9jKwN0vf3avdPQ/fZgUzTQAn+Wy7faKsYIYVccXoizRV 9QCDJZH22jImja6tr9pwC3SM+/MR5D3druL9Q3jliCBIOYVxtfbmWHsjo9Cb1S6ae7tM NDzkao24ki8znlqeMUQsn9U+GIMCuZ6GvoekAcJ2PN83eyvsnH2L3riEnd4m3FbOVETm QwtQuzzGvAeIwl5heuVQmaxXDg08ronsOJGAtfDw1sr/b2MKk/+vRKjslTMaJ3RKzX0T j4KA== X-Gm-Message-State: AJIora+gyuywPHf3QYdgl5i0e7fG8zUaZqeS/asvC3og1ZzyDMLL1Qdj gJv2aQleRvz77xxPWoy2g623AZKTCmBfwg== X-Google-Smtp-Source: ABdhPJyfTJ/prGzUJzsuS8HIOlarb9p3WwLN67rvQVxwlnghrLuD6hnImKF5tjblIsRSML8PHBwz6A== X-Received: by 2002:a17:906:3b87:b0:70d:3189:6aae with SMTP id u7-20020a1709063b8700b0070d31896aaemr8695065ejf.222.1655293653117; Wed, 15 Jun 2022 04:47:33 -0700 (PDT) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id s11-20020aa7d78b000000b0042bca34bd15sm9067640edq.95.2022.06.15.04.47.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jun 2022 04:47:32 -0700 (PDT) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Andrew Waterman , Philipp Tomsich , Christoph Muellner Subject: [PATCH v2 2/2] riscv-cores.def: Add T-Head XuanTie C906 Date: Wed, 15 Jun 2022 13:47:29 +0200 Message-Id: <20220615114729.826142-2-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220615114729.826142-1-christoph.muellner@vrull.eu> References: <20220615114729.826142-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_NUMSUBJECT, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Christoph Müllner This adds T-Head's XuanTie C906 to the list of known cores as "thead-c906". The C906 is shipped for quite some time (it is the core of the Allwinner D1). Note, that the tuning struct for the C906 is already part of GCC (it is also name "thead-c906"). gcc/ChangeLog: * config/riscv/riscv-cores.def (RISCV_CORE): Add "thead-c906". gcc/testsuite/ChangeLog: * gcc.target/riscv/mcpu-thead-c906.c: New test. Changes since v1: * Adding test case * Reword commit message Signed-off-by: Christoph Müllner --- gcc/config/riscv/riscv-cores.def | 2 ++ .../gcc.target/riscv/mcpu-thead-c906.c | 18 ++++++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index 60bcadbb034..dd97ece376f 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -44,4 +44,6 @@ RISCV_CORE("sifive-s76", "rv64imafdc", "sifive-7-series") RISCV_CORE("sifive-u54", "rv64imafdc", "sifive-5-series") RISCV_CORE("sifive-u74", "rv64imafdc", "sifive-7-series") +RISCV_CORE("thead-c906", "rv64imafdc", "thead-c906") + #undef RISCV_CORE diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c b/gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c new file mode 100644 index 00000000000..f579e7e2215 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ +/* { dg-options "-mcpu=thead-c906" { target { rv64 } } } */ +/* T-Head XuanTie C906 => rv64imafdc */ + +#if !((__riscv_xlen == 64) \ + && !defined(__riscv_32e) \ + && defined(__riscv_mul) \ + && defined(__riscv_atomic) \ + && (__riscv_flen == 64) \ + && defined(__riscv_compressed)) +#error "unexpected arch" +#endif + +int main() +{ + return 0; +}